CN102881564A - MOM (metal oxide metal) capacitor manufacturing method - Google Patents
MOM (metal oxide metal) capacitor manufacturing method Download PDFInfo
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- CN102881564A CN102881564A CN2012104049817A CN201210404981A CN102881564A CN 102881564 A CN102881564 A CN 102881564A CN 2012104049817 A CN2012104049817 A CN 2012104049817A CN 201210404981 A CN201210404981 A CN 201210404981A CN 102881564 A CN102881564 A CN 102881564A
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Abstract
The invention provides an MOM (metal oxide metal) capacitor manufacturing method. The MOM capacitor manufacturing method includes providing a semiconductor substrate; depositing an insulation medium layer on the semiconductor substrate; forming a first groove representing a first electrode diagram and a second groove representing a second electrode diagram in the insulation medium layer by the aid of two diagramming process; filling metal into the first groove and the second groove to form a first electrode and a second electrode. By the aid of the MOM capacitor manufacturing method, diagram distance smaller than a photoetching process restraint can be obtained, distance between finger-shaped electrode plates of the adjacent electrodes is greatly reduced, and accordingly, capacity of an MOM capacitor is improved while occupation area of the capacitor on a chip can be reduced.
Description
Technical field
The present invention relates to semiconductor integrated circuit and make the field, relate in particular to the manufacture method of a kind of metal-oxide-metal (metal-oxide-meter is called for short MOM) electric capacity.
Background technology
In semiconductor integrated circuit, be widely used with the integrated capacitance of circuit production on same chip.Its form mainly contains metal-insulator-metal type (metal-insulator-metal, be called for short MIM) and two kinds of MOM electric capacity, wherein, MIM electric capacity uses upper/lower layer metallic as capacitor plate, at least need use 2 layers of metal, its capacitance is mainly determined by the electric capacity area occupied, therefore, uses MIM electric capacity can cause that cost increases greatly in the occasion of the large electric capacity of needs; And MOM electric capacity adopt method that finger and lamination combine can be on the area of less the larger electric capacity of making capacity, therefore, the designer more favors this class electric capacity when the large capacity integrated capacitance of design.
MOM finger electric capacity is made two electrodes of electric capacity in same metal level, each electrode extends several finger-like pole plates, the finger-like pole plate of two electrodes is parallel to each other and places with interlaced form, and the inter-level dielectric with current layer between the finger-like pole plate that these are staggeredly placed forms MOM electric capacity as insulating barrier.In order to increase capacitance, among can also rotate to an angle with identical structure the upper strata metal that is produced on current MOM electric capacity or the lower metal and form the structure of lamination, the metal of same electrode different layers can be connected to form an integral body by via layer.A lamination MOM electric capacity like this comprises the electric capacity between layer capacitance and the upper lower metal layer, can further improve the capacitance of integrated capacitance.
Computing formula according to capacity plate antenna: capacitance=permittivity of vacuum * k * area/polar plate spacing.Be that capacitance is directly proportional with relative dielectric constant k and the metal polar plate area of insulating dielectric layer, and the distance between two-plate is inversely proportional to.Because in the special process, the k value is fixing, intermetallic will improve capacitance apart from being subjected to design rule and process technology limit if above-mentioned finger-like adds the electric capacity of laminated construction, can only increase capacitance by length or the quantity that increases the finger-like pole plate or the method that increases the laminated metal layer.The former will cause capacity area to increase, and the latter can make its occupied metal level increase and the rear end placement-and-routing of circuit is exerted an influence.Therefore, how can reduce again the shared chip area of electric capacity by a kind of effective means when improving the MOM capacitance, be the industry urgent problem.
Summary of the invention
The object of the present invention is to provide a kind of manufacture method of MOM electric capacity, the method is by using Dual graphing (double pattern) technique, form respectively two electrodes of metal-oxide-metal capacitor (MOM), thereby obtain less than spacing between the pole plate of design rule and photoetching process constraint.
For addressing the above problem, the invention provides the manufacture method of a kind of metal-oxide-metal capacitor (MOM), it is characterized in that, comprising:
A kind of manufacture method of MOM electric capacity, wherein, described MOM electric capacity comprises the first electrode and the second electrode, described the first electrode and the second electrode all adopt finger, formed by single-ended linking to each other of several finger-like pole plates that are parallel to each other respectively, described the first electrode is relative with the second electrode staggered, is arranged in layer dielectric; It is characterized in that described manufacture method comprises the steps:
The semiconductor substrate is provided;
Deposit insulating medium layer at described semiconductor base;
By the secondary image metallization processes, in described insulating medium layer, form respectively the first groove that represents the first electrode pattern and the second groove that represents the second electrode pattern;
In described the first groove and the second groove, fill metal, form the first electrode and the second electrode.
Preferably, forming the first groove that represents the first electrode pattern and the step that represents the second groove of the second electrode pattern in described insulating medium layer comprises:
A. at the hard mask dielectric layer of described insulating medium layer deposition;
B. at described hard mask dielectric layer coating the first photoresist layer, by photoetching, etching, described hard mask dielectric layer is carried out the first time graphically, utilize the first groove that forms at described hard mask dielectric layer to define the first electrode pattern;
C. remove residue the first photoresist layer, at described hard mask dielectric layer and insulating medium layer surface-coated the second photoresist layer, by photoetching, etching, it is graphical that described hard mask dielectric layer is carried out the second time, utilizes the second groove that forms at described hard mask dielectric layer in graphical for the second time to define the second electrode pattern;
D. remove residue the second photoresist layer, take through the hard mask dielectric layer behind the secondary image as mask, described insulating medium layer is carried out etching, form the first groove and the second groove.
Preferably, forming the first groove that represents the first electrode pattern and the step that represents the second groove of the second electrode pattern in described insulating medium layer comprises:
A. at described insulating medium layer coating the first photoresist layer, by photoetching, etching, described insulating medium layer is carried out the first time graphically, utilize the first ditch slot definition the first electrode pattern that forms at described insulating medium layer;
B. remove residue the first photoresist layer, be coated with the second photoresist layer at described insulating medium layer and substrate surface, by photoetching, etching, it is graphical that described insulating medium layer is carried out the second time, utilizes the second ditch slot definition the second electrode pattern that forms at described insulating medium layer in graphical for the second time;
C. remove residue the second photoresist layer.
The metal of preferably, filling in described the first groove and the second groove is copper.
Preferably, filling the employed technique of metallic copper in described the first groove and the second groove is to electroplate.
Preferably, utilize the plasma enhanced chemical vapor deposition technology to realize at described semiconductor base deposition insulating medium layer.
Preferably, in described groove, fill and also comprise behind the metal and utilize chemical Mechanical Polishing Technique to carry out planarisation step.
Preferably, described semiconductor base comprise substrate and be formed on front road device on the described substrate and the N layer after the road metal level, wherein, N is the integer more than or equal to zero.
The present invention makes the field with Dual graphing (double pattern) process application in MOM electric capacity, form respectively two electrodes of MOM electric capacity by the secondary image metallization processes, can obtain the figure spacing less than the photoetching process constraint, greatly reduce the distance between adjacent two electrode finger-like pole plates, thereby when improving the MOM capacitance, can reduce again the shared chip area of electric capacity.Understand from another angle, the manufacture method of the application of the invention, in the situation that realizes same capacitance, the area that electric capacity occupies is less, and the number of metal of perhaps using is still less.
Description of drawings
Fig. 1 is the structure vertical view of MOM electric capacity in the embodiment of the invention;
Fig. 2 is the schematic flow sheet of a preferred embodiment of MOM method for producing capacitor of the present invention
Fig. 3～17th, Fig. 1 dissects in order to explanation along AA ' direction and adopts manufacture method of the present invention to form the cross-sectional view of MOM electric capacity of the present invention.
Embodiment
For making content of the present invention more clear understandable, below in conjunction with Figure of description, content of the present invention is described further.Certainly the present invention is not limited to this specific embodiment, and the known general replacement of those skilled in the art also is encompassed in protection scope of the present invention.
The present invention utilizes schematic diagram that concrete structure and method have been carried out detailed statement, and when example of the present invention was described in detail in detail, for convenience of explanation, schematic diagram did not amplify according to general ratio is local, should be with this as limitation of the invention.
See also Fig. 1, Fig. 1 is the structure vertical view of MOM electric capacity in the embodiment of the invention.As shown in the figure, this MOM electric capacity comprises the first electrode 7 and the second electrode 8.The first electrode 7 was formed by many single-ended linking to each other of the finger-like pole plate 7a that is parallel to each other, and the second electrode 8 was formed by many single-ended linking to each other of the finger-like pole plate 8a that is parallel to each other.Described the first electrode 7 is staggered so that cross one another form is relative with the second electrode 8, and is arranged in same metal level, namely is produced on in the layer dielectric.The width of described the first electrode finger-like pole plate 7a less than the width of the distance between the adjacent finger-like pole plate of described the second electrode 8a and described the second electrode finger-like pole plate 8a less than the distance between the adjacent finger-like pole plate of described the first electrode 7a.In the present embodiment, the width of described the first electrode finger-like pole plate 7a is W
1, the distance between the adjacent finger-like pole plate of described the first electrode is W
3, the width of the finger-like pole plate 8a of described the second electrode is W
2, the distance between the adjacent finger-like pole plate of described the second electrode is W
4, the distance between the first electrode finger-like pole plate and adjacent the second electrode finger-like pole plate is W
5
Reach for convenience of description comparison, the layout size in the present embodiment is all take the layout design rules of 0.13um copper subsequent interconnection technique the second metal level as the basis.Although each manufacturer has slightly gap with regard to the related data of this Technology design rule, does not affect the elaboration for protection range of the present invention.
In traditional manufacturing process, the width W of above-mentioned the first electrode finger-like pole plate 7a
1Width W with the finger-like pole plate 8a of the second electrode
2All must be more than or equal to minimum design rule size 0.2um, the distance W between the adjacent finger-like pole plate of the first electrode
3, the distance W between the adjacent finger-like pole plate of the second electrode
4And the distance W between adjacent two electrode finger-like pole plates
5Must be more than or equal to minimum design rule size 0.21um.We can find out thus, if can reduce spacing between the adjacent two electrode finger-like pole plates by changing process, are W in the present embodiment
5, make it less than minimum design rule, just can increase capacitance, reach simultaneously and dwindle pitch, reduce the purpose of area.
Now by reference to the accompanying drawings 2 ~ 15, by a specific embodiment a kind of new manufacturing method that the present invention forms the described MOM electric capacity of Fig. 1 is elaborated.
Fig. 2 is the schematic flow sheet of a preferred embodiment of MOM method for producing capacitor of the present invention.In the present embodiment, the MOM method for producing capacitor comprises step S01～S07, and step S01～S07 is embodied by accompanying drawing 3-15 respectively, and accompanying drawing 3-15 is that MOM electric capacity shown in Figure 1 is along the cross-sectional view of AA ' direction.
See also Fig. 2, as shown in the figure, in this embodiment of the present invention, the MOM method for producing capacitor comprises the steps:
Step S01: see also Fig. 3, semiconductor substrate 1 be provided, described semiconductor base comprise substrate and be formed on front road device on the described substrate and the N layer after road metal level (not shown), wherein, N is the integer more than or equal to zero.When N was zero, described semiconductor base only comprised substrate and is formed on front road device on the described substrate.
Step S02: still consult Fig. 3, utilize plasma enhanced chemical vapor deposition (PECVD) deposition techniques insulating medium layer 2 at described semiconductor base 1, the material of described insulating medium layer can be silicon dioxide.
Step S03: still consult Fig. 3, utilize the hard mask dielectric layer 3 of plasma enhanced chemical vapor deposition (PECVD) deposition techniques on described insulating medium layer surface, the material of described hard mask dielectric layer can be silicon nitride.
Step S04 sees also Fig. 3 and Fig. 4, at first, at described hard mask dielectric layer 3 coatings the first photoresist layer 4, utilizes the first mask plate M
1Described photoresist is exposed, develops; Then take the photoresist after overexposure, development as mask, described hard mask dielectric layer 3 is carried out etching, realize that the first time of hard mask dielectric layer is graphical, utilize the first groove T that forms at described hard mask dielectric layer 3
1Define the first electrode pattern.The width of described the first groove is W
1, corresponding with the width of described the first electrode finger-like pole plate 7a, adopt in the present embodiment minimum design rule size 0.2um.Distance between adjacent two first grooves is W
3Distance between the adjacent finger-like pole plate with described the first electrode is corresponding, this distance is as long as satisfy more than or equal to minimum design rule size 0.21um in greater than the second electrode finger-like plate width, also adopt in the situation of minimum design rule size 0.2um in the second electrode finger-like plate width, as long as this distance is selected 0.44um more than or equal to 0.21um in the present embodiment.
Step S05 sees also Fig. 5, at first, removes remaining the first photoresist layer, then carries out the coating of the second photoresist layer 5 at described hard mask dielectric layer 3 and insulating medium layer 2 surfaces; Then consult Fig. 6 and Fig. 7, utilize the second mask plate M
2Described photoresist is exposed, develops, and take the photoresist after overexposure, development as mask, the described hard mask dielectric layer 3 of retaining after graphical through the first time is carried out etching, the second time of realizing hard mask dielectric layer is graphical, utilizes the second groove T that forms at described hard mask dielectric layer 3 in graphical for the second time
2Define the second electrode pattern.The width of described the second groove is W
2, corresponding with the width of described the second electrode finger-like pole plate 8a, adopt minimum design rule size 0.2um in the present embodiment.Distance between adjacent two second grooves is W
4, the distance between the adjacent finger-like pole plate with described the second electrode is corresponding, and this distance in the present embodiment, is specifically selected 0.44um as long as satisfy more than or equal to minimum design rule size 0.21um in greater than the first electrode finger-like plate width.For reaching preferably technique effect, the distance between the second groove and adjacent the first groove is W
5, corresponding with the distance between the second electrode finger-like pole plate and adjacent the first electrode finger-like pole plate, be specially in the present embodiment ((0.44-0.2)/2) um, i.e. 0.12um.Often, owing to be subject to the impact of technique, the inconsistent situation of distance between the second groove and adjacent the first groove also can occur, these situations also are interpreted as covereding within protection scope of the present invention.
Step S06, see also Fig. 8 and Fig. 9, remove residue the second photoresist layer, take through the hard mask dielectric layer 3 behind the secondary image as mask, described insulating medium layer is carried out etching, in described insulating medium layer, formed the first groove T that exposes representative first electrode pattern of substrate
3With the second groove T that represents the second electrode pattern
4
Step S07 sees also Figure 10, at first utilizes the physical vapor deposition (PVD) technology at described the first groove T
3With the second groove T
4Interior deposit and spread barrier layer (not shown), the material of described diffusion impervious layer can be TaN/Ta; Then, utilize electroplating technology to described the first groove T
3With the second groove T
4Carry out metal filledly, the metal of filling is copper; At last, utilize surface with chemical polishing technology that copper metal layer is carried out planarization, remove simultaneously the outer diffusion impervious layer of groove and hard mask dielectric layer 3, finally form the first electrode 7 and the second electrode 8.
Further, the present invention also provides another manufacture method, is with the difference of above-described embodiment, behind completing steps S02, directly at described insulating medium layer 2 coatings the first photoresist layer 4, sees also Figure 11 and Figure 12, utilizes the first mask plate M
1Described photoresist is exposed, develops; Then take the photoresist after overexposure, development as mask, described insulating medium layer is carried out etching, realize that the first time of insulating medium layer is graphical, utilize the first groove T that forms at described insulating medium layer 2
3Define the first electrode pattern.
Then, see also Figure 13, remove remaining the first photoresist layer, carry out the coating of the second photoresist layer 5 at described insulating medium layer 2 and substrate 1 surface again; Then see also Figure 14 and Figure 15, utilize the second mask plate M
2Described photoresist is exposed, develops, and take the photoresist after overexposure, development as mask, the described insulating medium layer 2 of retaining after graphical through the first time is carried out etching, the second time of realizing insulating medium layer is graphical, utilizes the second groove T that forms at described insulating medium layer 3 in graphical for the second time
4Define the second electrode pattern.
At last, can consult Figure 16 and Figure 17, at first remove remaining the second photoresist layer, the deposition that enters at last diffusion impervious layer, the filling of metallic copper and planarisation step finally realize the manufacturing of the first electrode 7 and the second electrode 8.
The employed mask plate of secondary imageization and alignment so are all same as the previously described embodiments in this embodiment, and therefore, resulting each dimension of picture is also consistent with above-described embodiment.
According to the figure transfer mechanism, from above-mentioned explanation, can find out, by the width W of these two the first electrode finger-like pole plate 7a that embodiment finally obtained
1Be 0.2 um, the width W of the finger-like pole plate 8a of the second electrode
2Be 0.2 um, the distance W between adjacent two electrode finger-like pole plates
5Be 0.12um.In these two embodiment, distance between adjacent two the finger-like pole plates of same electrode has all been selected 0.44um, much larger than minimum design rule size 0.21um, greatly alleviate etching pressure, certainly, this numerical value among these two embodiment can be less, equals in theory 0.21um and get final product, so the distance W between final resulting adjacent two electrode finger-like pole plates
5Also can be less.
According to the computing formula of capacity plate antenna, capacitance=permittivity of vacuum * k * area/polar plate spacing.In the situation that all adopts the minimum design rule size, utilize that distance between adjacent two electrode finger-like pole plates that conventional fabrication processes obtains is minimum to be 0.21um, and in these two embodiment, using the distance between adjacent two electrode finger-like pole plates that manufacture method of the present invention obtains only to be 0.12um, the capacitance density of latter's unit are is the former 2.05 times.
Although the present invention discloses as above with preferred embodiment; so it is not to limit the present invention; have in the technical field under any and usually know the knowledgeable; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking claims person of defining.
Claims (8)
1. the manufacture method of a MOM electric capacity, wherein, described MOM electric capacity comprises the first electrode and the second electrode, described the first electrode and the second electrode all adopt finger, formed by single-ended linking to each other of several finger-like pole plates that are parallel to each other respectively, described the first electrode is relative with the second electrode staggered, is arranged in layer dielectric;
It is characterized in that described manufacture method comprises the steps:
The semiconductor substrate is provided;
Deposit insulating medium layer at described semiconductor base;
By the secondary image metallization processes, in described insulating medium layer, form respectively the first groove that represents the first electrode pattern and the second groove that represents the second electrode pattern;
In described the first groove and the second groove, fill metal, form the first electrode and the second electrode.
2. the manufacture method of a kind of MOM electric capacity as claimed in claim 1 is characterized in that, forms the first groove that represents the first electrode pattern and the step that represents the second groove of the second electrode pattern and comprise in described insulating medium layer:
A. at the hard mask dielectric layer of described insulating medium layer deposition;
B. at described hard mask dielectric layer coating the first photoresist layer, by photoetching, etching, described hard mask dielectric layer is carried out the first time graphically, utilize the first groove that forms at described hard mask dielectric layer to define the first electrode pattern;
C. remove residue the first photoresist layer, at described hard mask dielectric layer and insulating medium layer surface-coated the second photoresist layer, by photoetching, etching, it is graphical that described hard mask dielectric layer is carried out the second time, utilizes the second groove that forms at described hard mask dielectric layer in graphical for the second time to define the second electrode pattern;
D. remove residue the second photoresist layer, take through the hard mask dielectric layer behind the secondary image as mask, described insulating medium layer is carried out etching, form the first groove and the second groove.
3. the manufacture method of a kind of MOM electric capacity as claimed in claim 1 is characterized in that, forms the first groove that represents the first electrode pattern and the step that represents the second groove of the second electrode pattern and comprise in described insulating medium layer:
A. at described insulating medium layer coating the first photoresist layer, by photoetching, etching, described insulating medium layer is carried out the first time graphically, utilize the first ditch slot definition the first electrode pattern that forms at described insulating medium layer;
B. remove residue the first photoresist layer, be coated with the second photoresist layer at described insulating medium layer and substrate surface, by photoetching, etching, it is graphical that described insulating medium layer is carried out the second time, utilizes the second ditch slot definition the second electrode pattern that forms at described insulating medium layer in graphical for the second time;
C. remove residue the second photoresist layer.
4. the manufacture method of a kind of MOM electric capacity as claimed in claim 1 is characterized in that, the metal of filling in described the first groove and the second groove is copper.
5. the manufacture method of a kind of MOM electric capacity as claimed in claim 4 is characterized in that, filling the employed technique of metallic copper in described the first groove and the second groove is to electroplate.
6. the manufacture method of a kind of MOM electric capacity as claimed in claim 1 is characterized in that, utilizes the plasma enhanced chemical vapor deposition technology to realize at described semiconductor base deposition insulating medium layer.
7. the manufacture method of a kind of MOM electric capacity as claimed in claim 1 is characterized in that, also comprises behind the filling metal in described groove and utilizes chemical Mechanical Polishing Technique to carry out planarisation step.
8. the manufacture method of a kind of MOM electric capacity as claimed in claim 1 is characterized in that, described semiconductor base comprise substrate and be formed on front road device on the described substrate and the N layer after the road metal level, wherein, N is the integer more than or equal to zero.
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| CN111129004A (en) * | 2019-12-20 | 2020-05-08 | 芯创智（北京）微电子有限公司 | Layout design method and layout structure of capacitor based on pmos tube and metal layer |
| CN114783998A (en) * | 2022-06-16 | 2022-07-22 | 合肥晶合集成电路股份有限公司 | Integrated circuit and forming method thereof |
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| CN102437023A (en) * | 2011-11-30 | 2012-05-02 | 上海华力微电子有限公司 | Method for manufacturing multilayer metal-oxide-metal capacitor |
| CN102446703A (en) * | 2010-10-14 | 2012-05-09 | 中芯国际集成电路制造(上海)有限公司 | Dual patterning method |
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| CN111129004A (en) * | 2019-12-20 | 2020-05-08 | 芯创智（北京）微电子有限公司 | Layout design method and layout structure of capacitor based on pmos tube and metal layer |
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