CN102779734A - Manufacturing method of multi-layer metal-silicon oxide-metal capacitor - Google Patents

Manufacturing method of multi-layer metal-silicon oxide-metal capacitor Download PDF

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CN102779734A
CN102779734A CN2012102931827A CN201210293182A CN102779734A CN 102779734 A CN102779734 A CN 102779734A CN 2012102931827 A CN2012102931827 A CN 2012102931827A CN 201210293182 A CN201210293182 A CN 201210293182A CN 102779734 A CN102779734 A CN 102779734A
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silicon oxide
metal
layer
capacitor
silica
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CN2012102931827A
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毛智彪
周军
张月雨
王丹
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Shanghai Huali Microelectronics Corp
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Shanghai Huali Microelectronics Corp
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Abstract

The invention discloses a manufacturing method of a multi-layer metal-silicon oxide-metal capacitor. The manufacturing method comprises the steps of: firstly forming a mixing layer of a low-k-value medium and a high-k-value silicon oxide; conducting photoetching of a convention process to form a metallic channel and a capacitance metallic channel connected with each other in the low-k-value medium and high-k-value silicon oxide respectively, and filling metal in the channels; repeating the steps so as to realize a multi-layer MOM (Mass Optical Memory) capacitor structure in the region of the high-k-value silicon oxide and realize the interconnection of low k values in other regions, wherein the high-k-value silicon oxide is formed by adopting the mode of PECVD (Plasma Enhanced Chemical Vapor Deposition) and nitrogen-contained gas cyclic processing, and silicon-hydrogen bonds in silicon oxide can be removed effectively. Compared with a conventional single-k value medium structure, the manufacturing method provided by the invention has the advantages that the capacitance of a capacitor in a high layer can be improved effectively, the electrical characteristics of breakdown voltage, leakage current and the like of an MOM capacitor are improved, and the electricity uniformity of all the devices is improved.

Description

The manufacture method of multiple layer metal-silica-metal capacitor
Technical field
The present invention relates to technical field of manufacturing semiconductors, relate in particular to the manufacture method of a kind of multiple layer metal-silica-metal capacitor.
Background technology
Capacitor is the important composition unit in the integrated circuit, extensively applies in the chips such as memory, microwave, radio frequency, smart card, high pressure and filtering.The capacitor constructions that in chip, widely adopts is metal-insulator-metal type (MIM, Metal-Insulator-Metal) capacitor that is parallel to silicon chip substrate.Wherein metal is that manufacture craft is prone to the copper compatible mutually with metal interconnected technology, aluminium etc., and insulator then is the dielectric substance of high-ks (k) such as silicon nitride, silica.The performance of improving the high-k dielectric material is one of main method that improves capacitor performance.
Plasma enhanced chemical vapor deposition method (PECVD, Plasma Enhanced Chemical Vapor Deposition) is because of the low thin film deposition that is widely used in the metal interconnected technology of its depositing temperature.Utilize residual a large amount of si-h bond (Si-H) in the silicon nitride film that the PECVD method makes; Make and have more electric charge in it; This causes the uniformity of this silicon nitride film aspect electrical thickness relatively poor, and the MIM capacitor that utilizes this silicon nitride film to make also can be corresponding relatively poor aspect each electrical characteristics such as puncture voltage, leakage current.Chinese patent CN101577227A has introduced a kind of method of improving aluminium-silicon nitride-tantalum thing capacitor performance; Handle this silicon nitride film through oxygen-containing gas; Can reduce si-h bond residual in the silicon nitride film effectively, thereby improve the performance of capacitor effectively.
Yet along with the continuous progress of semiconductor integrated circuit manufacturing technology, performance also is accompanied by device miniaturization, microminiaturized process when constantly promoting.More and more advanced processing procedure requires in as far as possible little zone, to realize device as much as possible, obtains high as far as possible performance.Therefore, how under limited area, to obtain highdensity electric capacity and become a problem that haves a great attraction.And do not obtain highdensity electric capacity among the above-mentioned Chinese patent CN101577227A.
(MOM, Metal-Oxide-Metal) capacitor is owing to realizing in less chip area that big electric capacity becomes the focus of present research perpendicular to the metal-oxide-metal of silicon chip substrate.Oxide wherein is generally silica, but in practical application, also can comprise the dielectric substance of high-ks (k) such as silicon nitride.MOM capacitor fabrication technology and metal interconnected technology compatible relatively good, the outer company of capacitor two-stage can realize with metal interconnected technology synchronously.But, utilize PECVD to make silicon oxide film and also have a large amount of si-h bond (Si-H) and remain in the silicon oxide film, thereby influence the performance of MOM capacitor.
Chinese patent CN111654.1 has introduced a kind of process of the MOM of making capacitor.Silica wherein adopts traditional P ECVD technology to make.A large amount of si-h bond (Si-H) remains in the silicon oxide film.Though the silica that this manufacture method is made conventional P ECVD technology has carried out the oxygen-containing gas processing, to reduce residual si-h bond in the silicon oxide film.Yet still residual in the silicon oxide film of this method preparation have a large amount of si-h bond (Si-H), can not satisfy the demand of high-performance MOM capacitor.
Therefore, be necessary further to improve the performance and the performance that improves the MOM capacitor of high-k dielectric material, thereby satisfy of the requirement of constantly microminiaturized chip high performance capacitors.
Summary of the invention
The object of the present invention is to provide the manufacture method of a kind of multiple layer metal-silica-metal capacitor, to improve the performance of MOM capacitor.
For addressing the above problem, the present invention proposes the manufacture method of a kind of multiple layer metal-silica-metal capacitor, comprises the steps:
Step 1 provides substrate;
Step 2, the mode of handling the circulation of two steps through plasma enhanced chemical vapor deposition and nitrogenous gas forms silicon oxide layer on said substrate;
Step 3 is carried out photoetching and etching to said silicon oxide layer, removes the silicon oxide layer outside the MOM capacitor regions;
Step 4; The low K value dielectric layer of deposition; Said low K value dielectric layer covers the silicon oxide layer of said substrate and said MOM capacitor regions, and removes the unnecessary low k value dielectric layer of the silicon oxide layer exceed the MOM capacitor regions with cmp, forms the mixed layer that hangs down k value dielectric layer and silicon oxide layer;
Step 5 is carried out photoetching and etching to the mixed layer of said low k value dielectric layer and silicon oxide layer, in said low K value dielectric layer and said silicon oxide layer, forms interconnecting metal groove and electric capacity metallic channel respectively;
Step 6 is filled metal in said interconnecting metal groove and electric capacity metallic channel;
Repeating step 2 is to step 6.
Optional, the reacting gas that said plasma enhanced chemical vapor deposition adopts comprises silane and nitrous oxide.
Optional; The flow of said silane is between 500sccm to 600sccm; The flow of said nitrous oxide is between 9000sccm to 15000sccm, and the flow-rate ratio of silane and nitrous oxide is between the 1:15 to 1:30, and rate of film build is between 1500 nm/minute to 5000 nm/minute.
Optional, said nitrogenous gas comprises nitric oxide, nitrous oxide or nitrogen.
Optional, the nitrogenous gas flow that said nitrogenous gas processing is adopted is between 2000sccm to 6000sccm, and treatment temperature is between 300 degrees centigrade to 600 degrees centigrade.
Optional, said mode through plasma reinforced chemical vapour deposition and nitrogenous gas processing two steps circulation forms in the process of silica, and the silicon oxide thickness of each deposition is 1 nanometer to 10 nanometer.
Compared with prior art, the present invention is through forming the mixed layer of low k value medium and high k value silica earlier; Utilize the photoetching etching of traditional handicraft in low K value medium and high k value silica, to form interconnecting metal groove and electric capacity metallic channel respectively again, and in groove, fill metal; Repeat above-mentioned steps and realized multilayer MOM capacitance structure, realize low k value interconnection in other zones in high k value region of silicon oxide.Wherein, the mode that the formation of high k value silica adopts PECVD deposition and nitrogenous gas cycle of treatment to carry out can effectively be removed the si-h bond in the silica.Compare with traditional single k value dielectric structure, the present invention can effectively improve the electric capacity of layer inner capacitor, has improved each electrical characteristics such as puncture voltage, leakage current of MOM capacitor again, and the electricity uniformity between each device.Through adopting the vertical capacitor structure, can also effectively improve capacitor density, thereby in less chip area, realize big electric capacity.
Description of drawings
Fig. 1 forms the method flow diagram of multilayer MOM electric capacity for the embodiment of the invention;
Fig. 2 A～Fig. 2 F is the corresponding device architecture sketch map of each step of the method for embodiment of the invention formation multilayer MOM electric capacity.
Embodiment
Below in conjunction with accompanying drawing and specific embodiment the manufacture method of the multiple layer metal-silica-metal capacitor of the present invention's proposition is done further explain.According to following explanation and claims, advantage of the present invention and characteristic will be clearer.What need explanation is, accompanying drawing all adopts the form of simplifying very much and all uses non-ratio accurately, only is used for conveniently, the purpose of the aid illustration embodiment of the invention lucidly.
Core concept of the present invention is, the manufacture method of a kind of multiple layer metal-silica-metal capacitor is provided, and this method is through forming the mixed layer of low k value medium and high k value silica earlier; Utilize the photoetching etching of traditional handicraft in low K value medium and high k value silica, to form interconnecting metal groove and electric capacity metallic channel respectively again, and in groove, fill metal; Repeat above-mentioned steps and realized multilayer MOM capacitance structure, realize low k value interconnection in other zones in high k value region of silicon oxide.Wherein, the mode that the formation of high k value silica adopts PECVD deposition and nitrogenous gas cycle of treatment to carry out can effectively be removed the si-h bond in the silica.Compare with traditional single k value dielectric structure, the present invention can effectively improve the electric capacity of layer inner capacitor, has improved each electrical characteristics such as puncture voltage, leakage current of MOM capacitor again, and the electricity uniformity between each device.Through adopting the vertical capacitor structure, can also effectively improve capacitor density, thereby in less chip area, realize big electric capacity.
Please refer to Fig. 1 and Fig. 2 A to Fig. 2 F; Wherein, Fig. 1 is the method flow diagram of embodiment of the invention formation multilayer MOM electric capacity, and Fig. 2 A～Fig. 2 F is the corresponding device architecture sketch map of each step of the method for embodiment of the invention formation multilayer MOM electric capacity, in conjunction with Fig. 1 and Fig. 2 A to Fig. 2 F; The manufacture method of multiple layer metal-silica provided by the invention-metal capacitor comprises the steps:
Step 1: substrate 101 is provided; The substrate 101 that is provided in the present embodiment can be simple silicon substrate, also can form the silicon substrate of semiconductor device for the surface;
Step 2, the mode of handling the circulation of two steps through plasma enhanced chemical vapor deposition and nitrogenous gas forms silicon oxide layer 102 on said substrate 101, shown in Fig. 2 A; In order to improve silicon oxide film that conventional P ECVD method makes in the uniformity aspect the electrical thickness; The mode that adopts PECVD method cvd silicon oxide and nitrogenous gas cycle of treatment to carry out among the present invention; After promptly depositing one deck silica, carry out nitrogenous gas subsequently and handle, and then cvd silicon oxide; Carry out nitrogenous gas again and handle, so circulation; The silicon oxide thickness of each deposition is 1 nanometer to 10 nanometer, until the silicon oxide layer 102 of deposition reaches till the thickness that needs in the technology.
Wherein, The reacting gas that PECVD adopts comprises silane and nitrous oxide; The process conditions of reaction are that the flow of silane is between 500sccm to 600sccm; The flow of nitrous oxide is between 9000sccm to 15000sccm, and the flow-rate ratio of silane and nitrous oxide is between the 1:15 to 1:30, and rate of film build is between 1500 nm/minute to 5000 nm/minute; Nitrogenous gas comprises nitric oxide, nitrous oxide or nitrogen; And be preferably nitrogen; The nitrogenous gas flow that the nitrogenous gas processing is adopted is between 2000sccm to 6000sccm, and treatment temperature is between 300 degrees centigrade to 600 degrees centigrade.
And then silica through the deposition skim also carries out the nitrogenous gas processing to it, can remove the si-h bond Si-H in the silicon oxide film fully, and so circulation can obtain the good silica of electrical thickness evenness.
Step 3 is carried out photoetching and etching to said silicon oxide layer 102, removes the silicon oxide layer outside the MOM capacitor regions; Device architecture figure after this step is accomplished is shown in Fig. 2 B;
Step 4; The low K value dielectric layer of deposition; Said low K value dielectric layer covers the silicon oxide layer 102 of said substrate 101 and said MOM capacitor regions; And remove the unnecessary low k value dielectric layer of the silicon oxide layer 102 exceed the MOM capacitor regions with cmp, form the mixed layer of low k value dielectric layer 103 and silicon oxide layer 102; Device architecture sketch map after cmp is handled is shown in Fig. 2 C; Said low k value dielectric layer 103 adopts chemical vapour deposition (CVD) to form, and its dielectric constant is 2～3; Certainly said low k value dielectric layer 103 can also adopt spin coating process to form.
Step 5 is carried out photoetching and etching to the mixed layer of said low k value dielectric layer 103 and silicon oxide layer 102, and formation interconnecting metal groove 200 and electric capacity metallic channel 300 in said low K value dielectric layer 103 and said silicon oxide layer 102 respectively are shown in Fig. 2 D; Wherein, electric capacity metallic channel 300 is used for the capacitor plate of follow-up formation multilayer MOM electric capacity; Electric capacity metallic channel 300 can evenly be offered a plurality of, and the degree of depth of electric capacity metallic channel 300 is less than the thickness of silicon oxide layer 102.Interconnecting metal groove 200 is used for follow-up formation interconnection, and its degree of depth can be identical with electric capacity metallic channel 300, also can adjust number, size, the degree of depth of interconnecting metal groove 200 according to the actual process demand.
Step 6 is filled metal in said interconnecting metal groove 200 and electric capacity metallic channel 300; Device architecture after this step is accomplished is shown in Fig. 2 E; Particularly, this step is included in processing steps such as the diffusion impervious layer deposition, copper plating, copper metal layer cmp of the copper that carries out copper wiring technique in interconnecting metal groove 200 and the electric capacity metallic channel 300, accomplishes copper and fills.
Then, repeating step 2 is realized multilayer MOM capacitance structure in high k value region of silicon oxide, shown in Fig. 2 F to step 6; Particularly, may further comprise the steps: the mode of at first handling the circulation of two steps at the body structure surface shown in Fig. 2 E through plasma enhanced chemical vapor deposition and nitrogenous gas forms silicon oxide layer; Then said silicon oxide layer is carried out photoetching and etching, remove the silicon oxide layer outside the MOM capacitor regions; Deposition is hanged down K value dielectric layer then; Said low K value dielectric layer covers the silicon oxide layer of said substrate and said MOM capacitor regions; And remove the unnecessary low k value dielectric layer of the silicon oxide layer exceed the MOM capacitor regions with cmp, form the mixed layer that hangs down k value dielectric layer and silicon oxide layer; Next the mixed layer to said low k value dielectric layer and silicon oxide layer carries out photoetching and etching; In said low K value dielectric layer and said silicon oxide layer, form interconnecting metal groove and electric capacity metallic channel respectively; Wherein, The electric capacity metallic channel is used for follow-up formation capacitor plate, and corresponding with the position of electric capacity metallic channel among Fig. 2 D, and the interconnecting metal groove is used to form interconnection; In interconnecting metal groove and electric capacity metallic channel, fill metal at last, thereby realize multilayer MOM capacitance structure, realize low K value interconnection in other zones in high K value region of silicon oxide.
Certainly, also can be as required once more or repeatedly repeating step 2 to 6 until reaching the required MOM electric capacity number of plies.
In sum, the invention provides the manufacture method of a kind of multiple layer metal-silica-metal capacitor, this method is through forming the mixed layer of low k value medium and high k value silica earlier; Utilize the photoetching etching of traditional handicraft in low K value medium and high k value silica, to form interconnecting metal groove and electric capacity metallic channel respectively again, and in groove, fill metal; Repeat above-mentioned steps and realized multilayer MOM capacitance structure, realize low k value interconnection in other zones in high k value region of silicon oxide.Wherein, the mode that the formation of high k value silica adopts PECVD deposition and nitrogenous gas cycle of treatment to carry out can effectively be removed the si-h bond in the silica.Compare with traditional single k value dielectric structure, the present invention can effectively improve the electric capacity of layer inner capacitor, has improved each electrical characteristics such as puncture voltage, leakage current of MOM capacitor again, and the electricity uniformity between each device.Through adopting the vertical capacitor structure, can also effectively improve capacitor density, thereby in less chip area, realize big electric capacity.
Obviously, those skilled in the art can carry out various changes and modification to invention and not break away from the spirit and scope of the present invention.Like this, belong within the scope of claim of the present invention and equivalent technologies thereof if of the present invention these are revised with modification, then the present invention also is intended to comprise these changes and modification interior.

Claims (6)

1. the manufacture method of multiple layer metal-silica-metal capacitor is characterized in that, comprises the steps:
Step 1 provides substrate;
Step 2, the mode of handling the circulation of two steps through plasma enhanced chemical vapor deposition and nitrogenous gas forms silicon oxide layer on said substrate;
Step 3 is carried out photoetching and etching to said silicon oxide layer, removes the silicon oxide layer outside the MOM capacitor regions;
Step 4; The low K value dielectric layer of deposition; Said low K value dielectric layer covers the silicon oxide layer of said substrate and said MOM capacitor regions, and removes the unnecessary low k value dielectric layer of the silicon oxide layer exceed the MOM capacitor regions with cmp, forms the mixed layer that hangs down k value dielectric layer and silicon oxide layer;
Step 5 is carried out photoetching and etching to the mixed layer of said low k value dielectric layer and silicon oxide layer, in said low K value dielectric layer and said silicon oxide layer, forms interconnecting metal groove and electric capacity metallic channel respectively;
Step 6 is filled metal in said interconnecting metal groove and electric capacity metallic channel; Repeating step 2 is to step 6.
2. the manufacture method of multiple layer metal-silica as claimed in claim 1-metal capacitor is characterized in that, the reacting gas that said plasma enhanced chemical vapor deposition adopts comprises silane and nitrous oxide.
3. the manufacture method of multiple layer metal-silica as claimed in claim 2-metal capacitor; It is characterized in that; The flow of said silane is between 500sccm to 600sccm; The flow of said nitrous oxide is between 9000sccm to 15000sccm, and the flow-rate ratio of silane and nitrous oxide is between the 1:15 to 1:30, and rate of film build is between 1500 nm/minute to 5000 nm/minute.
4. the manufacture method of multiple layer metal-silica as claimed in claim 1-metal capacitor is characterized in that said nitrogenous gas comprises nitric oxide, nitrous oxide or nitrogen.
5. the manufacture method of multiple layer metal-silica as claimed in claim 1-metal capacitor; It is characterized in that; The nitrogenous gas flow that said nitrogenous gas processing is adopted is between 2000sccm to 6000sccm, and treatment temperature is between 300 degrees centigrade to 600 degrees centigrade.
6. the manufacture method of multiple layer metal-silica as claimed in claim 1-metal capacitor; It is characterized in that; Said mode through plasma reinforced chemical vapour deposition and nitrogenous gas processing two steps circulation forms in the process of silica, and the silicon oxide thickness of each deposition is 1 nanometer to 10 nanometer.
CN2012102931827A 2012-08-16 2012-08-16 Manufacturing method of multi-layer metal-silicon oxide-metal capacitor Pending CN102779734A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115819986A (en) * 2022-12-06 2023-03-21 广东石成科技有限公司 Capacitor filling composite material and preparation method thereof

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030001188A1 (en) * 2001-06-27 2003-01-02 Nakagawa Osamu Samuel High-dielectric constant metal-insulator metal capacitor in VLSI multi-level metallization systems
CN1855374A (en) * 2005-04-18 2006-11-01 联华电子股份有限公司 Grid dielectric layer and its formation
CN102437023A (en) * 2011-11-30 2012-05-02 上海华力微电子有限公司 Method for manufacturing multilayer metal-oxide-metal capacitor
CN102437024A (en) * 2011-11-30 2012-05-02 上海华力微电子有限公司 Method for manufacturing multilayer metal-silicon oxide-metal (MOM) capacitor

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030001188A1 (en) * 2001-06-27 2003-01-02 Nakagawa Osamu Samuel High-dielectric constant metal-insulator metal capacitor in VLSI multi-level metallization systems
CN1855374A (en) * 2005-04-18 2006-11-01 联华电子股份有限公司 Grid dielectric layer and its formation
CN102437023A (en) * 2011-11-30 2012-05-02 上海华力微电子有限公司 Method for manufacturing multilayer metal-oxide-metal capacitor
CN102437024A (en) * 2011-11-30 2012-05-02 上海华力微电子有限公司 Method for manufacturing multilayer metal-silicon oxide-metal (MOM) capacitor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115819986A (en) * 2022-12-06 2023-03-21 广东石成科技有限公司 Capacitor filling composite material and preparation method thereof
CN115819986B (en) * 2022-12-06 2023-08-22 广东石成科技有限公司 Capacitance filling composite material and preparation method thereof

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Application publication date: 20121114