JP2010219229A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device that can suppress an increase in contact resistance between a lower electrode and a via interconnect and has a capacitive element, and a method of manufacturing the same. <P>SOLUTION: The semiconductor device includes the capacitive element formed on a semiconductor substrate 101 and having the lower electrode 110, a dielectric film 120, and an upper electrode 130. The lower electrode 110 of the capacitive element has a metal film 111 which is, for example, a Ti film, and TiN film 113 formed on the metal film 111. The semiconductor device further includes an insulating film 142 covering the capacitive element, and the via interconnect 150 penetrating the insulating film 142 to come into contact with the TiN film 113 of the lower electrode 110. The TiN film 113 is preferably &lt;30 nm thick. On at least a part of a surface of the Ti film 111, a nitride layer 112 is formed by nitriding the Ti film 111 to be interposed between the via interconnect 150 and the Ti film 111. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  The present invention relates to a semiconductor device having an MIM capacitor and a method for manufacturing the same.

  A semiconductor integrated circuit includes various passive elements such as capacitance elements on the same substrate as active elements such as transistors. 2. Description of the Related Art In recent years, with increasing performance and miniaturization of portable communication devices such as mobile phones, the capacitance elements provided in semiconductor integrated circuits are required to have higher capacity and higher performance. Generally, such a capacitance element has a lower electrode-dielectric film-upper electrode. A metal-insulator-metal (MIM) capacitor using a metal for each electrode has a small parasitic capacitance and parasitic resistance, and is suitable for realizing high performance of the capacitor.

  In order to increase the capacity and performance of the MIM capacitor, various studies have been made regarding the selection of a dielectric film material in consideration of the dielectric constant and the reduction in thickness. At the same time, various studies have been made on metal electrodes. The metal electrode is generally formed from a material that does not interact with the dielectric film. For example, an MIM capacitor element in which both the lower electrode and the upper electrode are made of titanium nitride (TiN) is known.

  In addition, when aluminum or titanium is used as an electrode of a capacitor element, in the process of forming a metal wiring connected to the electrode, the fluorine used in the process reacts with aluminum or titanium, thereby reducing the contact resistance with the metal wiring. It is known that it can be increased.

  In a capacitive element using a lower electrode made of TiN, when the thickness of the TiN film is increased, the unevenness of the TiN surface tends to increase. When irregularities are formed on the lower electrode, the thickness of the dielectric film between the upper electrode and the lower electrode is reduced by the convex portion of the lower electrode. Thus, the local thinning of the dielectric film is a factor that reduces the reliability of the capacitive element.

  A structure in which a TiN film is laminated on a metal film such as a Ti film is also known as a lower electrode.

JP-A-10-209272 JP 2003-273217 A

I. Kume et al., “High Performance SiN-MIM Decoupling Capacitors with Surface-smoothed Bottom Electrodes for High-speed MPUs”, Extended Abstracts of 2006 International Conference on Solid State Devices and Materials, 2006, p.1026-1027 S. Jeannot et al., “Toward next high performances MIM generation: up to 30fF / μm2 with 3D architecture and high-k materials”, Technical digest of International Electron Devices Meeting 2007, December 2007, p.997-1000

  After forming the capacitive element, when forming a contact hole reaching the lower electrode in the insulating film covering the capacitive element, the metal layer under the TiN film reacts with the via wiring deposition gas to contact The problem of increased resistance arises.

  According to one aspect, a semiconductor device including a capacitive element having a lower electrode, a dielectric film, and an upper electrode is provided. The lower electrode of the capacitive element has a metal film and a TiN film formed on the metal film. The semiconductor device further includes an insulating film that covers the capacitive element, and via wiring that contacts the TiN film of the lower electrode through the insulating film. A nitride layer formed by nitriding the metal film of the lower electrode is formed on at least a part of the surface of the metal film so as to be interposed between the via wiring and the Ti film.

  According to another aspect, a method for manufacturing a semiconductor device including a capacitive element is provided. The method includes a step of forming a metal film on a semiconductor substrate, a step of forming a TiN film on the metal film, and a step of forming a dielectric film and a conductive film on the TiN film. . The method further includes a step of nitriding the metal film to form a nitride layer on the surface of the metal film. The step of forming the nitride layer can be performed on the surface of the metal film after the metal film is formed. The step of forming the nitride layer may be performed on the surface of the metal film exposed by the via opening after the formation of the contact via opening to the TiN film and the metal film.

  The disclosed technique makes it possible to provide a semiconductor device having a capacitive element capable of suppressing an increase in contact resistance between the lower electrode and the via wiring.

It is sectional drawing which shows the semiconductor device which has a MIM capacitive element according to 1st Embodiment. It is a cross-sectional photograph which shows suppression of the unevenness | corrugation of the lower electrode surface. It is a figure which compares the lower electrode contact resistance with / without NH ₃ plasma treatment. FIG. 2 is a cross-sectional view showing a method for manufacturing the semiconductor device of FIG. 1. FIG. 2 is a cross-sectional view showing a method for manufacturing the semiconductor device of FIG. 1. FIG. 2 is a cross-sectional view showing a method for manufacturing the semiconductor device of FIG. 1. It is sectional drawing which shows the semiconductor device which has a MIM capacitive element according to 2nd Embodiment. FIG. 8 is a cross-sectional view showing a method for manufacturing the semiconductor device of FIG. 7. FIG. 8 is a cross-sectional view showing a method for manufacturing the semiconductor device of FIG. 7. FIG. 8 is a cross-sectional view showing a method for manufacturing the semiconductor device of FIG. 7.

  Hereinafter, embodiments will be described in detail with reference to the accompanying drawings.

  First, a semiconductor device having the capacitive element 100 according to the first embodiment will be described with reference to FIG. Here, an MIM capacitor element using metal layers for the upper electrode and the lower electrode will be described as an example. However, the upper electrode is not limited to a metal layer, and may be, for example, a Si layer doped with impurities.

  The MIM capacitor element 100 is formed on the interlayer insulating film 102 laminated on the semiconductor substrate 101. Although it does not specifically limit in the semiconductor substrate 101, For example, semiconductor elements, such as a transistor, are formed. The interlayer insulating film 102 includes a lower layer wiring 103 made of, for example, copper (Cu) or aluminum (Al).

  The MIM capacitor element 100 also includes a diffusion preventive film 104 for the conductive material of the lower layer wiring formed on the interlayer insulating film 102 and an insulating film 105 formed on the diffusion preventive film 104 as necessary. . The diffusion prevention film 104 can be, for example, a silicon carbide (hereinafter referred to as SiC) film having a thickness of about 70 nm. The insulating film 105 can be, for example, a silicon oxide (hereinafter referred to as SiO) film having a thickness of about 100 nm.

A lower electrode 110, a dielectric film 120, and an upper electrode 130 of the MIM capacitor element 100 are formed on the insulating film 105 as necessary. The lower electrode 110 includes, in order from the lower layer side, a Ti film 111, a nitride layer 112 that is the surface of the Ti film 111 that has been nitrided by ammonia (NH ₃ ) plasma treatment, and the TiN film 113. The Ti film 111 is typically formed by sputtering, and has a thickness of, for example, 80 nm including the surface nitride layer 112. The TiN film 113 is typically formed by sputtering to a thickness of 10-30 nm so as not to have columnar crystals. The dielectric film 120 typically includes SiO or silicon nitride (hereinafter referred to as SiN), and the thickness is determined so as to satisfy a desired capacitance value and reliability of the MIM capacitor element. For example, the dielectric film 120 may be a 40 nm thick SiO film. However, the dielectric film 120 may have other materials such as a high dielectric constant dielectric, or a combination thereof with SiO and / or SiN. The upper electrode 130 is not particularly limited, and may be a TiN film having a thickness of 100 nm, for example.

  The MIM capacitor element 100 further includes an etching stopper film 141 formed on the upper electrode 130, an interlayer insulating film 142 covering the stacked structure of the upper electrode 130 / dielectric film 120 / lower electrode 110, and an interlayer insulating film 142. The via wiring 150 is formed. Further, the semiconductor device has one or more upper layer wirings (not shown) for connecting the MIM capacitor element 100 to various semiconductor elements and / or electric circuits on the interlayer insulating film 142 and the via wiring 150. .

  The etching stopper film 141 is a film that functions as an etching stopper in an etching process for forming a via opening for the via wiring 150, and preferably has the same material as the diffusion prevention film 104, for example, SiC. The interlayer insulating film 142 can be, for example, a SiO film. The via wiring 150 includes, for example, a tungsten (W) plug 152 and a TiN film 151 that is a glue layer.

  Of the via wiring 150, the via wiring to the upper electrode 130 passes through the etching stopper film 141 and is in electrical contact with the upper electrode 130, and the via wiring to the lower layer wiring 103 includes the insulating film 105 and the diffusion prevention film 104. And is in electrical contact with the lower layer wiring 103. The via wiring 150 to the lower electrode 110 may extend partway through the TiN film 113, or may extend through the TiN film 113 and into the nitride layer 112 as illustrated. . However, the via wiring 150 to the lower electrode 110 is formed so as not to directly contact the Ti layer 111.

  The semiconductor device according to this embodiment includes a TiN / Ti laminated film 113/111 as the lower electrode 110 of the MIM capacitor element 100, and the TiN film 113 preferably has a thickness of less than 30 nm. Since the TiN film 113 has such a thickness, even when it is formed by sputtering, the surface unevenness is small, which is preferable in terms of electric characteristics of the capacitive element such as a withstand voltage.

  FIG. 2 shows cross-sectional photographs taken with a scanning transmission electron microscope (STEM) of two MIM capacitor elements having different lower electrodes. The lower electrode in FIG. 2A is a TiN film having a thickness of 150 nm, and the lower electrode in FIG. 2B is a laminated film having a TiN film 113 having a thickness of 20 nm / Ti film having a thickness of 80 nm. These photographs are observations of irregularities on the surface of the lower electrode in a cross section including the via wiring to the upper electrode. In (b), the unevenness on the surface of the TiN film 113 was suppressed as compared with the surface of the TiN film in (a).

  In addition, a dielectric dependent time breakdown (TDDB) test was performed for each of the MIM capacitor elements corresponding to (a) and (b). The lifetime until a 0.1% defect occurred at the operating temperature Tj = 125 ° C. and the voltage Vcc = 3.6 V of the MIM capacitor element was improved from (a) 4.1E + 4 hours to (b) 3.9E + 5 hours.

Furthermore, the semiconductor device according to the present embodiment has a nitride layer 112 formed by nitriding treatment such as NH ₃ plasma treatment or N ₂ O plasma treatment on the surface of the Ti film 111 of the lower electrode 110. Therefore, even if the via wiring 150 to the lower electrode 110 penetrates the TiN film 113 having a thickness of less than 30 nm, it can be prevented from reaching the Ti film 111 therebelow. If the via opening for the via wiring 150 reaches the Ti film 111, the film forming gas used in the subsequent plug forming process reacts with Ti, and the contact resistance between the plug and the lower electrode increases. Arise. For example, the Ti of the Ti film 111 exposed through the via opening reacts with the fluorine of tungsten hexafluoride (WF ₆ ) gas used when the W plug 152 is embedded in the via opening, whereby the bottom of the via wiring 150 is formed. In addition, cavities and foreign substances (reaction products) are generated on the side walls. This phenomenon increases the contact resistance between the W plug 152 and the lower electrode 110. However, according to the present embodiment, the occurrence of this phenomenon can be prevented by the nitride layer 112 by NH ₃ plasma treatment on the surface of the Ti film 111.

3 shows the contact resistance between the W plug 152 and the lower electrode 110 when (1) NH ₃ plasma treatment is not performed on the surface of the Ti film 111 and (2) NH ₃ plasma treatment is performed, that is, the nitride layer 112 is formed. The result compared with the case where it did is shown. For each of the conditions (1) and (2), the contact resistance for each via was measured at two wafers at 77 points / wafer measurement points. (1) Without NH ₃ plasma treatment, the contact resistance varies in the range of about 7Ω-15Ω, whereas (2) With NH ₃ plasma treatment, the contact resistance is suppressed from varying to the higher side, and about A contact resistance in the range of 7Ω-10Ω can be stably obtained.

FIG. 3 shows the contact resistance when RF etching of about 5 nm is performed from the surface of the Ti layer 111 (the nitrided surface in the condition (2)) prior to the formation of the via 150. . Regarding condition (2), when the same measurement was performed with the RF etching amount increased to 10 nm and 20 nm, the contact resistance remained stable in the range of about 6Ω-10Ω. From this, it is assumed that in this measurement sample, the NH ₃ plasma treatment on the surface of the Ti film 111 can form the nitride layer 112 having a thickness of 20 nm or more. In this case, the effect of this NH ₃ plasma treatment, that is, the effect of suppressing the increase in contact resistance is obtained by setting the amount of penetration of the contact opening to the lower electrode 110 from the surface of the nitride layer 112 to 20 nm or less. Can do.

  Next, a method for manufacturing a semiconductor device having the MIM capacitor element 100 of FIG. 1 will be described with reference to FIGS.

  First, as shown in FIG. 4A, a diffusion preventing film 104 and an insulating film 105 are formed on an interlayer insulating film 102 that is stacked on a semiconductor substrate 101 and encloses a lower wiring 103 having, for example, Cu or Al. Film. The diffusion prevention film 104 and the insulating film 105 can be, for example, a SiC film having a thickness of 70 nm and a SiO film having a thickness of 100 nm, respectively.

  Next, as shown in FIG. 4B, a first lower electrode conductive film 111 ″, which is a Ti film having a thickness of 50 nm to 100 nm, for example, 80 nm, is formed. Ar) In an atmosphere, sputtering can be performed using Ti as a target.

Next, as shown in FIG. 4C, the surface of the Ti film 111 ″ is nitrided by NH ₃ plasma treatment to form a Ti film 111 ′ and a nitride layer 112 ′. The nitride layer has a thickness of 10 nm to 30 nm. The plasma treatment conditions are not limited to the following, but may be, for example, NH ₃ flow rate 2000 sccm, N ₂ flow rate 7000 sccm, pressure 2.7 Torr, time 10 seconds.

Next, as shown in FIG. 4D, a second lower electrode conductive film 113 ′, which is a TiN film having a thickness of 20 nm, for example, is formed by sputtering. This sputtering can be performed using Ti as a target in an atmosphere containing Ar and N ₂ . At this time, by making the thickness of the TiN film 113 ′ less than 30 nm, it is possible to suppress the occurrence of irregularities such as needle-like protrusions on the surface of the TiN film 113. Through the above process group, a laminated lower electrode conductive film 110 ′ (TiN film 113 ′ / nitride layer 112 ′ / Ti film 111 ′) is obtained.

Next, as shown in FIG. 5A, a dielectric film 120, an upper electrode conductive film 130 ′, and an etching stopper film 141 are formed. Preferably, prior to the formation of the dielectric film 120, N ₂ O plasma treatment is performed in order to remove defects on the surface of the TiN film 113 ′ and make the film quality uniform. The dielectric film 120 is, for example, a 40 nm thick SiO film, and can be formed by a chemical vapor deposition (CVD) method. The upper electrode conductive film 130 ′ is a TiN film having a thickness of 100 nm, for example, and can be formed by sputtering. The etching stopper film 141 is a SiC film having a thickness of 70 nm, for example, and can be formed by a CVD method.

  Next, as shown in FIG. 5B, the etching stopper film 141 and the upper electrode conductive film 130 'are patterned by a lithography process and an etching process. Thereby, the upper electrode 130 is formed. At this time, the exposed dielectric film 120 may be partially etched.

  Next, as shown in FIG. 5C, the dielectric film 120 and the lower electrode conductive film 110 'are patterned by a lithography process and an etching process. Thereby, the lower electrode 110 is formed. In the illustrated example, since the insulating film 105 exists under the lower electrode conductive film 110 ′, the lower electrode conductive film 110 ′ is sufficiently over-etched until the exposed insulating film 105 is partially etched. Is possible.

  Next, as shown in FIG. 5D, an interlayer insulating film 142 is formed so as to cover the laminated structure of the upper electrode 130 / dielectric film 120 / lower electrode 110, and the interlayer insulating film is chemically and mechanically formed. Planarization is performed by polishing (CMP). The interlayer insulating film 142 may be a plasma SiO film having a thickness of 930 nm, for example.

  Next, as illustrated in FIG. 6A, via openings 150 ′ are formed in the interlayer insulating film 142 toward the upper electrode 130, the lower electrode 110, and the lower layer wiring 103 by a lithography process and an etching process.

At this time, it is preferable to form all of these via openings 150 ′ simultaneously from the viewpoint of process reduction. Since the via opening 150 ′ to the upper electrode 130 and the via opening 150 ′ to the lower electrode 110 are shallower than the via opening 150 ′ to the lower wiring 103, interlayer insulation of the etching stopper film 141 and the lower electrode 110 with respect to the TiN film 113 is performed. Etching conditions such as gas flow rate and pressure are determined so that the etching selectivity of the film 142 is increased. For example, when the etching stopper film 141 is a SiC film having a thickness of 70 nm and the diffusion prevention film 104 is a SiC film, an etching process using a mixed gas of C ₄ F ₆ , O ₂ and Ar can be used. In this etching step, via openings 150 ′ to the upper electrode 130, the lower electrode, and the lower layer wiring 103 can be stopped in the etching stopper film 141, on / in the TiN film 113, and on / in the diffusion prevention film 104, respectively. However, the present embodiment is not limited to forming all the via openings 150 ′ at the same time, and a plurality of lithography processes and etching processes for forming the respective via openings 150 ′ separately may be used. When each via opening 150 ′ is formed separately, the material of each film constituting the MIM capacitor element 100 and the degree of freedom of each etching condition can be increased.

Next, as shown in FIG. 6B, the etching stopper film 141 and the diffusion prevention film 104 existing at the bottoms of the via opening 150 ′ to the upper electrode 130 and the via opening 150 ′ to the lower layer wiring 103 are removed. To do. For example, an etching process using a mixed gas of CH ₂ F ₂ , O _2, and N ₂ can be used. By this etching process, the via opening 150 ′ to the lower electrode 110 is also deepened. However, by appropriately selecting the thickness of the TiN film 113 such as 10 nm or more, the via opening 150 ′ forms the nitride layer 112. It can be prevented that it extends beyond the Ti film 111.

  Next, as shown in FIG. 6C, a via wiring 150 having, for example, a TiN glue layer 151 and a W plug 152 is formed in the via opening 150 ′. For example, a TiN film to be the glue layer 151 is formed to a thickness of 50 nm by sputtering, a W film to be the W plug 152 is formed to a thickness of 300 nm by the CVD method, and is planarized by the CMP method. Prior to the formation of the glue layer 151, it is preferable to remove the oxide on the surface of the metal film existing at the bottom of each via opening 150 'by RF etching. Through the above process group, the MIM capacitor element 100 shown in FIG. 1 is formed. Thereafter, one or more required upper layer wirings (not shown) are formed.

  Next, a semiconductor device having the MIM capacitor element 200 according to the second embodiment will be described with reference to FIG. The MIM capacitor element 200 generally has the same configuration as that of the MIM capacitor element 100 according to the first embodiment described above, and corresponding components are denoted by the same reference numerals.

  The MIM capacitor element 200 is formed on an interlayer insulating film 202 stacked on the semiconductor substrate 201. Although it does not specifically limit in the semiconductor substrate 201, For example, semiconductor elements, such as a transistor, are formed. The interlayer insulating film 202 includes a lower layer wiring 203 made of, for example, Cu or Al.

  The MIM capacitor element 200 also includes a diffusion prevention film 204 formed on the interlayer insulation film 202 and an insulation film 205 as necessary formed on the diffusion prevention film 204. The diffusion prevention film 204 can be, for example, a SiC film having a thickness of about 70 nm. The insulating film 205 can be a SiO film having a thickness of about 100 nm, for example.

A lower electrode 210, a dielectric film 220, and an upper electrode 230 of the MIM capacitor element 200 are formed on the insulating film 205 as necessary. The lower electrode 210 includes a Ti film 211 and a TiN film 213 in order from the lower layer side. The Ti film 211 is typically formed by sputtering and has a thickness of, for example, 80 nm. The TiN film 213 is typically formed by sputtering to a thickness of 10-30 nm so as not to have columnar crystals. The lower electrode 210 further includes a nitride layer 212 formed by locally treating the Ti film 211 with NH ₃ plasma. The dielectric film 220 typically includes SiO or SiN, and the thickness is determined so as to satisfy a desired capacitance value and reliability of the MIM capacitor element. For example, the dielectric film 120 may be a 40 nm thick SiO film. However, the dielectric film 120 may have other materials such as a high dielectric constant dielectric, or a combination thereof with SiO and / or SiN. The upper electrode 230 is not particularly limited, but may be a TiN film having a thickness of 100 nm, for example.

  The MIM capacitor element 200 further includes an etching stopper film 241 formed on the upper electrode 230, an interlayer insulating film 242 that covers the laminated structure of the upper electrode 230 / dielectric film 220 / lower electrode 210, and an interlayer insulating film 242. A via wiring 250 is formed. In addition, the semiconductor device has one or more upper layer wirings (not shown) for connecting the MIM capacitor element 200 to various semiconductor elements and / or electric circuits on the interlayer insulating film 242 and the via wiring 250. .

  The etching stopper film 241 preferably has the same material as the diffusion prevention film 204, for example, SiC. The interlayer insulating film 242 can be, for example, a SiO film. The via wiring 250 includes, for example, a tungsten (W) plug 252 and a TiN film 251 that is a glue layer. Of the via wiring 250, the via wiring to the upper electrode 230 passes through the etching stopper film 241 and is in electrical contact with the upper electrode 230, and the via wiring to the lower layer wiring 203 includes the insulating film 205 and the diffusion prevention film 204. And is in electrical contact with the lower layer wiring 203. In addition, the via wiring 250 to the lower electrode 210 is formed so as to penetrate the TiN film 213 and reach the Ti film 211. However, due to the presence of the nitride layer 212, the via wiring 250 directly contacts the Ti film 211. Not.

  The semiconductor device according to the present embodiment includes a TiN / Ti stacked film 213/211 as the lower electrode 210 of the MIM capacitor element 200, and the TiN film 213 has a thickness of less than 30 nm. By having such a thickness, the TiN film 113 does not have columnar crystals even when formed by sputtering. Therefore, as described with reference to FIG. 2, the unevenness of the surface of the TiN film 213 is suppressed, and the life of the MIM capacitor element is improved.

Furthermore, the semiconductor device according to the present embodiment includes a nitride layer 212 formed by nitriding treatment such as NH ₃ plasma treatment between the via wiring 250 to the lower electrode 210 and the Ti film 211 of the lower electrode 210. Therefore, as described with reference to FIG. 3, the fluorination reaction of the Ti film 211 during the formation of the W plug 252, and hence the increase in contact resistance between the via wiring 250 and the lower electrode 210 is suppressed. In this embodiment, as will be described later with reference to FIG. 10, after forming the contact hole 250 ′ to the lower electrode, the lower electrode exposed at the bottom of the contact hole is subjected to nitriding, so that the contact hole 250 Even when 'is formed deep from the surface of the Ti film 211, for example, exceeding 20 nm, an increase in contact resistance can be reliably suppressed. Therefore, the semiconductor device according to the present embodiment can increase the margin of the etching process of the via opening for the via wiring 250.

  Next, a method for manufacturing a semiconductor device having the MIM capacitor element 200 of FIG. 7 will be described with reference to FIGS. Processes common to the method for manufacturing the MIM capacitor 100 shown in FIGS. 4-6 will not be described in detail.

  First, as shown in FIG. 8A, a diffusion prevention film 204 and an insulating film 205 are formed on an interlayer insulating film 202 that is stacked on the semiconductor substrate 201 and encloses the lower layer wiring 203.

  Next, as shown in FIG. 8B, a first lower electrode conductive film 211 ', which is a Ti film having a thickness of 80 nm, for example, is formed. This film formation can be performed, for example, by sputtering using Ti as a target in an argon (Ar) atmosphere.

Next, as shown in FIG. 8C, a second lower electrode conductive film 213 ′, which is a TiN film having a thickness of, for example, 20 nm, is formed by sputtering. This sputtering can be performed using Ti as a target in an atmosphere containing Ar and N ₂ . At this time, by making the thickness of the TiN film 113 ′ less than 30 nm, it is possible to suppress the occurrence of irregularities such as needle-like protrusions on the surface of the TiN film 113. Through the above process group, a laminated lower electrode conductive film 210 ′ (TiN film 213 ′ / Ti film 211 ′) is obtained.

  Next, as shown in FIG. 8D, a dielectric film 220, an upper electrode conductive film 230 ', and an etching stopper film 241 are formed.

  Next, as shown in FIG. 9A, the etching stopper film 241 and the upper electrode conductive film 230 ′ are patterned by a lithography process and an etching process to form the upper electrode 230.

  Next, as shown in FIG. 9B, the dielectric film 220 and the lower electrode conductive film 210 'are patterned by a lithography process and an etching process. Thereby, a laminated structure of the TiN film 213 / Ti film 211 is obtained.

  Next, as shown in FIG. 9C, an interlayer insulating film 242 is formed, and the interlayer insulating film is planarized by a CMP method.

  Next, as shown in FIG. 9D, via openings are formed in the interlayer insulating film 242 toward the upper electrode 230, the laminated structure of the TiN film 213 / Ti film 211, and the lower layer wiring 203 by a lithography process and an etching process. 250 'is formed. As described with reference to FIG. 6A, it is preferable to form all of these via openings 250 'simultaneously, but at least a part of the via openings 250' may be formed separately.

  Next, as shown in FIG. 10A, the etching stopper film 241 and the diffusion prevention film 204 existing at the bottoms of the via opening 250 ′ to the upper electrode 230 and the via opening 250 ′ to the lower layer wiring 203 are removed. . Since the TiN film 213 is typically 10-30 nm thick, the etching process at this time causes the via opening 250 ′ to the laminated structure of the TiN film 213 / Ti film 211 to penetrate the TiN film 213. Extending into the Ti film 211, a part of the Ti film 211 is exposed.

Next, as shown in FIG. 10B, the exposed surface of the Ti film 211 is nitrided by NH ₃ plasma treatment to form a nitride layer 212. The plasma treatment conditions are not limited to the following, but may be, for example, NH ₃ flow rate 2000 sccm, N ₂ flow rate 7000 sccm, pressure 2.7 Torr, time 10 seconds.

  Next, as shown in FIG. 10C, a via wiring 250 having, for example, a TiN glue layer 251 and a W plug 252 is formed in the via opening 250 ′. Through the above process group, the MIM capacitor element 200 shown in FIG. 7 is formed. Thereafter, one or more required upper layer wirings (not shown) are formed.

Although the embodiment has been described in detail above, the present invention is not limited to the specific embodiment, and various modifications and changes can be made within the scope of the gist described in the claims. For example, the NH ₃ plasma treatment on the entire surface of the Ti film in the first embodiment and the local NH ₃ plasma treatment on the surface of the Ti film in the second embodiment may be combined as necessary. Although the lower electrode has been described as having a laminated structure including a Ti film, a nitride layer is formed by NH ₃ plasma treatment instead of the Ti film, and the nitride layer suppresses the fluorination reaction during plug formation. Other metal films may be used.

Regarding the above description, the following additional notes are disclosed.
(Appendix 1)
A metal film formed on a semiconductor substrate and having a nitride layer on the upper surface, a TiN film formed on the metal film, a dielectric film formed on the TiN film, and formed on the dielectric film A capacitive element having an upper electrode;
An insulating film covering the capacitive element;
A via wiring penetrating the insulating film and contacting the TiN film;
A semiconductor device.
(Appendix 2)
The semiconductor device according to appendix 1, wherein the thickness of the TiN film is 10 nm or more and less than 30 nm.
(Appendix 3)
The semiconductor device according to appendix 1 or 2, wherein the nitride layer has a thickness of 10 nm or more and less than 30 nm.
(Appendix 4)
The semiconductor device according to any one of appendices 1 to 3, wherein the nitride layer is formed over the entire surface of the Ti film.
(Appendix 5)
4. The semiconductor device according to claim 1, wherein the nitride layer is formed along a portion of the via wiring penetrating the TiN film.
(Appendix 6)
Forming a metal film on a semiconductor substrate;
Nitriding the metal film and forming a nitride layer on the surface of the metal film;
Forming a TiN film on the nitride layer;
Forming a dielectric film and a conductive film on the TiN film;
A method for manufacturing a semiconductor device comprising:
(Appendix 7)
Forming an insulating film on the conductive film;
Forming a via opening reaching the TiN film in the insulating film;
Forming via wiring in the via opening;
The method for manufacturing a semiconductor device according to appendix 6, further comprising:
(Appendix 8)
Forming a metal film on a semiconductor substrate;
Forming a TiN film on the metal film;
Forming a dielectric film and a conductive film on the TiN film;
Forming an insulating film on the conductive film;
Forming a via opening reaching the metal film in the insulating film;
Nitriding the exposed surface of the metal film through the via opening, and forming a nitride layer on the exposed surface of the metal film;
Forming via wiring in the via opening;
A method for manufacturing a semiconductor device comprising:
(Appendix 9)
The method for manufacturing a semiconductor device according to any one of appendices 6 to 8, wherein the thickness of the TiN film is 10 nm or more and less than 30 nm.
(Appendix 10)
The method for manufacturing a semiconductor device according to any one of appendices 6 to 9, wherein the nitride layer has a thickness of 10 nm or more and less than 30 nm.
(Appendix 11)
The method for manufacturing a semiconductor device according to any one of appendices 6 to 10, wherein the nitriding treatment is NH ₃ plasma treatment.

100, 200 MIM capacitive element 101, 201 Semiconductor substrate 102, 142, 202, 242 Interlayer insulating film 103, 203 Lower layer wiring 104, 204 Diffusion prevention film 105, 205 Insulating film 110, 210 Lower electrode 111, 211 First lower electrode Films 112 and 212 First lower electrode film nitride layer 113 and 213 Second lower electrode film 120 and 220 Dielectric film 130 and 230 Upper electrode 141 and 241 Etching stopper film 150 and 250 Via wiring 150 'and 250' Via Opening 151,251 Glue layer 152,252 Plug

Claims (8)

A metal film formed on a semiconductor substrate and having a nitride layer on the upper surface, a TiN film formed on the metal film, a dielectric film formed on the TiN film, and formed on the dielectric film A capacitive element having an upper electrode;
An insulating film covering the capacitive element;
A via wiring penetrating the insulating film and contacting the TiN film;
A semiconductor device.   The semiconductor device according to claim 1, wherein the thickness of the TiN film is 10 nm or more and less than 30 nm.   The semiconductor device according to claim 1, wherein the nitride layer has a thickness of 10 nm or more and less than 30 nm. Forming a metal film on a semiconductor substrate;
Nitriding the metal film and forming a nitride layer on the surface of the metal film;
Forming a TiN film on the nitride layer;
Forming a dielectric film and a conductive film on the TiN film;
A method for manufacturing a semiconductor device comprising: Forming an insulating film on the conductive film;
Forming a via opening reaching the TiN film in the insulating film;
Forming via wiring in the via opening;
The method for manufacturing a semiconductor device according to claim 4, further comprising: Forming a metal film on a semiconductor substrate;
Forming a TiN film on the metal film;
Forming a dielectric film and a conductive film on the TiN film;
Forming an insulating film on the conductive film;
Forming a via opening reaching the metal film in the insulating film;
Nitriding the exposed surface of the metal film through the via opening, and forming a nitride layer on the exposed surface of the metal film;
Forming via wiring in the via opening;
A method for manufacturing a semiconductor device comprising:   The method of manufacturing a semiconductor device according to claim 4, wherein the thickness of the TiN film is 10 nm or more and less than 30 nm.   The method of manufacturing a semiconductor device according to claim 4, wherein the nitride layer has a thickness of 10 nm or more and less than 30 nm.