KR980011885A - Metal wiring contact formation method of semiconductor device - Google Patents

Abstract

Etching occurs when etching the layers of material between the substrate and the metal wiring layer to form metal wiring contact pads in the peripheral circuit area when forming the storage node contacts in the cell array area to form the metal wiring contact in the peripheral circuit area. Reduce the burden

Description

Metal wiring contact formation method of semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a metal wiring contact in a semiconductor device, and more particularly, to a method for forming a contact for a metal wiring to form a pad for a metal wiring contact when forming a storage node.

As semiconductor devices become more integrated, not only the width of the wiring but also the space between the wiring and the wiring are significantly reduced. Furthermore, in a memory device using multiple conductive layers, the height between the conductive layer and the conductive layer is further increased by the interlayer insulating film, making the process of forming contact holes between the conductive layers very difficult. In addition, in the highly integrated memory device of 1 Gigabyte or more DRAM, the margin of the photolithography process due to the step is insufficient due to the reduction of the dimension. Flattening processes using chemical-mechanical-polishing (CMP) are currently under development / applications to improve these poor photo etch margins and are essential for fine patterning in devices with more than 4 gigabytes of DRAM.

However, current chemical-physical polishing techniques have not been applied in trailing processes such as Dilan's metallization. The reason for this is that after forming the cell capacitor, the contact is formed in the material layers formed on the substrate for the contact of the metal wiring layer. Therefore, the metal contact is too deep due to the step difference between the cell array portion and the remaining peripheral circuit portion. . Therefore, the contact for forming the metal wiring is not easy.

Referring to Fig. 1, a conventional metal wiring forming method will be described.

The trench isolation region 2 is formed on the substrate 1, the gate electrode 4 is patterned on the upper surface of the substrate, a capping layer is formed on the gate electrode, and a spacer ( 6) is formed. The pad poly layer 8 is formed by depositing a polysilicon layer on a predetermined portion of the substrate and planarizing it using a chemical-physical polishing technique. A contact hole for depositing a first interlayer insulating film 10 on the entire surface of the resultant, flattening by chemical-physical polishing, and etching a part of the interlayer first insulating film to expose a part of the pad poly layer, an upper part of a gate electrode, and a part of a substrate. To form. The contact hole is filled and a conductive material layer is formed on the first interlayer insulating film, and the conductive material layer is patterned to form a bit line 12 pattern. A second interlayer insulating layer 14 is coated on the resultant bit line pattern, and the nitride interlayer 14 is formed on the planarized second interlayer insulating layer 14 to planarize the second interlayer insulating layer 14. Next, a portion of the nitride layer 16 and the second interlayer insulating layer 14 are etched to expose the upper portion of the poly pad layer 8, and a conductive material is filled in the contact hole formed in the second interlayer insulating layer. On the resultant, the storage node contact 20 is depoted and patterned with a metal such as, for example, platinum and then plate metal 24 acting on top of the high dielectric oxide layer 22 and the upper electrode of the storage node sequentially. Deposit. Thereafter, the plate metal 24, the high dielectric oxide layer 22, and the silicon nitride layer 16 are patterned. Next, a third interlayer insulating layer 26 is formed and planarized, and a contact hole for metal wiring is formed in the third interlayer insulating layer to expose a portion of the substrate. This contact hole is filled with tungsten and serves as a tungsten plug 28. Next, the lower interconnection layer 30 and the fourth interlayer insulation layer 32 are sequentially formed on the upper surface of the third interlayer insulation layer 26, and contact holes are formed on the fourth interlayer insulation layer 32 to electrically connect with the upper interconnection layer 34. Connect with

However, in order to form the tungsten plug 28, since the first to third interlayer insulating films must be etched, there is an etching burden, and the aspect ratio is large, so that cleaning and filling of tungsten after etching are not easy. Specifically, when the current one gigabyte is based on the scale of the DRAM, the aspect ratio is about 5, and it is difficult to form a good contact hole using the etching equipment currently used.

In order to solve this problem, a method of forming an attitude of contacting a tungsten plug in forming a bit line pattern has been disclosed, which will be described with reference to FIG. 2.

In FIG. 2, when forming the first interlayer insulating film 50, performing chemical-physical polishing, and forming a contact hole in the first interlayer insulating film, a contact hole for contact between the wiring layer and the substrate, in addition to the bit line contact, is used. Form 51. Next, a conductive material is filled in the contact hole formed in the first interlayer insulating layer to form a bit line pattern 52 and a wiring layer connection pad pattern 53 formed on an upper surface of the first interlayer insulating layer. The subsequent process is the same as the process for manufacturing the semiconductor device shown in FIG. 1 except that the contact hole for forming the tungsten plug 68 is etched from the second and third interlayer insulating films 54 and 66 to form the wiring layer. It is formed by exposing the connection pad pattern 53. Here, the contact hole for connecting the lower metal wiring layer and the upper metal wiring layer is formed by etching the first interlayer insulating film to form a contact hole, forming a pad pattern 53, and etching only the upper surface of the pattern 53. By forming the contact holes to make the tungsten plug 68, the etching burden for one-time etching is considerably reduced. However, in the technique of FIG. 2, since the wiring layer connection pattern must be formed at the peripheral circuit part at the time of bit line patterning, the photolithography process is difficult, and in particular, the patterning is not easy in a high-density device of more than 1G DRAM.

The technical problem to be achieved by the present invention is to provide a method for forming a contact of the metal wiring of the semiconductor device, the etching process is easy to solve the above problems.

1 is a cross-sectional view of a semiconductor device showing a conventional metal wiring contact forming method.

2 is a cross-sectional view of a semiconductor device showing another conventional method for forming metal wiring contacts.

3 is a cross-sectional view of a semiconductor device showing a metallization contact forming method according to the present invention.

4A to 4C are cross-sectional views of a semiconductor device showing a metal wiring contact forming method according to the present invention.

In order to achieve the above object, the method for forming a metal wiring contact according to the present invention includes forming a bit line pattern on a semiconductor substrate having a bit line pad poly layer formed between a gate electrode and the gate electrode, and forming the bit line pattern. Sequentially forming a planarized first interlayer insulating film and an etch stop layer on an upper surface of the resultant, and etching the first interlayer insulating film and an etch stop layer to form a storage node contact hole in a cell region and a metal wiring contact hole in a peripheral circuit region. Forming a conductive plug by filling the storage node contact hole and the metal wiring contact hole with a conductive material; forming a first conductive layer pattern on an upper surface of both conductive plugs; The high dielectric material layer and the second conductive layer pattern may be formed only on the storage node metal layer pattern. Forming a planarized second interlayer insulating film over the entire surface of the resultant; forming a second contact hole in the second interlayer insulating film to expose a first conductive layer pattern formed in the peripheral circuit region; and the second contact Forming a first wiring layer on an upper surface of the second interlayer insulating layer while filling a hole, forming a third interlayer insulating layer on an upper surface of the first wiring layer, and forming a third contact hole in the third interlayer insulating film to form the first wiring layer And forming a second wiring layer on an upper surface of the third interlayer insulating layer to fill a portion of the third contact hole.

Here, the conductive plug is made of tungsten, and the first conductive layer pattern is made of platinum.

Hereinafter, the present invention will be described with reference to FIGS. 3 and 4A to 4C.

3 shows a semiconductor device formed by a metal wiring contact forming method according to the present invention. The difference from the invention of FIG. 1 is that after forming the interlayer insulating film 94, when the tungsten plug is formed in the storage node contact hole, the tungsten plug for the metal wiring contact is also formed. In other words, the etching burden is considerably reduced and the damage of the substrate due to etching can be reduced compared to forming a contact hole for etching the resultant of the capacitor to expose the substrate. On the other hand, Figure 2 is to form a tungsten plug pad layer 53 for the metal wiring contact when forming the bit line pattern in the present invention, since the pattern for the tungsten plug pad layer is not formed in the peripheral circuit area, the conventional photolithography Do not face the limitations of the process.

4A to 4C illustrate a metal wiring forming method according to the present invention.

In FIG. 4A, a gate electrode 84 is formed on an upper surface of the substrate 81 on which the trench isolation region 82 is formed, and a spacer 86 is formed on sidewalls of the gate electrode 84. A pat poly layer 88 is formed between the gate electrodes of the cell region and the layer is planarized by a chemical-physical polishing technique. Next, after forming and planarizing the first interlayer insulating film 90 on the entire surface of the resultant, a first contact hole for bit line contact of the cell region is formed in the first interlayer insulating film 90. A conductive material forming a bit line is deposited on an upper surface of the first interlayer insulating layer, and fills the first contact hole. Next, the conductive material for the bit line is patterned to form a bit line pattern 92. Thereafter, a second interlayer insulating film 94 is formed on the entire surface of the resultant, and the resultant surface is planarized using a chemical-physical polishing technique.

In FIG. 4B, the nitride film 96 is formed as an etch stop layer on the upper surface of the second interlayer insulating film 94. Next, the first conductive pattern 100 is formed of a metal such as platinum in the cell region and the peripheral circuit region, and the surface thereof is planarized. Next, a high dielectric material layer 102 such as BST and a second conductive pattern 104 are sequentially formed on the first conductive pattern 100 in the cell region, and the etch stop layer 96 is etched. As the end point, the first and second conductive patterns 104, the high dielectric film 102, and the nitride film 96 are patterned. Thereafter, a third interlayer insulating film 106 is formed on the entire surface of the resultant and the surface is planarized by using a physical-physical polishing technique.

In FIG. 4C, a third contact hole is formed in the third interlayer insulating film 106, and as a result, the first wiring layer 108 is formed by applying a metal material such as aluminum or an alloy thereof to the surface. In this case, the material constituting the first wiring layer 108 fills the third contact hole. Next, a fourth interlayer insulating film is formed on the upper surface of the first wiring layer 108, and the surface thereof is planarized by a chemical-physical polishing technique, and the connection between the first wiring layer 108 and the second wiring layer 112 to be formed later is formed. A fourth contact hole for forming is formed. Thereafter, the second wiring layer 112 is formed on the upper surface of the fourth interlayer insulating film.

The present invention has been described above with reference to specific embodiments, but the present invention is not limited thereto, and various modifications of the present invention are possible to those skilled in the art.

As described above, for the connection between the metal wiring layer and the substrate, the first and second interlayer insulating films 90 and 94 are etched, the tungsten plug 97 is formed, and the metal wiring contact pad 100 is formed when the storage node pattern is formed. ) Is also formed at the same time, through which the metal wiring layer and the substrate are connected. This reduces the burden of etching for metallization contacts as compared to the prior art and is suitable for more than one gigabyte high integration devices.

Claims (2)

Forming a bit line pattern on the semiconductor substrate on which the bit line pad poly layer formed between the gate electrode and the gate electrode is formed, and sequentially forming a planarized first interlayer insulating layer and an etch stop layer on an upper surface of the resultant product on which the bit line pattern is formed Forming a metal interconnection contact hole in a storage node contact hole and a peripheral circuit region of a cell region by etching the first interlayer insulating layer and the etch stop layer; conductively conducting the storage node contact hole and the metal wiring contact hole Forming a conductive plug filled with a material, forming a first conductive layer pattern on the upper surface of both conductive plugs, the high dielectric material layer and the second conductive layer pattern only on the storage node metal layer pattern formed on the storage node contact hole Forming a planarized second interlayer insulating film on the entire surface of the resultant; Forming a second contact hole in a second interlayer insulating film to expose a first conductive layer pattern formed in the peripheral circuit region, forming a first wiring layer on an upper surface of the second interlayer insulating film while filling the second contact hole; Forming a third interlayer insulating film on an upper surface of the first wiring layer, forming a third contact hole in the third interlayer insulating film to expose a portion of the first wiring layer, and filling the third contact hole and filling the third contact hole And forming a second wiring layer on the upper surface of the interlayer insulating film. The method of claim 1, wherein the conductive plug is made of tungsten, and the first conductive layer pattern is made of platinum. ※ Note: The disclosure is based on the initial application.