KR100589497B1 - Method for fabricating capacitor - Google Patents

Abstract

The present invention relates to a method for manufacturing a capacitor, and more particularly, to form a capacitor so that the upper electrode surrounds both sides of the lower electrode, thereby increasing the capacity corresponding to the thickness of the lower electrode, and highly integrated MIM (Metal-Insulator-). Metal) It relates to a method of manufacturing a capacitor.

The object of the present invention is to form a lower electrode by depositing a lower electrode material on top of the substrate and depositing a first photoresist and patterning, forming an insulating film on the entire surface of the substrate including the lower electrode and the second photoresist Patterning the insulating layer to expose the side surface of the patterned lower electrode after depositing the same, forming a dielectric layer and an upper electrode material on the substrate including the insulating layer, and planarizing the upper electrode material and the dielectric layer It is achieved by a capacitor manufacturing method comprising the step of forming an electrode.

Therefore, the method of manufacturing the capacitor of the present invention has the effect of increasing the capacitance corresponding to the thickness of the lower electrode by forming the capacitor so that the upper electrode surrounds both sides of the lower electrode, the sidewall of the dielectric film when forming the upper electrode There is an effect of suppressing the phenomenon of re-deposition to cause a short, thereby improving the process margin, and preventing the deterioration of the characteristics of the capacitor due to the fringe capacity.

MIM, capacitor

Description

Method for fabricating capacitor             

1A to 1D are cross-sectional views of a capacitor manufacturing process according to the prior art.

Figure 2a to 2e is a cross-sectional view of the capacitor manufacturing process according to the present invention.

The present invention relates to a method for manufacturing a capacitor, and more particularly, to form a capacitor so that the upper electrode surrounds both sides of the lower electrode, thereby increasing the capacity corresponding to the thickness of the lower electrode, and highly integrated MIM (Metal-Insulator-). Metal) It relates to a method of manufacturing a capacitor.

Usually, SiO ₂ / Si ₃ N ₄ -based dielectric material is used as the dielectric film of the capacitor. Depending on the electrode material of the capacitor, a PIP (Poly-Insulator-Poly) capacitor or a MIM capacitor is used. Thin-film capacitors such as PIP capacitors or MIM capacitors are used in analog products that require the precision of capacitors, unlike MOS capacitors and junction capacitors, because they are bias-independent.

In addition, in the case of MIM capacitors, the capacitance per unit area is harder to manufacture than PIP capacitors, whereas the VCC (Voltage Coefficient for Capacitor) and TCC (Temperature Coefficient for Capacitor) of the capacitance according to voltage or temperature are applied to the PIP capacitor. It is very advantageous for producing precise analog products because it shows very good characteristics.

As the degree of integration of semiconductor devices increases, a conventional dielectric-insulator-semiconductor (MIS) capacitor has a low dielectric film formed between the dielectric film and the polysilicon film, thereby failing to obtain a desired capacitance. Accordingly, the need for a MIM capacitor that can replace the MIS capacitor is increasing.

Hereinafter, a method of manufacturing the MIM capacitor will be described with reference to FIGS. 1A to 1D.

First, as shown in FIG. 1A, in a state in which a predetermined base layer 10 is formed on the semiconductor substrate 1, the first metal film 11 and the dielectric film 12 on the base layer 10. ) And the second metal film 13 are sequentially formed. Here, the base layer 10 may be understood to include an interlayer insulating film having a transistor and surface planarization.

Next, as shown in FIG. 1B, the first photoresist layer pattern 14 is formed on the second metal layer 13 by a known photolithography process, and then the first photoresist layer pattern 14 is etched. The capacitor upper electrode 13a is obtained by etching the second metal film 13 and the dielectric film 12 using a mask.

Next, in a state in which the first photoresist pattern is removed, as shown in FIG. 1C, a second photoresist pattern 15 for forming a capacitor lower electrode is formed on the resultant again through a photolithography process. Next, the exposed first metal film part is etched to obtain the capacitor lower electrode 11a, thereby completing the MIM capacitor. Unexplained reference numeral 11b denotes a circuit wiring in the logic region.

Thereafter, as shown in FIG. 1D, in a state where the interlayer insulating film 16 is formed on the resultant, predetermined portions of the interlayer insulating film 16 are selectively etched to form the lower and upper electrodes 11a and 13a of the capacitor. Contact holes exposing the circuit wiring 11b, respectively, are formed, and then a conductive film is embedded in each of the contact holes, so that the plug 17 contacts with the circuit wiring 11b and the capacitor lower and upper electrodes 11a and 13a, respectively. ). Subsequently, a metal film is deposited on the interlayer insulating film 16, and then patterned to form a metal film which is electrically contacted with the circuit wiring 11b and the capacitor lower and upper electrodes 11a and 13a by the plug 17, respectively. Electrodes 18 are formed.

However, in the conventional MIM capacitor manufacturing method as described above, due to the formation of the lower electrode after the formation of the upper electrode, the formation of the capacitance (capacitance) is only made in the area covered with the upper electrode, not in the side of the lower electrode Thus, in connection with having to have a high capacity per unit area in order to obtain a high Q value and a low voltage coefficient, it is necessary to enlarge the capacitor electrode area in order to secure a desired capacity, thus wasting chip area. And, consequently, undesirable in terms of high integration.

In addition, in the conventional MIM capacitor structure, since a fringe capacity exists on the side of the electrode, there is also a problem in that the capacitor characteristics are degraded due to the fringe capacity.

Korean Patent Laid-Open Publication No. 2002-82549 describes a method of forming an upper electrode so that one side of the lower electrode is wrapped, but the above technique has increased storage capacity on only one side and there is a problem in miniaturization of the device. In addition, US Pat. No. 6,271,084 describes a technique for forming a capacitor using a large machine method to increase the degree of integration. However, the technique causes the electrode material to be redeposited on the sidewall of the dielectric film to cause a short when the upper electrode is formed. There is a problem that occurs.

Accordingly, the present invention is to solve the problems of the prior art as described above, by forming a capacitor so that the upper electrode surrounds both sides of the lower electrode to increase the capacity corresponding to the thickness of the lower electrode, forming the upper electrode An object of the present invention is to provide a method of manufacturing a capacitor capable of suppressing a phenomenon of causing red short due to redeposition on the sidewall of a dielectric film and preventing a decrease in capacitor characteristics due to fringe capacitance.

The object of the present invention is to form a lower electrode by depositing a lower electrode material on top of the substrate and depositing a first photoresist and then patterning, forming an insulating film on the entire surface of the substrate including the lower electrode and the second photoresist Patterning the insulating layer to expose the side surface of the patterned lower electrode after depositing the same, forming a dielectric layer and an upper electrode material on the substrate including the insulating layer, and planarizing the upper electrode material and the dielectric layer It is achieved by a capacitor manufacturing method comprising the step of forming an electrode.

Details of the above object and technical configuration of the present invention and the effects thereof according to the present invention will be more clearly understood by the following detailed description with reference to the drawings showing preferred embodiments of the present invention.

First, FIG. 2A is a view of forming a lower electrode. A lower electrode material 21 is formed on the substrate 20 on which a predetermined structure is formed, an anti-reflective coating (ARC) 22 is formed on the lower electrode material, and the first photoresist is formed. After deposition, the first photoresist is patterned using an exposure and development process. Subsequently, the lower electrode material and the anti-reflection film are etched using the first photoresist as an etch mask to form a lower electrode, and the first photoresist is removed. The lower electrode material is preferably Ti, W, TiN or the like. The anti-reflection film may improve the interface property with the dielectric film to be formed in a later step.

Next, as shown in FIG. 2B, an insulating film 23 is formed, and a second photoresist 24 is patterned on the insulating film. An interlayer insulating film is formed on the entire upper surface of the substrate on which the lower electrode is formed, and after the second photoresist is deposited on the interlayer insulating film, the second photoresist is patterned by using an exposure and development process. The second photoresist is patterned to be wider than the width of the lower electrode such that the upper electrode may be filled on both sides of the lower electrode when patterning the second photoresist. The insulating layer is preferably USG (Undoped Silicate Glass), PSG (Phospho Silicate Glass), BPSG (Boro Phospho Silicate Glass) or TEOS (Tetra Ethyl Ortho Silicate).

Next, as shown in FIG. 2C, the insulating film is etched and the second photoresist is removed. The interlayer insulating layer is etched using the second photoresist as an etching mask. When the interlayer insulating layer is etched, the anti-reflection film and the lower electrode existing under the interlayer insulating film are not etched. Next, the second photoresist is removed.

Next, as shown in FIG. 2D, the dielectric film 25 and the upper electrode material 26 are formed. A dielectric film is formed on the entire upper surface of the substrate on which the structure is formed, and an upper electrode material is deposited on the entire upper surface of the dielectric film. The dielectric film is preferably TaO ₂ , Al ₂ O ₃ , SiN, and the upper electrode material is preferably Ru, Pt, TiN, or the like.

Next, as shown in FIG. 2E, the upper electrode material and the dielectric film are planarized to form the upper electrode. The upper electrode material and the dielectric film are planarized by chemical mechanical polishing (CMP) until the insulating layer is exposed to form the upper electrode.

It will be apparent that changes and modifications incorporating features of the invention will be readily apparent to those skilled in the art by the invention described in detail. It is intended that the scope of such modifications of the invention be within the scope of those of ordinary skill in the art including the features of the invention, and such modifications are considered to be within the scope of the claims of the invention.

Therefore, the method of manufacturing the capacitor of the present invention has the effect of increasing the capacity corresponding to the thickness of the lower electrode by forming the capacitor so that the upper electrode surrounds both sides of the lower electrode, the sidewall of the dielectric film when forming the upper electrode There is an effect of suppressing the phenomenon of re-deposition to cause a short, thereby improving the process margin, and preventing the deterioration of the characteristics of the capacitor due to the fringe capacity.

Claims (6)

In the method of manufacturing a capacitor of a semiconductor device, Depositing a lower electrode material on the substrate, depositing a first photoresist, and patterning the lower electrode material to form a lower electrode; Forming an insulating film on an entire surface of the substrate including the lower electrode, depositing a second photoresist on the patterned lower electrode, and patterning the insulating layer to be wider than the width of the patterned lower electrode; Patterning the insulating layer using the patterned second photoresist pattern as a mask to expose side surfaces of the patterned lower electrode; Sequentially forming a dielectric film and an upper electrode material on the substrate including the patterned insulating film; And Forming the upper electrode by planarizing the upper electrode material and the dielectric layer until the insulating layer is exposed; Capacitor manufacturing method comprising a. The method of claim 1, Capacitor manufacturing method, characterized in that for forming the lower electrode after the deposition of the anti-reflection film further patterned. The method of claim 1, The lower electrode material is a capacitor manufacturing method, characterized in that any one of Ti, W and TiN. The method of claim 1, The insulating film is a capacitor manufacturing method, characterized in that any one of USG, PSG, BPSG and TEOS. The method of claim 1, The dielectric film is a capacitor manufacturing method, characterized in that any one of TaO ₂ , Al ₂ O ₃ and SiN. The method of claim 1, The upper electrode material is a capacitor manufacturing method, characterized in that any one of Ru, Pt and TiN.

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