CN112490246A - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

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Publication number
CN112490246A
CN112490246A CN202011230844.7A CN202011230844A CN112490246A CN 112490246 A CN112490246 A CN 112490246A CN 202011230844 A CN202011230844 A CN 202011230844A CN 112490246 A CN112490246 A CN 112490246A
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contact element
trench isolation
shallow trench
isolation structure
semiconductor device
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CN112490246B (en
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薛磊
刘威
陈亮
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Yangtze Memory Technologies Co Ltd
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Yangtze Memory Technologies Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/41—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The invention provides a semiconductor device and a preparation method thereof, wherein the semiconductor device comprises a semiconductor substrate, a dielectric layer, a contact element and a metal interconnection layer; the semiconductor substrate comprises a transistor and a shallow trench isolation structure; the contact element penetrates through the dielectric layer and comprises a first contact element and a second contact element which are contacted with the same shallow trench isolation structure, so that a capacitor is formed by the first contact element and the second contact element; the metal interconnection layer is located on the dielectric layer and electrically connected with the contact element. The invention can increase the capacitance of the capacitor and enlarge the application range of the semiconductor device on the premise of not changing the size of the semiconductor device.

Description

Semiconductor device and method for manufacturing the same
Technical Field
The invention belongs to the technical field of semiconductors, and relates to a semiconductor device and a preparation method thereof.
Background
A conventional Charge pump (Charge pump), also called a switched capacitor voltage converter, is a converter that stores energy by using a so-called "fast" or "pumping" capacitor, and the main applications include MOS (metal-oxide-silicon) capacitors and MOM (metal-oxide-metal) capacitors, however, these two capacitors usually occupy a large wafer area.
Taking 3D NAND as an example, 3D NAND is a technology for increasing capacity by vertically stacking memory cells to obtain higher storage density. In 3D NAND technology, the memory cell operates at a high voltage, and thus a capacitor is required to implement the voltage boosting. In the conventional 3D NAND architecture, peripheral circuits (peripheral) and stacked memory arrays (Array) are usually fabricated on the same wafer, so that in the 3D NAND architecture, the peripheral circuits can have enough space to form capacitors with larger plate area, thereby providing enough capacitance to meet the application requirements, and thus the technical problem of fabricating high-density and high-capacitance capacitors in the conventional 3D NAND architecture is not considered excessively. However, with the development of semiconductor technology, the fabrication of integrated circuits with lower cost, faster speed and higher integration has become the target of the current semiconductor technology, so that the conventional large-sized 3D NAND architecture is no longer suitable for the development requirement, and similarly, the structure of the current capacitor fabricated by occupying a larger wafer area is no longer in line with the development requirement, and how to fabricate a high-density and high-capacitance capacitor in a limited space to meet the development trend of semiconductor devices has become an urgent problem to be solved.
Therefore, it is necessary to provide a novel semiconductor device and a method for manufacturing the same.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a semiconductor device and a method for manufacturing the same, which solve the problem of the prior art that it is difficult to form a capacitor with high capacitance on a limited wafer area.
To achieve the above and other related objects, the present invention provides a semiconductor device including:
the semiconductor substrate comprises a transistor and a shallow trench isolation structure;
the dielectric layer is positioned on the semiconductor substrate and covers the transistor and the shallow trench isolation structure;
the contact element penetrates through the dielectric layer and comprises at least one first contact element and at least one second contact element which are in contact with the same shallow trench isolation structure, so that a capacitor is formed by the first contact element and the second contact element;
a metal interconnect layer on the dielectric layer and electrically connected with the contact element.
Optionally, the aspect ratio of the contact element ranges from 200:1 to 2500: 1.
Optionally, the same shallow trench isolation structure comprises N capacitors, wherein N is a positive integer and N is greater than or equal to 2.
Optionally, the capacitors on the same shallow trench isolation structure are arranged in parallel along the X direction of the shallow trench isolation structure.
Optionally, the aspect ratio of the contact element ranges from 1:1 to 20: 1. Optionally, on the same shallow trench isolation structure, X capacitors are included along an X direction of the shallow trench isolation structure, Y capacitors are included along a Y direction of the shallow trench isolation structure, X and Y are perpendicular to each other, where X and Y are both positive integers, and at least one of X and Y is greater than 1.
Optionally, the capacitors on the same shallow trench isolation structure are arranged in a staggered manner.
Optionally, the capacitor comprises one or a combination of a parallel connection or a series connection.
The present invention also provides a semiconductor device including:
a first wafer, the first wafer comprising:
the semiconductor substrate comprises a transistor and a shallow trench isolation structure;
the dielectric layer is positioned on the semiconductor substrate and covers the transistor and the shallow trench isolation structure;
the contact element penetrates through the dielectric layer and comprises at least one first contact element and at least one second contact element which are in contact with the same shallow trench isolation structure, so that a capacitor is formed by the first contact element and the second contact element;
a metal interconnect layer on the dielectric layer and electrically connected to the contact element;
a second wafer comprising a functional array layer and an array interconnect layer electrically connected to the functional array layer;
wherein the metal interconnect layer is electrically connected to the array interconnect layer.
Optionally, the aspect ratio of the contact element ranges from 200:1 to 2500:1 or from 1:1 to 20: 1.
The invention also provides a preparation method of the semiconductor device, which comprises the following steps:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a transistor and a shallow trench isolation structure;
forming a dielectric layer on the semiconductor substrate, and etching the dielectric layer to form a contact hole penetrating to the shallow trench isolation structure;
filling the contact hole to form a contact element, wherein the contact element comprises at least one first contact element and at least one second contact element which are in contact with the same shallow trench isolation structure, so that a capacitor is formed by the first contact element and the second contact element;
and forming a metal interconnection layer on the dielectric layer, wherein the metal interconnection layer is electrically connected with the contact element.
Optionally, the contact element is formed with an aspect ratio in a range including 200:1 to 2500:1 or 1:1 to 20: 1.
As described above, the semiconductor substrate of the present invention includes a transistor and a shallow trench isolation structure, a dielectric layer is formed on the semiconductor substrate, a contact element is formed in the dielectric layer, and the contact element includes a first contact element and a second contact element contacting with the same shallow trench isolation structure, so as to form a capacitor through the first contact element and the second contact element, and a metal interconnection layer is formed on the dielectric layer. On the premise of not changing the size of a semiconductor device, the first contact element and the second contact element with smaller distance are arranged on the shallow trench isolation structure, so that the distance between capacitors can be effectively reduced, and the capacitance can be increased; the area of the capacitor can be effectively increased by increasing the areas of the first contact element and the second contact element on the shallow trench isolation structure, so that the capacitance is increased; the distribution density of the capacitor can be increased by increasing the number of the contact elements on the shallow trench isolation structure so as to increase the capacitance; the connection of the capacitor can be flexibly controlled through the metal interconnection layer so as to expand the application range of the semiconductor device.
Drawings
Fig. 1 shows a schematic cross-sectional structure of a 3D NAND in a comparative example.
Fig. 2 is an enlarged schematic view of a region a in fig. 1.
FIG. 3 is a schematic cross-sectional view of a 3D NAND in the examples.
Fig. 4 is an enlarged schematic view of a' region in fig. 3.
Fig. 5a to 5c are schematic views showing three different enlarged structures of the region B in fig. 4.
Fig. 6 is a schematic view of a process flow for manufacturing a semiconductor device according to the present invention.
Description of the element reference numerals
10. 10' first wafer
11. 11' metal interconnection layer
20. 20' second wafer
21. 21' array interconnect layer
22. 22' functional array layer
100. 110 semiconductor substrate
101. 111 semiconductor substrate
102. 112 transistor
1021. 1121 Source electrode
1022. 1122 drain electrode
1023. 1123 Gate Structure
103. 113 shallow trench isolation structure
104. 114 passivation layer
200. 210 first dielectric layer
300. 310 contact element
301. 311 first contact element
302. 312 second contact element
400. 410 second dielectric layer
500. 510 metal layer
501. 511 first metal layer
502. 512 second metal layer
600. 610 metal plug
a. Distance b
A. Regions A' and B
Height H
The distances between D1, D2 and D3
W1, W2, W3 Width
L1, L2, L3 Length
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structures are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. As used herein, "between … …" is meant to include both endpoints.
In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed freely, and the layout of the components may be more complicated.
Comparative example
In a comparative example, a semiconductor device is exemplified by a 3D NAND, as shown in fig. 1, which is a schematic structural diagram of the 3D NAND in the present comparative example, wherein the 3D NAND has a first wafer 10 and a second wafer 20, the first wafer 10 includes a metal interconnection layer 11, the second wafer 20 includes an array interconnection layer 21 and a functional array layer 22, and the 3D NAND is electrically connected to the metal interconnection layer 11 and the array interconnection layer 21 through a bonding process, so that the first wafer 10 and the second wafer 20 are electrically connected to each other, and the second wafer 20 is electrically controlled through the first wafer 10.
It should be noted that, in fig. 1, for simplicity, only a part of the device structure is illustrated in the edge region of the first wafer 10, but it is understood that the first wafer 10 has the transistors, the contact elements, the metal interconnection layers, the shallow trench isolation structures, and other elements throughout, and specific elements and distributions thereof may be selected and arranged as needed.
Specifically, since the conventional 3D NAND is implemented by fabricating a peripheral circuit (peripheral) and a stacked memory Array (Array) on the same wafer, in this comparative example, in order to reduce the device size, improve the integration level, and improve the device quality, the peripheral circuit and the stacked memory Array are respectively fabricated on different wafers, and the peripheral circuit and the stacked memory Array are electrically connected through a bonding process.
Fig. 2 is an enlarged schematic view of a region a of the first wafer 10, wherein the specific structure and manufacturing method of the second wafer 20 can be referred to the prior art and are not described herein, and the first wafer 10 can also be applied to other semiconductor devices as required, and is not limited herein.
The first wafer 10 includes a semiconductor substrate 100, a first dielectric layer 200, a contact element 300, and the metal interconnection layer 11. The semiconductor substrate 100 includes a semiconductor substrate 101, a transistor 102, a shallow trench isolation structure 103, and a passivation layer 104, wherein the transistor 102 includes a source 1021, a drain 1022, and a gate 1023, and the transistor 102 can be a CMOS transistor, but is not limited thereto; the metal interconnection layer 11 includes a second dielectric layer 400, a metal layer 500 and a metal plug 600, but is not limited thereto, and the metal interconnection layer 11 may also include other structures. The contact element 300 includes a first contact element 301 in contact with an active region and a second contact element 302 in contact with the gate structure 1023, so as to form a capacitor through the first contact element 301 and the second contact element 302, and the first contact element 301 and the second contact element 302 are electrically connected to the outside, i.e., the array interconnection layer 21 in the second wafer 20, respectively through a first metal layer 501, a second metal layer 502 and a metal plug 600 located between the first metal layer 501 and the second metal layer 502 in the metal interconnection layer 11, it can be understood that the first contact element 301 and the second contact element 302 form two plates of the capacitor, and the capacitor further includes an insulating medium, i.e., the first dielectric layer 200, located between the first contact element 301 and the second contact element 302.
Since the contact element 300 is in contact with the active region and the gate structure 1023, the distance b between the contact element 300 and the gate structure 1023 and the overlapping distance a between the gate structure 1023 and the contact element 300 need to be considered when forming the first contact element 301 and the second contact element 302, so that it is difficult to further prepare the capacitor with high capacitance.
In addition, as the semiconductor technology advances toward high density and high capacity, the number of functional array layers 22 in the second wafer 20 is also increasing in the 3D NAND architecture, so that the first wafer 10 is required to have a denser distribution, and thus the capacitor on the transistor 102 is also difficult to meet the requirement.
Furthermore, in the 3D NAND, in order to reduce the size of the 3D NAND, the first dielectric layer 200 is generally thin, so that the height of the contact element 300 is formed to be small, and thus the capacitance that the capacitor formed by the contact element 300 can provide is limited in height, thereby also limiting the feasibility of forming the capacitor with high capacitance.
Examples
To further solve the limitation of the semiconductor device in the comparative example on the high capacitance, the following is further improved.
Referring to fig. 3, the embodiment provides a 3D NAND, the 3D NAND includes a first wafer 10 ' and a second wafer 20 ', the first wafer 10 ' includes a metal interconnection layer 11 ', the second wafer 20 ' includes an array interconnection layer 21 ' and a functional array layer 22 ', and the 3D NAND is electrically connected to the metal interconnection layer 11 ' and the array interconnection layer 21 ' through a bonding process, so as to electrically connect the first wafer 10 ' and the second wafer 20 ', and perform circuit control on the second wafer 20 ' through the first wafer 10 '.
It should be noted that, in fig. 3, for simplicity of illustration, only a portion of the device structure is illustrated in the edge region of the first wafer 10 ', but it is understood that the transistors, the contact elements, the metal interconnection layers, the shallow trench isolation structures, and the like are all provided in the entire first wafer 10', and specific distribution may be set as required, and in the illustration, a specific electrical connection manner between the contact elements in the first wafer 10 'and the metal interconnection layers 11' may be selected as required, and only the contact elements located on the same shallow trench isolation structure need to be able to form a capacitor, and the specific electrical connection manner is not limited herein.
Fig. 4 is an enlarged schematic view of a region a 'of the first wafer 10', wherein the specific structure and manufacturing method of the second wafer 20 'are not described herein, but refer to the prior art, and the first wafer 10' may be applied to other semiconductor devices according to the requirement, which is not limited herein.
Wherein the first wafer 10' comprises:
a semiconductor substrate 110, wherein the semiconductor substrate 110 includes a transistor 112 and a shallow trench isolation structure 113;
a dielectric layer on the semiconductor substrate 110, the dielectric layer covering the transistor 112 and the shallow trench isolation structure 113;
a contact element 310, wherein the contact element 310 penetrates through the dielectric layer, and the contact element 310 includes at least one first contact element 311 and at least one second contact element 312 which are in contact with the same shallow trench isolation structure 113, so that a capacitor is formed by the first contact element 311 and the second contact element 312;
a metal interconnect layer 11 ', the metal interconnect layer 11 ' being on the dielectric layer, and the metal interconnect layer 11 ' being electrically connected with the contact element 310.
Specifically, the semiconductor substrate 110 includes a semiconductor substrate 111, a transistor 112, a shallow trench isolation structure 113, and further may further include a passivation layer 114, and the transistor 112 includes a source 1121, a drain 1122, and a gate structure 1123, and the transistor 112 may be a CMOS transistor, but is not limited thereto; the dielectric layer is a first dielectric layer 210; the metal interconnection layer 11' includes a second dielectric layer 410, a metal layer 510, and a metal plug 610. The specific structure and type of the semiconductor substrate 110 and the metal interconnection layer 11' are not overly limited herein. The contact element 310 includes the first contact element 311 and the second contact element 312 which are in contact with the same shallow trench isolation structure 113, so that the first contact element 311 and the second contact element 312 form the capacitor, it can be understood that the first contact element 311 and the second contact element 312 form two plates of the capacitor, and the capacitor further includes an insulating medium, i.e., the first dielectric layer 210, between the first contact element 311 and the second contact element 312. Further, the contact element 310 further includes a contact element located on the transistor 112 and electrically connected to the gate structure 1123 and the active region of the transistor 112, which may refer to a comparative example and is not described herein again. Wherein the contact element 310 is electrically connected with the metal interconnection layer 11 ' so that the contact element 310 and the array interconnection layer 21 ' in the second wafer 20 ' can be connected through the metal interconnection layer 11 ' to perform circuit control on the second wafer 20 '.
In the embodiment, the contact element 310 is disposed on the sti structure 113 without considering the position of the contact element 310 and the transistor 112, and the size of the contact element 310 is limited to the precision of the etching process, so that the distance between the first contact element 311 and the second contact element 312 can be effectively reduced to form the capacitor with a smaller distance to increase the capacitance.
As an example, in the capacitor, a distance D1 is provided between the first contact element 311 and the second contact element 312, and a value of the distance D1 is in a range of 0.1 μm to 0.15 μm.
Specifically, referring to fig. 5a, an enlarged schematic top view of the area B in fig. 4 is shown. In accordance with the principle of the capacitor, when the distance D1 between the first contact element 311 and the second contact element 312 is smaller, the capacitance of the capacitor can be increased. Further, when the distance D1 is smaller, the number of the contact elements 310 can be increased in a limited area to increase the distribution density of the capacitor, so as to expand the application range of the semiconductor device. The range of the distance D1 may include any range of values from 0.1 μm to 0.15 μm, such as 0.12 μm, 0.14 μm, and the like, which is not limited herein.
As an example, the range of the area S between the first contact element 311 and the second contact element 312 includes 0.01 μm2～100μm2。
Specifically, according to the principle of the capacitor, when the area S facing the first contact element 311 and the second contact element 312 is larger, the capacitance of the capacitor can be increased. To avoid increasing the size of the semiconductor device, therefore, the size of the contact element 310 is related to the size of the shallow trench isolation structure 113 and the thickness of the first dielectric layer 210, in this embodiment, the range of the area S may include 1 μm2、10μm2、50μm2、100μm2And the like, and the values within any range may be specifically selected as required.
By way of example, the contact element 310 may be formed with an aspect ratio in a range from 1:1 to 2500:1, preferably from 200:1 to 2500:1 or from 1:1 to 20: 1.
Specifically, the contact element 310 includes a square shape with an aspect ratio of 1:1, but may also include a rectangular shape, which may be selected as desired.
The length of the first contact element 311 and the second contact element 312 ranges from 0.05 μm to 100 μm.
Specifically, in this embodiment, referring to fig. 5a, the first contact element 311 and the second contact element 312 are in a wall shape, wherein a length L1 of the first contact element 311 and the second contact element 312 may range from 0.05 μm to 100 μm. In the present embodiment, since the wall shape is adopted, in order to increase the capacitance of the capacitor, it is preferable to have a larger length L1, such as, but not limited to, a value within a range from 10 μm to 100 μm, for example, 10 μm, 25 μm, 50 μm, 80 μm, 100 μm, etc. As shown in fig. 5b and 5c, the contact elements 310 are rectangular in shape, and the lengths L2 and L3 are smaller than the length L1, and the lengths L2 and L3 can be 0.05 μm, 0.1 μm, 0.2 μm, 0.5 μm, 0.8 μm, and the like in the range of 0.05 μm to 1.0 μm, so as to increase the distribution density of the capacitor and increase the capacitance by providing the contact elements 310 with smaller sizes, thereby expanding the application range of the capacitor,
the width of the first contact element 311 and the width of the second contact element 312 range from 40nm to 50 nm.
Specifically, when the width of the contact element 310 is smaller, the number of the contact elements 310 may be increased in a limited area to increase the distribution density of the capacitor, but the width of the contact element 310 is also affected by the etching process, so in this embodiment, the width of the contact element 310 may be set to a value in any range of 45nm, 48nm, 50nm, and the like, and is not limited herein.
As shown in fig. 5a, since the contact element 310 employs the length L1 having a large value to increase capacitance by increasing the area S of the capacitor, the aspect ratio of the contact element 310 preferably ranges from any value within a range of 200:1 to 2500: 1. In addition, as shown in fig. 5b and 5c, in order to increase the capacitance, it can be implemented by providing a plurality of capacitors having small sizes, for example, the length ratio of the contact element 310 can be any value within the range of 1:1 to 20:1, so as to increase the number of capacitors.
For example, the same shallow trench isolation structure 113 includes N first contact elements 311 and N second contact elements 312 correspondingly disposed to form N capacitors, where N is a positive integer and N ≧ 2.
Specifically, referring to fig. 5a, in the present embodiment, 2 first contact elements 311 and second contact elements 312 are alternately disposed, so as to form 2 capacitors disposed in parallel, but the number of the first contact elements 311 and second contact elements 312 is not limited thereto, and in another embodiment, only 1 first contact element 311 and second contact element 312 disposed correspondingly, or a plurality of first contact elements 311 and second contact elements 312 disposed correspondingly, such as 3, 4, 5, etc., may be included, specifically, the selection may be performed according to the size and the process requirement of the shallow trench isolation structure 113, which is not limited herein, and the arrangement of the capacitors in this embodiment is preferably suitable for the contact elements 310 with a larger aspect ratio, but the distribution of the contact elements 310 with a larger size is not limited thereto, it is understood that, if necessary, the contact elements 310 with the length-width ratio ranging from 200:1 to 2500:1 may also be arranged as shown in fig. 5b and 5c, or other arrangements satisfying the capacitor principle, which is not limited herein.
For example, on the same shallow trench isolation structure 113, X first contact elements 311 and X second contact elements 312 are correspondingly disposed along an X direction of the shallow trench isolation structure 113, and Y first contact elements 311 and Y second contact elements 312 are correspondingly disposed along a Y direction of the shallow trench isolation structure 113, where X and Y are positive integers, and at least one of X and Y is greater than 1.
Specifically, referring to fig. 5b, on the same shallow trench isolation structure 113, along the X direction of the shallow trench isolation structure 113, 2 first contact elements 311 and second contact elements 312 are correspondingly disposed, and along the Y direction of the shallow trench isolation structure 113, 4 first contact elements 311 and second contact elements 312 are correspondingly disposed, where X and Y are perpendicular to each other, but not limited thereto, and values of X and Y may be set as required. Wherein, the width W2 can be 40 nm-50 nm, the length L2 can be 0.05 μm-100 μm, preferably 0.05 μm-1.0 μm, and the distance D2 can be 0.1 μm-0.15 μm. Compared to fig. 5a, in fig. 5b, the distance D2 may have the same value as that of D1, and the width W2 may have the same value as that of W1, except that in fig. 5b, the shape of the contact element 310 is rectangular, i.e., the length L2 is smaller than the length L1, for example, the length L2 may be 0.05 μm, 0.1 μm, 0.2 μm, 0.5 μm, 0.8 μm, and the like, so as to increase the distribution density of the capacitor by reducing the length L2, so as to expand the application range of the capacitor, but the values of D2, W2, and L2, and the values of x and y are not limited thereto. In the present embodiment, the plurality of capacitors are formed in parallel, but not limited thereto.
Further, as an example, the capacitors formed by the first contact elements 311 and the second contact elements 312 are arranged in a staggered manner.
Specifically, referring to fig. 5c, the capacitors formed on the same shallow trench isolation structure 113 are arranged in a staggered manner. Wherein, the width W3 can be 40 nm-50 nm, the length L3 can be 0.05 μm-100 μm, preferably 0.05 μm-1.0 μm, and the distance D3 can be 0.1 μm-0.15 μm. In this embodiment, the distribution density of the capacitor can be further improved compared to that in fig. 5b to further expand the application area of the capacitor, but the values of D3, W3, and L3 and the values in the X and Y directions are not limited thereto.
As an example, the capacitors are connected in parallel or in series, or in combination.
Specifically, according to specific needs, the capacitors located on the same shallow trench isolation structure 113 may be connected in parallel or in series by controlling the metal interconnection layer 11', so as to further expand the application range of the semiconductor device, and the specific connection manner may be selected according to needs, which is not limited herein, and only needs to satisfy the application principle of the capacitors.
As an example, the height H of the first contact element 311 and the second contact element 312 ranges from 0.2 μm to 1.0 μm.
Specifically, the larger the range of the height H of the first contact element 311 and the second contact element 312 is, the more beneficial the effective area of the capacitor is to be increased, so as to increase the capacitance of the capacitor, but the increase of the height H will certainly increase the size of the semiconductor device, therefore, in this embodiment, the height H of the first contact element 311 and the second contact element 312 is preferably set to be, for example, 0.4 μm, 0.5 μm, 0.6 μm, 0.8 μm, so as to reduce the size of the semiconductor device, but the range of the height H is not limited thereto, and can be selected as required.
Referring to fig. 3 and 6, this embodiment further provides a method for manufacturing a semiconductor device, which can be used to manufacture the semiconductor device, but the method for manufacturing the semiconductor device is not limited thereto, and details about the structure of the semiconductor device are not described herein. The preparation method of the semiconductor device specifically comprises the following steps:
providing a semiconductor substrate 110, wherein the semiconductor substrate 110 comprises a transistor 112 and a shallow trench isolation structure 113;
forming a dielectric layer on the semiconductor substrate 110, and etching the dielectric layer to form a contact hole (not shown) penetrating to the shallow trench isolation structure;
filling the contact hole to form a contact element 310, wherein the contact element 310 includes a first contact element 311 and a second contact element 312 which are in contact with the same shallow trench isolation structure 113, so as to form a capacitor through the first contact element 311 and the second contact element 312;
a metal interconnect layer 11 'is formed on the dielectric layer, and the metal interconnect layer 11' is electrically connected to the contact element 310.
Specifically, referring to fig. 3 to fig. 5c, the surface of the transistor 112 may include a passivation layer 114, and the passivation layer 114 may be made of, for example, SiN; the dielectric layers include the first dielectric layer 210 and the second dielectric layer 410, and the material of the dielectric layers can be BCB, silicon oxide, TEOS, etc.; the material of the first contact element 311 and the second contact element 312 can be Cu metal, W metal, etc., and the selection of the specific material is not limited herein.
As an example, in the capacitor, a pitch between the first contact element 311 and the second contact element 312 ranges from 0.1 μm to 0.15 μm, and an area between the first contact element 311 and the second contact element 312 ranges from 0.01 μm2～100μm2。
By way of example, the contact element 310 may be formed to have an aspect ratio in a range of 200:1 to 2500:1 or 1:1 to 20: 1; the length of the contact element 310 is formed to range from 0.05 μm to 100 μm, preferably from 0.05 μm to 1.0 μm and from 10 μm to 100 μm; the width of the contact element 310 is formed to have a range of 40nm to 50 nm.
As an example, the height of the contact element 310 may be formed to have a range of 0.2 μm to 1.0 μm.
As an example, the number of the capacitors formed on the same shallow trench isolation structure 113 includes N, where N is a positive integer and N ≧ 2.
As an example, the capacitors on the same shallow trench isolation structure 113 are arranged in parallel along the X direction of the shallow trench isolation structure 113.
As an example, on the same shallow trench isolation structure 113, X capacitors are included along an X direction of the shallow trench isolation structure 113, Y capacitors are included along a Y direction of the shallow trench isolation structure 113, X and Y are perpendicular to each other, where X and Y are positive integers, and at least one of X and Y is greater than 1.
As an example, the capacitors on the same shallow trench isolation structure 113 are arranged in a staggered manner.
As an example, the capacitor comprises one or a combination of a parallel connection or a series connection.
As an example, referring to fig. 3, the following steps are also included:
providing a second wafer 20 ', the second wafer 20 ' comprising a functional array layer 22 ' and an array interconnect layer 21 ' electrically connected to the functional array layer 22 ';
bonding the metal interconnection layer 11 'and the array interconnection layer 21' to electrically connect the array interconnection layer 21 'and the metal interconnection layer 11'.
Wherein the contact element 310 is electrically connected with the metal interconnection layer 11 ' so that the contact element 310 and the array interconnection layer 21 ' in the second wafer 20 ' can be connected through the metal interconnection layer 11 ' to perform circuit control on the second wafer 20 '.
In summary, the semiconductor substrate of the present invention includes a transistor and a shallow trench isolation structure, a dielectric layer is formed on the semiconductor substrate, a contact element is formed in the dielectric layer, and the contact element includes a first contact element and a second contact element contacting with the same shallow trench isolation structure, so as to form a capacitor through the first contact element and the second contact element, and a metal interconnection layer is formed on the dielectric layer. On the premise of not changing the size of a semiconductor device, the first contact element and the second contact element with smaller distance are arranged on the shallow trench isolation structure, so that the distance between capacitors can be effectively reduced, and the capacitance can be increased; the area of the capacitor can be effectively increased by increasing the areas of the first contact element and the second contact element on the shallow trench isolation structure, so that the capacitance is increased; the distribution density of the capacitor can be increased by increasing the number of the contact elements on the shallow trench isolation structure so as to increase the capacitance; the connection of the capacitor can be flexibly controlled through the metal interconnection layer so as to expand the application range of the semiconductor device.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (12)

1. A semiconductor device, characterized in that the semiconductor device comprises:
the semiconductor substrate comprises a transistor and a shallow trench isolation structure;
the dielectric layer is positioned on the semiconductor substrate and covers the transistor and the shallow trench isolation structure;
the contact element penetrates through the dielectric layer and comprises at least one first contact element and at least one second contact element which are in contact with the same shallow trench isolation structure, so that a capacitor is formed by the first contact element and the second contact element;
a metal interconnect layer on the dielectric layer and electrically connected with the contact element.
2. The semiconductor device according to claim 1, wherein: the aspect ratio of the contact element ranges from 200:1 to 2500: 1.
3. The semiconductor device according to claim 2, wherein: the same shallow trench isolation structure comprises N capacitors, wherein N is a positive integer and is more than or equal to 2.
4. The semiconductor device according to claim 2, wherein: and the capacitors on the same shallow trench isolation structure are arranged in parallel along the X direction of the shallow trench isolation structure.
5. The semiconductor device according to claim 1, wherein: the aspect ratio of the contact element ranges from 1:1 to 20: 1.
6. The semiconductor device according to claim 5, wherein: the method comprises the steps of forming a shallow trench isolation structure on a substrate, forming a plurality of capacitors on the same shallow trench isolation structure along the X direction of the shallow trench isolation structure, forming a plurality of capacitors along the Y direction of the shallow trench isolation structure, wherein the capacitors are mutually vertical to each other, X and Y are positive integers, and at least one of X and Y is larger than 1.
7. The semiconductor device according to claim 5, wherein: and the capacitors on the same shallow trench isolation structure are arranged in a staggered manner.
8. The semiconductor device according to claim 1, wherein: the capacitors include one or a combination of parallel or series connections.
9. A semiconductor device, characterized in that the semiconductor device comprises:
a first wafer, the first wafer comprising:
the semiconductor substrate comprises a transistor and a shallow trench isolation structure;
the dielectric layer is positioned on the semiconductor substrate and covers the transistor and the shallow trench isolation structure;
the contact element penetrates through the dielectric layer and comprises at least one first contact element and at least one second contact element which are in contact with the same shallow trench isolation structure, so that a capacitor is formed by the first contact element and the second contact element;
a metal interconnect layer on the dielectric layer and electrically connected to the contact element;
a second wafer comprising a functional array layer and an array interconnect layer electrically connected to the functional array layer;
wherein the metal interconnect layer is electrically connected to the array interconnect layer.
10. The semiconductor device according to claim 9, wherein: the aspect ratio of the contact element ranges from 200:1 to 2500:1 or from 1:1 to 20: 1.
11. A method for manufacturing a semiconductor device, comprising the steps of:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a transistor and a shallow trench isolation structure;
forming a dielectric layer on the semiconductor substrate, and etching the dielectric layer to form a contact hole penetrating to the shallow trench isolation structure;
filling the contact hole to form a contact element, wherein the contact element comprises at least one first contact element and at least one second contact element which are in contact with the same shallow trench isolation structure, so that a capacitor is formed by the first contact element and the second contact element;
and forming a metal interconnection layer on the dielectric layer, wherein the metal interconnection layer is electrically connected with the contact element.
12. The method for manufacturing a semiconductor device according to claim 11, wherein: the contact element is formed with an aspect ratio in a range of 200:1 to 2500:1 or 1:1 to 20: 1.
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