CN111755446A - Semiconductor structure - Google Patents

Abstract

The invention provides a semiconductor structure, which relates to the technical field of semiconductor production and comprises a first wafer and a second wafer which are stacked into a whole; the first wafer comprises a capacitance area and a non-capacitance area; the second wafer comprises an array region and a control region; the capacitance area corresponds to the array area, and the non-capacitance area corresponds to the control area; the first wafer and the second wafer are electrically connected. The semiconductor structure in the technical scheme provided by the invention is formed by stacking two wafers, and compared with the prior art, the density and the production speed of the semiconductor structure on the wafers can be improved.

Description

Semiconductor structure

Technical Field

The invention relates to the technical field of semiconductor production, in particular to a semiconductor structure.

Background

The structures of Memory chips such as DRAM (Dynamic Random Access Memory) and other semiconductor devices are mostly planar structures, and the semiconductor devices can be scaled to smaller sizes by improving process technology, circuit design, programming algorithm, and manufacturing process. However, as the feature size of semiconductor devices approaches the lower limit, planar processes and fabrication techniques become challenging and costly.

As electronic devices and memories are being miniaturized and thinned, higher demands are being made on the size and thickness of memory chips.

In addition, when the memory chips such as DRAM are manufactured by adopting a planar process and a manufacturing technology, the production period is longer and the production speed is slower due to the limitation of the process sequence.

Therefore, how to increase the density and production speed of semiconductor chips such as memory chips on a wafer is a problem to be solved.

It is to be noted that the information invented in the above background section is only for enhancing the understanding of the background of the present invention, and therefore, may include information that does not constitute prior art known to those of ordinary skill in the art.

Disclosure of Invention

The present invention is directed to a semiconductor structure that improves, at least to some extent, the density and production speed of the semiconductor structure on a wafer.

Additional features and advantages of the invention will be set forth in the detailed description which follows, or may be learned by practice of the invention.

According to an embodiment of the present invention, a semiconductor structure is provided, which includes a first wafer and a second wafer stacked as a single body; the first wafer comprises a capacitance area and a non-capacitance area; the second wafer comprises an array region and a control region; the capacitance area corresponds to the array area, and the non-capacitance area corresponds to the control area; the first wafer and the second wafer are electrically connected.

In one embodiment, the capacitive region of the first wafer includes a capacitive structure and the non-capacitive region includes a first conductive interconnect structure.

In one embodiment, the array region of the second wafer includes an active region, the control region of the second wafer includes a second conductive interconnect structure and a control structure, and the second conductive interconnect structure and the control structure are electrically connected.

In one embodiment, the capacitive structure comprises: a second electrode located in the capacitance region; a dielectric layer disposed on the second electrode; a first electrode disposed on the dielectric layer.

In one embodiment, the capacitor region is provided with an isolation layer, and the second electrode is disposed on the isolation layer.

In one embodiment, the capacitive structure comprises: a first electrode located in the capacitive region; a dielectric layer disposed on the first electrode; a second electrode disposed on the dielectric layer.

In one embodiment, the capacitor region is provided with an isolation layer, and the first electrode is disposed on the isolation layer.

In one embodiment, the first electrode of the first wafer is electrically connected to the active region of the second wafer, and the first conductive interconnect structure of the first wafer is electrically connected to the second conductive interconnect structure of the second wafer.

In one embodiment, the first conductive interconnect structure of the first wafer includes a top conductive layer, a first conductive plug, a second conductive plug; the first conductive plug is connected with the top conductive layer and the second electrode, and the second conductive plug is connected with the top conductive layer and the second conductive interconnection structure; the number of the first conductive plugs is at least 1, and the number of the second conductive plugs is at least 1.

In one embodiment, the first wafer first conductive interconnect structure includes a top conductive layer, a first conductive plug, a second conductive plug, and a middle interconnect structure; the second conductive plug comprises a first second conductive plug and a second conductive plug; the first conductive plug is connected with the top conductive layer and the second electrode, the first conductive plug is connected with the top conductive layer and the middle interconnection structure, and the second conductive plug is connected with the middle interconnection structure and the second conductive interconnection structure; the number of the first conductive plugs is at least 1, the number of the first second conductive plugs is at least 1, and the number of the second conductive plugs is at least 1.

In one embodiment, the middle interconnection structure comprises at least one middle conductive layer, and the middle conductive layers of more than one layer are connected through a third conductive plug; the number of the third conductive plugs is at least 1.

In one embodiment, the second conductive interconnection structure comprises at least two lower conductive layers, and the lower conductive layers are connected through a fourth conductive plug; the number of the fourth conductive plugs is at least 1.

In one embodiment, the first electrode of the first wafer and the active region of the second wafer are electrically connected through fifth conductive plugs, and the number of the fifth conductive plugs is at least 1.

In one embodiment, the first wafer includes a first substrate, the capacitor structure is located in the first substrate, and the first conductive interconnection structure is connected to the first substrate; the first substrate includes a first dielectric material therein.

In one embodiment, the first substrate is a doped substrate.

In one embodiment, the capacitive area further comprises a capacitive connection member connecting the second electrode of the capacitive structure.

In one embodiment, the capacitive connecting member is connected with the first conductive interconnect structure or the second conductive interconnect structure.

In one embodiment, the first wafer includes a second dielectric material surrounding the first conductive interconnect structure, the second dielectric material being the same as the first dielectric material.

In one embodiment, the first wafer includes a second dielectric material surrounding the first conductive interconnect structure, the second dielectric material being different from the first dielectric material.

In one embodiment, the orthographic projection between the lower conductive layers in the second conductive interconnect structure partially overlaps.

In one embodiment, the material of the first dielectric layer and the second dielectric layer comprises one of oxide, nitride, silicide, carbide or amorphous carbon, or any combination thereof.

In one embodiment, the first and second conductive interconnect structures comprise one or any combination of copper, aluminum, tin, or tungsten.

In one embodiment, the first conductive interconnect structure includes a first conductive layer exposed at a surface of the first wafer in contact with the second wafer; the second conductive interconnect structure comprises a second conductive layer exposed on a surface of the second wafer in contact with the first wafer; the first conductive layer is connected to the second conductive layer.

In one embodiment, the control structure comprises a transistor structure including a source, a drain, and a gate.

In one embodiment, the active region has a buried gate structure, a fifth conductive plug and a bit line plug therein; the bit line plug is positioned above the middle of the active region, the fifth conductive plug is positioned above two ends of the active region, and the fifth conductive plug is exposed on the surface of the second wafer, which is in contact with the first wafer.

The technical scheme provided by the embodiment of the invention has the following beneficial effects:

according to the technical scheme provided by the embodiment of the invention, the semiconductor structure is formed by stacking two wafers, compared with the prior art, the density of the semiconductor structure on the wafers is improved, so that the first wafer and the second wafer can be produced simultaneously, and the production speed of the semiconductor structure is also improved.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention. It is obvious that the drawings in the following description are only some embodiments of the invention, and that for a person skilled in the art, other drawings can be derived from them without inventive effort.

FIG. 1 schematically illustrates a cross-sectional view of a semiconductor structure in one embodiment of the invention;

FIG. 2a schematically illustrates a cross-sectional view of a capacitive region in one embodiment of the invention;

FIG. 2b schematically shows a cross-sectional view of a capacitive area in another embodiment of the invention;

FIG. 3 schematically illustrates a cross-sectional view of a second wafer in an embodiment of the invention;

FIG. 4 schematically illustrates a cross-sectional view of a first wafer in an embodiment of the invention;

FIG. 5a schematically illustrates a cross-sectional view of a capacitive region in yet another embodiment of the present invention;

FIG. 5b schematically shows a cross-sectional view of a capacitive region in a further embodiment of the invention;

FIG. 6 schematically illustrates a cross-sectional view of a semiconductor structure in another embodiment of the invention;

FIG. 7a schematically illustrates a cross-sectional view of a semiconductor structure in yet another embodiment of the present invention;

FIG. 7b schematically illustrates a cross-sectional view of a semiconductor structure in yet another embodiment of the invention;

FIG. 7c schematically illustrates a cross-sectional view of a semiconductor structure in yet another embodiment of the present invention;

FIG. 7d schematically illustrates a cross-sectional view of a semiconductor structure in a further embodiment of the invention;

FIG. 8 schematically illustrates a cross-sectional view of a semiconductor structure in yet another embodiment of the invention;

figure 9 schematically illustrates a cross-sectional view of a semiconductor structure in yet another embodiment of the invention.

Detailed Description

Exemplary embodiments will now be described more fully with reference to the accompanying drawings. The exemplary embodiments, however, may be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus their detailed description will be omitted.

Although relative terms, such as "upper" and "lower," may be used in this specification to describe one element of an icon relative to another, these terms are used in this specification for convenience only, e.g., in accordance with the orientation of the examples described in the figures. It will be appreciated that if the module of the icon is turned upside down, the component described as "upper" will become the component "lower". Other relative terms, such as "high," "low," "top," "bottom," "left," "right," and the like are also intended to have similar meanings. When a structure is "on" another structure, it may mean that the structure is integrally formed with the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via another structure.

The terms "a," "an," "the," and the like are used to denote the presence of one or more elements/components/parts; the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. other than the listed elements/components/etc.

In the related art DRAM structure, since a plurality of different processes are performed on the same wafer when the DRAM structure is manufactured, the manufacturing of different parts cannot be performed simultaneously, resulting in a long production process time. In addition, when the DRAM structure is manufactured by adopting a planar process, the number of devices on a unit area wafer is small.

A stacked wafer structure formed by stacking semiconductor wafers can function as a single device, thereby achieving performance improvements with a smaller footprint than conventional planar processes.

Here, an example in which a DRAM chip is used as the semiconductor chip is described, but the semiconductor chip is not limited to the DRAM chip.

Embodiments of the present disclosure provide a semiconductor structure having a stacked wafer structure. Thus, the two or more wafers can be produced simultaneously on different production lines, and the semiconductor structure is formed through bonding and subsequent processes, thereby achieving the technical effect of shortening the production time. The following detailed description of exemplary embodiments of the disclosure refers to the accompanying drawings.

Fig. 1 schematically illustrates a cross-sectional view of a semiconductor structure according to an exemplary embodiment of the disclosure, and referring to fig. 1, a semiconductor structure 400 according to an embodiment of the disclosure includes a first wafer and a second wafer stacked as a single body. The first wafer comprises a capacitance area and a non-capacitance area. As shown in fig. 3, the second wafer has an array region 320 and a control region 330. As shown in fig. 1, the array region 320 corresponds to the capacitor region, and the first wafer is electrically connected to the second wafer.

In this aspect, a stacked wafer structure semiconductor structure is formed that can increase the density of semiconductor structures on a wafer compared to fabricating semiconductor structures on a planar structure.

In addition, two wafers forming the stacked structure can be produced simultaneously and then bonded, so that compared with the method that various procedures are sequentially executed on one wafer to manufacture a semiconductor structure in a planar structure, the production time is saved, and the production efficiency is improved.

As shown in fig. 2a, the capacitor region has a capacitor structure 220, and the capacitor structure 220 includes a first electrode 223 and a second electrode 221. The first electrode 223 of the capacitive structure is electrically connected to the array region 320.

The array region of the second wafer includes an active region, the control region of the second wafer includes a second conductive interconnect structure and a control structure, and the second conductive interconnect structure and the control structure are electrically connected.

As shown in fig. 3, the active region has a buried gate structure 321, a fifth conductive plug and a bit line plug 322 therein; the bit line plug 322 is located above the middle of the active region, and the fifth conductive plugs are located above the two ends of the active region, including the fifth conductive plug 424 and the fifth conductive plug 425. The fifth conductive plug is exposed on the surface of the second wafer, which is in contact with the first wafer. A bit line 323 is disposed above the bit line plug 322.

The fifth conductive plug is electrically connected to the first electrode of the capacitor. The number of the fifth conductive plugs is the same as that of the capacitors, and each fifth conductive plug corresponds to one capacitor.

The control structure includes a transistor structure 331 that includes a source, a drain, and a gate.

The first electrode 223 of the first wafer is electrically connected to the active region of the second wafer, and the first conductive interconnect structure of the first wafer is electrically connected to the second conductive interconnect structure of the second wafer.

In an exemplary embodiment of the disclosure, the periphery of the capacitor structure on the first wafer comprises a first dielectric material, and the first dielectric material is a substrate material.

As shown in fig. 4, the first wafer 200 includes a first substrate 210, and the capacitor structure is located in the first substrate 210. The first substrate 210 includes a first dielectric material therein. The first substrate 210 may be a doped substrate.

The periphery of the first conductive interconnection structure of the first wafer comprises a second dielectric material, and the second dielectric material and the first dielectric material can be the same or different.

The material of the second substrate 310 of the second wafer is the same as the material of the first substrate 210 of the first wafer, and may be a silicon substrate material.

In an exemplary embodiment of the present disclosure, the non-capacitive region includes a first conductive interconnect structure. The first conductive interconnect structure may be located entirely in the non-capacitive region. The structure can reduce the thickness of the semiconductor structure.

It may also take the form as shown in fig. 4, with a portion of the top metal layer of the first conductive interconnect structure being located in the capacitive region and another portion being located in the non-capacitive region.

As shown in fig. 8, in the semiconductor structure 700, the first conductive interconnection structure of the first wafer includes a top conductive layer 410, a first conductive plug 411, and a second conductive plug 4113; the first conductive plug 411 connects the top conductive layer 410 and the second electrode 221, and the second conductive plug 4113 connects the top conductive layer 410 and the second conductive interconnect structure; the number of the first conductive plugs is the same as that of the capacitor structures, and the number of the second conductive plugs is at least 1.

As shown in fig. 6 and 7a, the first conductive interconnect structure of the first wafer includes a top conductive layer 410, a first conductive plug 411, a second conductive plug 4112 and a middle interconnect structure; the second electrically conductive plug comprises a first second electrically conductive plug 4114 and a second electrically conductive plug 431; the first conductive plug 411 connects the top conductive layer and the second electrode, the first second conductive plug 4114 connects the top conductive layer and the middle interconnect structure, and the second conductive plug 431 connects the middle interconnect structure and the second conductive interconnect structure; the number of the first conductive plugs is at least 1, the number of the first second conductive plugs is at least 1, and the number of the second conductive plugs is at least 1.

As shown in fig. 7a, in the semiconductor structure 600, the middle interconnect structure includes a middle conductive layer 430. As shown in fig. 1 and 6, the middle interconnection structure may include two middle conductive layers connected to each other by a third conductive plug 431; the number of the third conductive plugs is at least 1.

As shown in fig. 1 and 3, the second conductive interconnect structure includes at least two lower conductive layers, i.e., a lower conductive layer 333 and a lower conductive layer 334, and the lower conductive layers are connected by a fourth conductive plug 336; the number of the fourth conductive plugs is at least 1. The lower conductive layer 333 and the control structure 332 are connected by a fourth conductive plug 332.

In the above solution, since the size, the number, and the position of each conductive interconnect layer of the first conductive interconnect structure and the second conductive interconnect structure inside the wafer can be adjusted, for example, the orthographic projection part between the lower conductive layers in the second conductive interconnect structure can be overlapped, so that a larger layout space is provided inside the semiconductor structure, and the density of the semiconductor structure on the wafer is increased.

In another embodiment, as shown in FIG. 7b, in a semiconductor structure 6100, a first conductive interconnect is connected to the first substrate 210. The first substrate 210 may be a silicon wafer substrate or other semiconductor material substrate. The second electrode of the capacitor structure 220 is connected to the first substrate 210 and the top conductive layer 410 of the first conductive interconnect structure is connected to the first substrate 210.

The first substrate 210 may be a doped substrate. The doping is performed to increase the conductivity of the first substrate 210, and the doping ions are not limited, such as boron ions, arsenic ions, phosphorus ions, and the like. The doping step is not limited to be performed for a certain time, and may be performed when the first wafer is formed, for example, the first substrate 210 is doped before the capacitor structure 220 is formed, or the first substrate 210 may be doped by defining a doped region on a stacked wafer formed after bonding by using a photolithography process.

Then, the second electrode of the capacitor structure 220 is connected to the doped conductive property of the first substrate 210, so as to apply the same potential, for example, the first substrate 210 is connected to a zero potential through the top conductive layer 410, so that the capacitor structure 220 in the first substrate 210 can store the same amount of charge. The process can greatly reduce the process steps, save the cost and save the space occupied by the semiconductor structure.

In an exemplary embodiment of the present disclosure, the capacitance region further includes a capacitance connection member connected to the second electrode of the capacitance structure. The capacitive connecting member may be connected with the first conductive interconnect structure or with the second conductive interconnect structure.

As shown in fig. 7c, in the semiconductor structure 6200, the capacitance connection member 412 is connected with the top conductive layer 410 of the first conductive interconnect structure. The second electrode of the capacitor structure is directly connected by the capacitor connecting member, the conventional method of connecting the second electrode through a conductive plug is omitted, the space occupied by the conductive interconnection structure in the longitudinal direction can be reduced, and the density of the first conductive interconnection structure is increased.

As shown in fig. 7d, in the semiconductor structure 6300, the capacitance connection member 225 is connected to the lower conductive layer 333 of the second conductive interconnect structure.

In the bonded stacked wafer, the capacitance connecting member is connected with the second conductive interconnection structure, so that the capacitance connecting member connected with the second electrode can be prevented from being formed on the top of the capacitor, the density of the semiconductor structure is increased, and the volume occupied by the semiconductor structure is reduced.

In the exemplary embodiments of the present disclosure, the material of the first dielectric layer and the second dielectric layer may be one of oxide, nitride, silicide, carbide or amorphous carbon, or any combination thereof.

In exemplary embodiments of the present disclosure, the first conductive interconnect structure and the second conductive interconnect structure may be one of copper, aluminum, tin, or tungsten, or any combination thereof.

After the non-capacitance area of the first wafer is removed by etching, a notch appears on the first wafer. After the dielectric layer material, the conductive plug material and the conductive layer material are deposited layer by layer at the gap, a second metal interconnection layer and a first metal interconnection layer can be formed to realize connection with the control area and the outside of the wafer.

In one embodiment, as shown in fig. 2a, the first wafer 200 includes a first substrate 210, and the capacitor structure 220 includes: a first electrode 223 located at the capacitance region; a dielectric layer 222 disposed on the first electrode; a second electrode 221 disposed on the dielectric layer 222.

As shown in fig. 2a, the cross section of the first electrode and the dielectric layer is U-shaped, the first electrode is formed in the first substrate, the dielectric layer is formed on the inner wall of the first electrode, and the second electrode is a cylindrical structure located on the inner wall of the dielectric layer.

In another embodiment, as shown in fig. 2b, the capacitor structure 220 includes: an isolation layer 224 located in the capacitor region; a first electrode 223 disposed on the isolation layer; a dielectric layer 222 disposed on the first electrode; a second electrode 221 disposed on the dielectric layer 222.

As shown in fig. 2b, the isolation layer is a bottomless cylinder structure, the cross-sections of the first electrode and the dielectric layer are U-shaped, the first electrode is formed on the inner wall of the isolation layer, the dielectric layer is formed on the inner wall of the first electrode, and the second electrode is a cylinder structure located on the inner wall of the dielectric.

The formation of the first wafer 200 and the formation of the second wafer 300 can be performed in different machines at the same time, which can save the production time of the semiconductor structure.

After the first wafer 200 and the second wafer 300 are bonded, a semiconductor structure 400 is formed. The bonding process enables the first wafer 200 and the second wafer 300 to be bonded and form a stacked wafer structure of high density interconnects.

In another embodiment, the layout of the capacitor area is different from that of fig. 2 b.

As shown in fig. 5a, the capacitor structure 520 includes a first electrode 522 located in the capacitor region; a dielectric layer 521 disposed on the first electrode; a second electrode 523 disposed on the dielectric layer.

As shown in fig. 5a, the cross section of the second electrode and the dielectric layer is U-shaped, the second electrode is formed on the inner wall of the isolation layer, the dielectric layer is formed on the inner wall of the second electrode, and the first electrode is a cylindrical structure located on the inner wall of the dielectric.

In another embodiment, as shown in fig. 5b, the capacitor structure 520 includes an isolation layer 510 in the capacitor region; a first electrode 522 disposed on the isolation layer; a dielectric layer 521 disposed on the first electrode; a second electrode 523 disposed on the dielectric layer.

As shown in fig. 5b, the isolation layer is a bottomless cylinder structure, the cross-section of the second electrode and the dielectric layer is U-shaped, the second electrode is formed on the inner wall of the isolation layer, the dielectric layer is formed on the inner wall of the second electrode, and the first electrode is a cylinder structure located on the inner wall of the dielectric.

The capacitor region shown in fig. 5b has a different opening direction of the U-shaped electrode compared to the capacitor region shown in fig. 2b, so that the semiconductor structure 500 including the capacitor region shown in fig. 5b is shown in fig. 6, and the semiconductor structure 400 including the capacitor region shown in fig. 2b is shown in fig. 1, and the semiconductor structure 500 is different from the semiconductor structure 400.

As shown in fig. 9, in a semiconductor structure 800, the first conductive interconnect structure includes a first conductive layer 720, the first conductive layer 720 is exposed to a surface of the first wafer that is in contact with the second wafer; the second conductive interconnect structure comprises a second conductive layer 710, the second conductive layer 710 being exposed to a surface of the second wafer in contact with the first wafer; the first conductive layer 720 is connected to the second conductive layer 710.

When the connection between the wafers is realized by adopting the connection mode of the conductive interconnection line and the conductive interconnection line, the process window of the connection can be enlarged, and the manufacturing difficulty is reduced.

As shown in fig. 1, the lowermost layer of the first conductive interconnection is a second conductive plug 431, the uppermost layer of the second conductive interconnection is a lower conductive layer 333, and the second conductive plug 431 is connected to the lower conductive layer 333.

In addition, there is a case where the lowermost layer of the first conductive interconnect structure is a conductive layer and the uppermost conductive plug of the second conductive interconnect structure is a conductive layer, and at this time, the lowermost conductive layer of the first conductive interconnect structure is connected to the uppermost conductive plug of the second conductive interconnect structure.

The semiconductor structure provided by the exemplary embodiment of the present invention is a stacked structure formed by bonding a first wafer and a second wafer, and compared with the prior art, the density of the semiconductor structure on the wafer is increased, so that the first wafer and the second wafer can be simultaneously produced, and the production speed of the semiconductor structure is also increased.

Other embodiments of the invention will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the invention following, in general, the principles of the invention and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.

It will be understood that the invention is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the invention is limited only by the appended claims.

Claims (25)

1. A semiconductor structure is characterized by comprising a first wafer and a second wafer which are stacked into a whole; wherein the content of the first and second substances,

the first wafer comprises a capacitance area and a non-capacitance area;

the second wafer comprises an array region and a control region;

the capacitance area corresponds to the array area, and the non-capacitance area corresponds to the control area;

the first wafer and the second wafer are electrically connected.

2. The semiconductor structure of claim 1, wherein the capacitive region of the first wafer comprises a capacitive structure and the non-capacitive region comprises a first conductive interconnect structure.

3. The semiconductor structure of claim 2, wherein the array region of the second wafer comprises an active region, the control region of the second wafer comprises a second conductive interconnect structure and a control structure, and the second conductive interconnect structure and the control structure are electrically connected.

4. The semiconductor structure of claim 3, wherein the capacitive structure comprises:

a second electrode located in the capacitance region;

a dielectric layer disposed on the second electrode;

a first electrode disposed on the dielectric layer.

5. The semiconductor structure of claim 4, wherein the capacitor region is provided with an isolation layer, and the second electrode is provided on the isolation layer.

6. The semiconductor structure of claim 3, wherein the capacitive structure comprises:

a first electrode located in the capacitive region;

a dielectric layer disposed on the first electrode;

a second electrode disposed on the dielectric layer.

7. The semiconductor structure of claim 6, wherein the capacitive region is provided with an isolation layer, and wherein the first electrode is provided on the isolation layer.

8. The semiconductor structure of claim 4 or 6, wherein the first electrode of the first wafer is electrically connected to the active region of the second wafer, and the first conductive interconnect structure of the first wafer is electrically connected to the second conductive interconnect structure of the second wafer.

9. The semiconductor structure of claim 8, wherein the first conductive interconnect structure of the first wafer comprises a top conductive layer, a first conductive plug, a second conductive plug;

the first conductive plug is connected with the top conductive layer and the second electrode, and the second conductive plug is connected with the top conductive layer and the second conductive interconnection structure;

the number of the first conductive plugs is at least 1, and the number of the second conductive plugs is at least 1.

10. The semiconductor structure of claim 8, wherein the first wafer first conductive interconnect structure comprises a top conductive layer, a first conductive plug, a second conductive plug, and a middle interconnect structure;

the second conductive plug comprises a first second conductive plug and a second conductive plug;

the first conductive plug is connected with the top conductive layer and the second electrode, the first conductive plug is connected with the top conductive layer and the middle interconnection structure, and the second conductive plug is connected with the middle interconnection structure and the second conductive interconnection structure;

the number of the first conductive plugs is at least 1, the number of the first second conductive plugs is at least 1, and the number of the second conductive plugs is at least 1.

11. The semiconductor structure of claim 10, wherein the middle interconnect structure comprises at least one middle conductive layer, and more than one middle conductive layers are connected by a third conductive plug;

the number of the third conductive plugs is at least 1.

12. The semiconductor structure of claim 11, wherein the second conductive interconnect structure comprises at least two lower conductive layers connected by a fourth conductive plug;

the number of the fourth conductive plugs is at least 1.

13. The semiconductor structure of claim 12, wherein the first electrode of the first wafer is electrically connected to the active region of the second wafer through fifth conductive plugs, and the number of the fifth conductive plugs is at least 1.

14. The semiconductor structure of claim 12,

the first wafer comprises a first substrate, the capacitor structure is located in the first substrate, and the first conductive interconnection structure is connected with the first substrate;

the first substrate includes a first dielectric material therein.

15. The semiconductor structure of claim 14, wherein the first substrate is a doped substrate.

16. The semiconductor structure of claim 15, wherein the capacitive region further comprises a capacitive connection member, the capacitive connection member connecting the second electrode of the capacitive structure.

17. The semiconductor structure of claim 16, wherein the capacitive connection member is connected with the first conductive interconnect structure or the second conductive interconnect structure.

18. The semiconductor structure of claim 17, wherein the first conductive interconnect structure of the first wafer comprises a second dielectric material surrounding the first conductive interconnect structure, the second dielectric material being the same as the first dielectric material.

19. The semiconductor structure of claim 18, wherein the first conductive interconnect structure of the first wafer includes a second dielectric material therearound, the second dielectric material being different from the first dielectric material.

20. The semiconductor structure of claim 19, wherein an orthogonal projection between lower conductive layers in the second conductive interconnect structure partially overlaps.

21. The semiconductor structure of claim 20, wherein a material of the first dielectric layer and the second dielectric layer comprises one of an oxide, a nitride, a silicide, a carbide, or amorphous carbon, or any combination thereof.

22. The semiconductor structure of claim 21, wherein the first and second conductive interconnect structures comprise one or any combination of copper, aluminum, tin, or tungsten.

23. The semiconductor structure of claim 22,

the first conductive interconnect structure comprises a first conductive layer exposed on a surface of the first wafer in contact with the second wafer;

the second conductive interconnect structure comprises a second conductive layer exposed on a surface of the second wafer in contact with the first wafer;

the first conductive layer is connected to the second conductive layer.

24. The semiconductor structure of claim 23,

the control structure includes a transistor structure including a source, a drain, and a gate.

25. The semiconductor structure of claim 24,

the active region is provided with a buried grid structure, a fifth conductive plug and a bit line plug;

the bit line plug is positioned above the middle of the active region, the fifth conductive plug is positioned above two ends of the active region, and the fifth conductive plug is exposed on the surface of the second wafer, which is in contact with the first wafer.

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