CN112951828B

CN112951828B - Semiconductor structure and forming method thereof

Info

Publication number: CN112951828B
Application number: CN202110374506.9A
Authority: CN
Inventors: 华文宇; 余兴
Original assignee: ICLeague Technology Co Ltd
Current assignee: ICLeague Technology Co Ltd
Priority date: 2021-04-07
Filing date: 2021-04-07
Publication date: 2022-04-22
Anticipated expiration: 2041-04-07
Also published as: CN112951828A

Abstract

A semiconductor structure and a method of forming the same, wherein the structure comprises: the first substrate comprises a plurality of first active regions and a plurality of second active regions; a plurality of word line gate structures located within the first substrate, the plurality of word line gate structures extending through the first active region and the second active region; a plurality of first active doping regions and a plurality of first inactive doping regions in the first active region; the first active doping regions and the second inactive doping regions are arranged at intervals, and the second active doping regions and the first inactive doping regions are arranged at intervals; a plurality of third doped regions located within the first active region and the second active region; a first conductive structure located on each first active doping region; a plurality of first bit lines; a second conductive structure located on each second active doping region; a number of second bit lines. By the semiconductor structure, the integration level of the memory can be high, and the difficulty of the manufacturing process is small.

Description

Semiconductor structure and forming method thereof

Technical Field

The present invention relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.

Background

With the rapid development of technology, semiconductor memories are widely used in electronic devices. Dynamic Random Access Memory (DRAM), which is a volatile memory, is the most commonly utilized solution for applications that store large amounts of data.

Generally, a dram is composed of a plurality of memory cells, each of which is mainly composed of a transistor and a capacitor operated by the transistor, and each of the memory cells is electrically connected to each other through a word line and a bit line.

However, in the conventional memory cell, on one hand, since the channel direction of the transistor is along the substrate surface, the occupied area of the channel and the source/drain on both sides of the channel in the transistor on the substrate surface is very large, resulting in low integration of the memory. On the other hand, because the source/drain of the two sides of the channel of the transistor is exposed on the same surface of the substrate, the bit line conductive structure connecting the bit line and the source/drain of one side of the channel and the capacitor conductive structure connecting the capacitor and the source/drain of the other side of the channel are both on the same side of the substrate, so that the distance between the bit line conductive structure and the capacitor conductive structure is small, and the bit line conductive structure and the capacitor conductive structure need to be mutually avoided, thereby the window of the manufacturing process for forming the memory is small, and the manufacturing process difficulty is large.

Disclosure of Invention

The invention provides a semiconductor structure and a forming method thereof, which aims to ensure that the integration level of a memory is high and the manufacturing process difficulty is low.

To solve the above technical problem, an aspect of the present invention provides a semiconductor structure, including: the first substrate comprises a first face and a second face which are opposite, the first substrate comprises a plurality of first active regions and a plurality of second active regions which are separated from each other, the first active regions and the second active regions are arranged at intervals along a first direction, the first active regions and the second active regions are respectively parallel to a second direction, and the first direction and the second direction are perpendicular to each other; the word line grid structures are arranged in the first substrate and penetrate through the first active regions and the second active regions along the first direction; the first active area is provided with a plurality of first active doping areas and a plurality of first inactive doping areas, the first active doping areas and the first inactive doping areas are exposed on the first surface, the first active doping areas and the first inactive doping areas are arranged at intervals along the second direction, and the two sides of each word line gate structure are respectively provided with the first active doping areas and the first inactive doping areas; the first surface exposes the second effective doping regions and the second ineffective doping regions, the second effective doping regions and the second ineffective doping regions are arranged at intervals along a second direction, the second effective doping regions and the second ineffective doping regions are respectively arranged on two sides of each word line gate structure, the first effective doping regions and the second ineffective doping regions are arranged at intervals along a first direction, and the second effective doping regions and the first ineffective doping regions are arranged at intervals along the first direction; a plurality of third doped regions separated from each other within the first active region and the second active region, the second face exposing the third doped regions; a first conductive structure located on each first active doping region; a plurality of first bit lines, each of which is connected to the first conductive structures on 1 of the first active regions; a second conductive structure located on each second active doping region; and a plurality of second bit lines, each of which is connected with the second conductive structures on the 1 second active regions.

Optionally, the method further includes: and a plurality of capacitors on the second surface, each capacitor electrically connected to 1 third doped region.

Optionally, the method further includes: and each capacitor conductive structure is respectively connected with 1 capacitor and 1 third doped region.

Optionally, the method further includes: the projection of the capacitance on the second face at least partially coincides with the third doped region.

Optionally, the method further includes: and the second substrate is bonded with the first substrate, and the surface of the second substrate faces the first surface.

Optionally, a logic circuit is disposed in the second substrate, and the logic circuit is electrically connected to the word line gate structure, the first bit line, and the second bit line, respectively.

Optionally, the method further includes: a first isolation structure between adjacent first and second active regions, the first isolation structure separating the adjacent first and second active regions.

Optionally, the method further includes: the second isolation structures are positioned in the first active region and the second active region, the surface of each second isolation structure is exposed on the second face, the second isolation structures positioned in the first active region penetrate through the first active region along the first direction, the second isolation structures positioned in the second active region penetrate through the second active region along the first direction, in addition, the second isolation structures are arranged between the adjacent word line gate structures in the second direction, and in the normal direction of the second face, the thickness of each second isolation structure is larger than the depth of each third doped region.

Optionally, the word line gate structure includes: the gate structure comprises a gate and a gate dielectric layer positioned between the gate and a first substrate.

Optionally, the gate is a composite gate, the gate includes a first gate and a second gate located on a top surface of the first gate, and the first gate and the second gate are made of different materials.

Optionally, a top surface of the gate is lower than the first surface, and the gate structure further includes: and the cover dielectric layer is positioned on the top surface of the grid and is flush with or higher than the first surface.

Optionally, the word line gate structure further includes: the word line layer is positioned on the top surface of the grid electrode, the surface of the word line layer is lower than the top surface of the first conductive structure, the surface of the word line layer is lower than the top surface of the second conductive structure, and the word line layer is respectively insulated from the first conductive structure and the second conductive structure.

Correspondingly, the technical scheme of the invention also provides a method for forming the semiconductor structure, which comprises the following steps: providing a first substrate, wherein the first substrate comprises a first face and a second face which are opposite to each other, the first substrate comprises a plurality of first active regions and a plurality of second active regions which are separated from each other, the first active regions and the second active regions are arranged at intervals along a first direction, the first active regions and the second active regions are respectively parallel to a second direction, and the first direction and the second direction are perpendicular to each other; forming a plurality of word line grid structures in the first substrate, wherein the word line grid structures are arranged along a second direction, and the word line grid structures penetrate through a plurality of first active regions and a plurality of second active regions along a first direction; forming a plurality of first effective doping regions and a plurality of first ineffective doping regions in the first active region, wherein the first effective doping regions and the first ineffective doping regions are exposed on the first surface, the first effective doping regions and the first ineffective doping regions are arranged at intervals along a second direction, and the first effective doping regions and the first ineffective doping regions are respectively arranged on two sides of each word line gate structure; forming a plurality of second effective doping regions and a plurality of second ineffective doping regions in the second active region, wherein the second effective doping regions and the second ineffective doping regions are exposed on the first surface, the second effective doping regions and the second ineffective doping regions are arranged at intervals along a second direction, the second effective doping regions and the second ineffective doping regions are respectively arranged on two sides of each word line gate structure, the first effective doping regions and the second ineffective doping regions are arranged at intervals along a first direction, and the second effective doping regions and the first ineffective doping regions are arranged at intervals along the first direction; forming a first conductive structure on each first effective doping area; forming a second conductive structure on each second effective doping area; forming a plurality of first bit lines and a plurality of second bit lines, wherein each first bit line is connected with the first conductive structures on 1 first active region, and each second bit line is connected with the second conductive structures on 1 second active region; after the first bit line and the second bit line are formed, a plurality of third doped regions which are separated from each other are formed in the first active region and the second active region, and the second surface exposes the third doped regions.

Optionally, the method further includes: a first isolation structure is formed between adjacent first and second active regions, the first isolation structure separating the adjacent first and second active regions.

Optionally, the method further includes: providing a second substrate; and bonding the second substrate with the first substrate, wherein the surface of the second substrate faces to the first surface.

Optionally, the method further includes: after the first substrate and the second substrate are bonded, forming the third doped region in the first active region and the second active region; after the third doped regions are formed, a plurality of capacitors are formed on the second face, each capacitor being electrically connected to 1 third doped region.

Optionally, the method further includes: after the first substrate and the second substrate are bonded, a plurality of second isolation structures are formed in the first active region and the second active region, the surfaces of the second isolation structures are exposed by the second surface, the second isolation structures in the first active region penetrate through the first active region along the first direction, the second isolation structures in the second active region penetrate through the second active region along the first direction, in addition, the second isolation structures are arranged between the adjacent word line gate structures in the second direction, and in the normal direction of the second surface, the thickness of the second isolation structures is larger than the depth of the third doping region.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:

in the semiconductor structure provided by the technical scheme of the invention, the first conductive structures are positioned on the first effective doped regions, each first bit line is connected with the first conductive structures on 1 first active region, the second conductive structures are positioned on the second effective doped regions, and each second bit line is connected with the second conductive structures on 1 second active region, so that the effectiveness of the first effective doped regions and the second effective doped regions and the effectiveness of the first ineffective doped regions and the second ineffective doped regions are realized simultaneously. Moreover, because the first surface exposes the first effective doping area and the second effective doping area, and the second surface exposes the third doping area, a channel along the normal direction of the first surface can be formed between 1 third doping area and 1 first effective doping area, and a channel along the normal direction of the first surface can be formed between 1 third doping area and 1 second effective doping area, so that the formed channel occupies the space in the normal direction of the first surface, and the occupied areas of the doping areas for forming the channel on the surface of the first substrate (the first surface and the second surface) coincide, so that the integration degree of the semiconductor structure is high. On the basis, the third doping area, the first effective doping area and the second effective doping area are exposed on the surface opposite to the first substrate, the first effective doping area and the first ineffective doping area, and the second effective doping area and the second ineffective doping area are arranged at intervals along the second direction respectively, the first effective doping area and the first ineffective doping area, the second effective doping area and the second ineffective doping area are arranged on two sides of each word line gate structure respectively, and the first effective doping area and the second ineffective doping area, the second effective doping area and the first ineffective doping area are arranged at intervals along the first direction. Therefore, on one hand, the mutual interference among the electric device electrically connected to the third doped region, the first bit line and the second bit line in the circuit arrangement is small, so that the circuit arrangement of the semiconductor structure can be simpler, and the integration level of the semiconductor structure is higher; on the other hand, when the circuit arrangement of the semiconductor structure is simple, the distances between the adjacent first conductive structures, between the adjacent second conductive structures and between the adjacent first conductive structures and the adjacent second conductive structures are larger, so that the process window of the manufacturing process for forming the first conductive structures and the second conductive structures is larger, and the difficulty of the manufacturing process of the memory is small.

Drawings

Fig. 1 to 21 are schematic structural diagrams of steps in a method for forming a semiconductor structure according to an embodiment of the invention.

Detailed Description

As described in the background art, in the conventional memory cell, on the one hand, since the channel direction of the transistor is along the substrate surface, the occupied area of the channel in the transistor and the source/drain on both sides of the channel on the substrate surface is very large, resulting in low integration of the memory. On the other hand, because the source/drain of the two sides of the channel of the transistor is exposed on the same surface of the substrate, the bit line conductive structure connecting the bit line and the source/drain of one side of the channel and the capacitor conductive structure connecting the capacitor and the source/drain of the other side of the channel are both on the same side of the substrate, so that the distance between the bit line conductive structure and the capacitor conductive structure is small, and the bit line conductive structure and the capacitor conductive structure need to be mutually avoided, thereby the window of the manufacturing process for forming the memory is small, and the manufacturing process difficulty is large.

In order to solve the above technical problems, a technical solution of the present invention provides a semiconductor structure and a method for forming the same, wherein on one hand, a channel can be formed in a normal direction of a first surface, and on the other hand, a first effective doping region and a second ineffective doping region, a second effective doping region and a first ineffective doping region are respectively arranged at intervals along a first direction, and a first conductive structure is located on each first effective doping region and a second conductive structure is located on each second effective doping region, so that the semiconductor structure can enable a memory to have a high integration level and a small difficulty in a manufacturing process.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

Referring to fig. 1 and fig. 2, fig. 1 is a schematic top view structure diagram in the process of forming a semiconductor structure according to an embodiment of the present invention, fig. 2 is a schematic cross-sectional structure diagram along a direction a1-a2 in fig. 1, a first substrate 100 is provided, the first substrate 100 includes a first surface 101 and a second surface 102 opposite to each other, the first substrate 100 includes a plurality of first active regions B and a plurality of second active regions T that are separated from each other, the plurality of first active regions B and the plurality of second active regions T are arranged at intervals along a first direction X, the first active regions B and the second active regions T are respectively parallel to a second direction Y, and the first direction X and the second direction Y are perpendicular to each other.

The material of the first substrate 100 is a semiconductor material. In this embodiment, the material of the first substrate 100 is silicon. In other embodiments, the material of the first substrate comprises silicon carbide, silicon germanium, a multi-component semiconductor material of group iii-v elements, silicon-on-insulator (SOI), or germanium-on-insulator. The multielement semiconductor material formed by III-V group elements comprises InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

Next, a first isolation structure is formed between the adjacent first and second active regions B and T, the first isolation structure separating the adjacent first and second active regions B and T. Please refer to fig. 3 to 4 for specific steps of forming the first isolation structure.

Referring to fig. 3, the first substrate 100 is etched in a direction consistent with the view direction of fig. 2, a first isolation opening 103 is formed between the adjacent first active region B and the second active region T, and the first isolation opening 103 is exposed by the first surface 101.

The first isolation opening 103 provides space for a material filling the first isolation structure.

In the present embodiment, the method of forming the first isolation opening 103 includes: forming a first isolation opening mask layer (not shown) on the first surface 101, wherein the first isolation opening mask layer exposes the first surface 101 between the adjacent first active region B and the second active region T; and etching the first substrate 100 by taking the first isolation opening mask layer as a mask to form the first isolation opening 103.

In this embodiment, the process of etching the first substrate 100 includes at least one of a dry etching process and a wet etching process with the first isolation opening mask layer as a mask.

Referring to fig. 4, fig. 4 is the same as the view direction of fig. 3, a first isolation structure 110 is formed in the first isolation opening 103, and the first isolation structure 110 separates adjacent first active region B and second active region T.

In the present embodiment, in a direction perpendicular to the first surface 101, the height of the first isolation structure 110 is smaller than the distance between the first surface 101 and the second surface 102.

In this embodiment, the method for forming the first isolation structure 110 in the first isolation opening 103 includes: forming a first layer of isolation structure material (not shown) within the first face 101 and first isolation opening 103; planarizing the first isolation structure material layer until the first face 101 is exposed.

In the present embodiment, the process of forming the first isolation structure material layer includes at least one of a chemical vapor deposition process, a flowable chemical vapor deposition process, a physical vapor deposition process, and a spin coating process.

In this embodiment, the process of planarizing the first isolation structure material layer includes a chemical mechanical polishing process.

Next, a plurality of word line gate structures are formed in the first substrate 100, the plurality of word line gate structures are arranged along the second direction Y, and the plurality of word line gate structures penetrate the plurality of first active regions B and the plurality of second active regions T along the first direction X. Please refer to fig. 5 to 9 for specific steps of forming the word line gate structure.

Referring to fig. 5 to 7, fig. 5 is a schematic top view structure diagram in the process of forming a semiconductor structure according to an embodiment of the invention, fig. 6 is a schematic cross-sectional structure diagram along the direction C1-C2 in fig. 5, fig. 7 is a schematic cross-sectional structure diagram along the direction D1-D2 in fig. 5, the first surface 101 is etched, a plurality of word line gate openings 104 are formed in the first substrate 100 and the first isolation structure 110, the plurality of word line gate openings 104 are arranged along the second direction Y, and the plurality of word line gate openings 104 penetrate through the plurality of first active regions B and the plurality of second active regions T along the first direction X.

The word line gate openings 104 provide space for forming word line gate structures.

In the present embodiment, in a direction perpendicular to the first surface 101, the depth of the word line gate opening 104 is smaller than the distance between the top surface of the first isolation structure 110 and the bottom surface of the first isolation structure 110.

In this embodiment, the method for etching the first surface 101 to form the word line gate opening 104 includes: forming a word line gate opening mask layer (not shown) on the first surface 101 and the first isolation structure 110, wherein the word line gate opening mask layer exposes a part of the first surface 101 and a part of the top surface of the first isolation structure 110; and etching the first substrate 100 and the first isolation structure 110 from the first surface 101 to the second surface 102 by using the word line gate opening mask layer as a mask to form the word line gate opening 104.

Referring to fig. 8 and 9, fig. 8 is a schematic top view illustrating a semiconductor structure forming method according to an embodiment of the invention, fig. 9 is a schematic cross-sectional view taken along a direction D1-D2 in fig. 8, and fig. 8 and 7 are views in a same direction, in which word line gate structures 120 are formed in each of the word line gate openings 104 to form a plurality of word line gate structures 120 in the first substrate 100. The plurality of word line gate structures 120 are arranged along the second direction Y, and the plurality of word line gate structures 120 penetrate the plurality of first active regions B and the plurality of second active regions T along the first direction Y.

Since the embedded word line gate structure 120 is formed in the first substrate 100, on one hand, a vertical transistor perpendicular to the surface direction of the first substrate 100 can be formed, so that the occupied areas of the word line and the gate structure in the surface direction of the first substrate 100 are small, and the bit line and the capacitor can be respectively located on two sides (on the first surface 101 and the second surface 102) of the first substrate 100, thereby facilitating simplification of the circuit layout of the semiconductor structure and improvement of the integration level of the semiconductor structure. On the other hand, the word line grid structure 120 can simultaneously function as a word line and a grid structure, thereby being beneficial to improving the integration degree of the semiconductor structure.

In this embodiment, the word line gate structure 120 includes: a gate electrode 121, and a gate dielectric layer 122 between the gate electrode 121 and the first substrate 100.

In this embodiment, the top surface of the gate electrode 121 is lower than the first surface 101. Also, the word line gate structure 120 further includes: and a capping dielectric layer 123 on the top surface of the gate 121.

Since the capping dielectric layer 123 is located on the top surface of the gate electrode 121, and therefore, the gate electrode 121 can be insulated from a subsequently formed bit line by the capping dielectric layer 123. Moreover, since the top surface of the gate 121 is lower than the first surface 101, at least a portion of the capping dielectric layer 123 can be formed in the word line gate opening 104, so that the word line gate opening 104 is effectively utilized as a portion of the occupied space of the capping dielectric layer 123, the influence of the position of the capping dielectric layer 123 on other semiconductor structures is reduced, and the circuit layout of the semiconductor structure is simplified.

Note that, for convenience of understanding, fig. 8 is a schematic top view of the capping dielectric layer 123.

In this embodiment, the capping dielectric layer 123 is flush with the first surface 101. Therefore, the occupied space of the word line gate opening 104 as the cover dielectric layer 123 is further effectively utilized, so that the circuit layout of the semiconductor structure can be better simplified, and meanwhile, the integration level of the semiconductor structure is improved.

In other embodiments, the cap dielectric layer is higher than the first side.

In other embodiments, the word line gate structure further comprises: and the word line layer is positioned on the top surface of the grid electrode, the surface of the word line layer is lower than the bottom surface of a subsequently formed bit line, and the word line layer is insulated from the bit line.

In this embodiment, the gate 121 is a single layer. The material of the gate electrode 121 is, for example, polysilicon or a metal material.

In other embodiments, the gate is a composite gate, the gate includes a first gate and a second gate on a top surface of the first gate, and the first gate and the second gate are made of different materials. The material of the first gate electrode comprises a metal material, and the second gate electrode structure comprises polysilicon. Because the grid comprises the first grid and the second grid which are made of different materials, the threshold voltage of the word line grid structure can be adjusted by adjusting the volume ratio of the first grid and the second grid so as to meet different device design requirements.

Note that the gate electrode 121 in the word line gate structure 120 may be extended in the first direction X (not shown) to extract a word line in a back-end process, so as to achieve electrical connection with other circuits.

Next, referring to fig. 10 to 12, fig. 10 is a schematic top view illustrating a method for forming a semiconductor structure according to an embodiment of the present invention, fig. 11 is a schematic cross-sectional structure taken along a direction D1-D2 in fig. 10, fig. 12 is a schematic cross-sectional structure taken along a direction E1-E2 in fig. 10, and a plurality of first active doping regions R1 and a plurality of first inactive doping regions U1 are formed in the first active region B; a plurality of second active doping regions R2 and a plurality of second inactive doping regions U2 are formed within the second active region T.

The first surface 101 exposes the first effective doping regions R1 and the first ineffective doping regions U1, the first effective doping regions R1 and the first ineffective doping regions U1 are arranged at intervals along the second direction Y, and two sides of each word line gate structure 120 are respectively provided with a first effective doping region R1 and a first ineffective doping region U1.

The first surface 101 exposes the second effective doping regions R2 and the second ineffective doping regions U2, the second effective doping regions R2 and the second ineffective doping regions U2 are arranged at intervals along the second direction Y, two sides of each word line gate structure 120 are respectively provided with the second effective doping regions R2 and the second ineffective doping regions U2, the first effective doping regions R1 and the second ineffective doping regions U2 are arranged at intervals along the first direction X, and the second effective doping regions R2 and the first ineffective doping regions U1 are arranged at intervals along the first direction X.

In the embodiment, the method for forming the first active doping region R1, the first inactive doping region U1, the second active doping region R2 and the second inactive doping region U2 includes: after the word line gate structure 120 is formed, an ion implantation process is performed on the first surface 101 to implant first ions in the first active region B and the second active region T of the first substrate 100, so as to form the first effective doping region R1, the first inactive doping region U1, the second effective doping region R2, and the second inactive doping region U2. The first ions include N-type ions or P-type ions.

Since the first effective doping region R1, the first ineffective doping region U1, the second effective doping region R2 and the second ineffective doping region U2 are simultaneously formed through one ion implantation process, i.e., the ion implantation process performed on the first face 101, the efficiency of forming the semiconductor structure is improved.

It should be noted that, in the present embodiment, since the first conductive structure connected to the first bit line is subsequently formed on each of the first effective doping regions R1, and the first ineffective doping region U1 is insulated from the first bit line, the first effective doping region R1 and the first ineffective doping region U1 are distinguished. Since the second conductive structure connected to the second bit line is subsequently formed on each of the second effective doping regions R2 and the second ineffective doping region U2 is insulated from the second bit line, the second effective doping region R2 and the second ineffective doping region U2 are distinguished. Thus, the first and second effective doping regions R1 and R2 are effective, and the first and second ineffective doping regions U1 and U2 are ineffective.

In other embodiments, a first ion implantation process is performed on the first face to form a first active doping region and a first inactive doping region. And performing a second ion implantation process on the first surface to form a second effective doping area and a second ineffective doping area. By performing the first ion implantation process and the second ion implantation process, respectively, a first effective doped region and a second effective doped region having different doping concentrations or doping ions can be formed. Thus, diverse electrical property requirements are satisfied.

Referring to fig. 13, in the same view direction as fig. 10, a first conductive structure 141 is formed on each first effective doping region R1, and a second conductive structure 142 is formed on each second effective doping region R2 in fig. 13.

Through the first conductive structure 141, on the one hand, each of the subsequently formed first bit lines is electrically connected to the first active doping regions R1 on the 1 first active regions B. On the other hand, by raising the first bit line, the distance between the first bit line and the word line gate structure 120 is better increased, which is beneficial to improving the insulation reliability between the first bit line and the word line gate structure 120.

Through the second conductive structures 142, on the one hand, each of the subsequently formed second bit lines is electrically connected to the second effective doping regions R2 on the 1 second active regions T. On the other hand, by raising the second bit line, the distance between the second bit line and the word line gate structure 120 is better increased, which is beneficial to improving the insulation reliability between the second bit line and the word line gate structure 120.

In this embodiment, the method of forming the first and second

conductive structures

141 and 142 includes: depositing a conductive structure material layer (not shown) on the surfaces of the word line grid structure 120, the first isolation structure 110, and the first active doping region R1, the second active doping region R2, the first inactive doping region U1, and the second inactive doping region U2; forming a plurality of conductive mask structures on the surfaces of the conductive structure material layers on the first effective doping region R1 and the second effective doping region R2; and etching the conductive structure material layer by using the conductive mask structure as a mask until the first isolation structure 110, the surface of the word line gate structure 120, the surface of the first ineffective doping region U1 and the surface of the second ineffective doping region U2 are exposed, so as to form the first conductive structure 141 and the second conductive structure 142.

In this embodiment, the material of the first conductive structure 141 and the second conductive structure 142 includes a metal material, such as copper or tungsten.

Referring to fig. 14 and 15, fig. 14 is a schematic top view illustrating a semiconductor structure forming method according to an embodiment of the invention, fig. 15 is a schematic cross-sectional view taken along the direction D1-D2 in fig. 14, and a plurality of first bit lines 143 and a plurality of second bit lines 144 are formed, each first bit line 143 is connected to the first conductive structures 141 in 1 first active region B, and each second bit line 144 is connected to the second conductive structures 142 in 1 second active region T.

In the present embodiment, before the first bit line 143 and the second bit line 144 are formed, an initial third isolation dielectric layer (not shown) is formed on the exposed surfaces of the first effective doping region R1, the second effective doping region R2, the first ineffective doping region U1, the second ineffective doping region U2, the word line gate structure 120, the first conductive structure 141, the second conductive structure 142, and the first isolation structure 110, and the initial third isolation dielectric layer is higher than the top surfaces of the first conductive structure 141 and the second conductive structure 142.

In this embodiment, the process of forming the initial third isolation dielectric layer includes a deposition process or a spin-on process, and the deposition process is, for example, a chemical vapor deposition process, a physical vapor deposition process, or a flowable vapor deposition process.

In this embodiment, the method for forming the first bit line 143 and the second bit line 144 includes: forming a bit line mask layer (not shown) on the surface of the initial third isolation dielectric layer, wherein the bit line mask layer exposes the first active region B and the second active region T; etching the initial third isolation dielectric layer by using the bit line mask layer as a mask until the top surfaces of the first conductive structures 141 and the second conductive structures 142 are respectively exposed, so as to form a third isolation dielectric layer 150, and a plurality of first bit line openings (not shown) and second bit line openings (not shown) in the third isolation dielectric layer 150, wherein each first bit line opening exposes the top surfaces of the first conductive structures 141 in 1 first active region B, and each second bit line opening exposes the top surfaces of the second conductive structures 142 in 1 second active region T; forming a bit line material layer (not shown) in the first bit line opening, the second bit line opening and the surface of the third isolation dielectric layer 150; and planarizing the bit line material layer until the surface of the third isolation dielectric layer 150 is exposed, forming the first bit line 143 in the first bit line opening, and forming the second bit line 144 in the second bit line opening.

In the present embodiment, the materials of the first bit line 143 and the second bit line 144 respectively include a metal material, such as copper or tungsten.

In this embodiment, after the first bit lines 143 and the second bit lines 144 are formed, a plurality of first interconnection layers (not shown) electrically connected to the first bit lines 143, a plurality of second interconnection layers (not shown) electrically connected to the second bit lines 144, a plurality of third interconnection layers electrically connected to the word line gate structures 120, and a first interlayer dielectric layer (not shown) surrounding the first interconnection layers, the second interconnection layers, and the third interconnection layers are formed, and the surface of the first interlayer dielectric layer exposes the top surfaces of the first interconnection layers, the second interconnection layers, and the third interconnection layers. The first interconnect layer, the second interconnect layer and the third interconnect layer are used for being respectively connected with a circuit in a second substrate provided later, so that the first bit line 143, the second bit line 144 and the word line gate structure 120 are respectively electrically connected with the circuit in the second substrate.

In other embodiments, the first interconnect layer, the second interconnect layer, the third interconnect layer, and the first interlevel dielectric layer are not formed.

Referring to fig. 16, a second substrate 200 is provided.

In this embodiment, the second substrate 200 has a logic circuit (not shown) therein.

Voltages can be applied to the word line gate structure 120, the first bit line 143, and the second bit line 144, respectively, by the logic circuit to control writing and reading of the memory.

In the present embodiment, the second substrate 200 has a fourth interconnect layer (not shown) therein, which is electrically connected to the logic circuit, and the fourth interconnect layer is exposed on the surface of the second substrate 200.

In the present embodiment, the logic circuit includes 1 or more of a row address decoder, a data input buffer, a data output buffer, a sense amplifier, a column address decoder, and a driving circuit.

In other embodiments, the second substrate does not have logic circuitry therein.

With continued reference to fig. 16, the second substrate 200 is bonded to the first substrate 100, the surface of the second substrate 200 faces the first surface 101, and the logic circuits are electrically connected to the word line grid structures 120 and the bit lines 140, respectively.

In this embodiment, the first interconnect layer, the second interconnect layer, and the third interconnect layer are respectively connected to a fourth interconnect layer, so that logic circuits are electrically connected to the word line grid structure 120, the first bit line 143, and the second bit line 144, respectively.

In this embodiment, after the first substrate 100 and the second substrate 200 are bonded, the first substrate 100 is thinned from the second surface 102 until the bottom surface of the first isolation structure 110 is exposed.

In the present embodiment, the process of thinning the first substrate 100 includes a chemical mechanical polishing process.

Referring to fig. 17 and 18, fig. 17 is a schematic top view structure along a direction M in fig. 18, fig. 18 is a schematic cross-sectional structure along a direction D1-D2 in fig. 17, after the first substrate 100 and the second substrate 200 are bonded, a plurality of second isolation structures 160 are formed in the first active region T and the second active region B, the second surface 102 exposes a surface of the second isolation structures 160, the second isolation structures 160 in the first active region B penetrate the first active region B along a first direction X, the second isolation structures 160 in the second active region T penetrate the second active region T along the first direction X, and the second isolation structures 160 are between adjacent word line gate structures 120 in the second direction Y.

The second isolation structure 160 is used to space adjacent third doped regions among subsequently formed third doped regions, so as to insulate the adjacent third doped regions.

The surface of the second isolation structure 160 and the first effective doped region U1, the first ineffective doped region R1, the second effective doped region U2, and the second ineffective doped region R2 all have a distance therebetween, that is, in the normal direction of the second surface 102, the thickness H1 of the second isolation structure 160 is smaller than the distance between the second surface 102 and the first effective doped region U1, and the distance between the second surface 102 and the second effective doped region U2, respectively, so as to prevent the second isolation structure 160 from damaging the first effective doped region U1 and the second effective doped region U2.

In the present embodiment, the method of forming the second isolation structure 160 includes: forming a second isolation structure mask layer (not shown) on the second side 102, the second isolation structure mask layer exposing the second side 102 between the word line grid structures 120; etching the first substrate 100 by using the second isolation structure mask layer as a mask, and forming a second isolation opening (not shown) in the first substrate 100; the second isolation opening is filled with a material of a second isolation structure 160 to form the second isolation structure 160.

The process of filling the material of the second isolation structure 160 in the second isolation opening includes a deposition process or a spin-on process, for example, a chemical vapor deposition process or a physical vapor deposition process.

Referring to fig. 19 and 20, fig. 19 is a schematic top view along a direction M in fig. 20, fig. 20 is a schematic cross-sectional view along a direction D1-D2 in fig. 19, after the first bit line 143 and the second bit line 144 are formed, a plurality of third doped regions 170 separated from each other are formed in the first active region B and the second active region T, and the second surface 102 exposes the third doped regions 170.

Specifically, in the present embodiment, after the first substrate 100 and the second substrate 200 are bonded, the third doped region 170 is formed in the first active region B and the second active region T.

In the present embodiment, in the normal direction of the second surface 102, the thickness H1 of the second isolation structure 160 is greater than the depth H2 of the third doped region 170. To space adjacent third doped regions 170 by the second isolation structures 160.

In this embodiment, the method for forming the third doped region 170 includes: an ion implantation process is performed on the second surface 102 to implant first ions into the first active region B and the second active region T of the first substrate 100, so as to form the third doped region 170.

In the present embodiment, the second isolation structure 160 is formed prior to the third doped region 170.

In other embodiments, the third doped region is formed prior to the second isolation structure.

Referring to fig. 21, the view directions of fig. 21 and fig. 20 are the same, after the third doped region 170 is formed, a plurality of capacitors 180 are formed on the second surface 102, and each capacitor 180 is electrically connected to 1 third doped region 170.

In this embodiment, the capacitor 180 includes: a first electrode layer (not shown), a second electrode layer (not shown), and a dielectric layer (not shown) between the first electrode layer and the second electrode layer.

The shape of the dielectric layer includes: planar or "U" shaped.

When the shape of the dielectric layer is planar, the surface of the first electrode layer is flat, and the surface of the second electrode layer is flat.

When the dielectric layer is in a U shape, the surface of the first electrode layer is an uneven surface, and the surface of the second electrode layer is an uneven surface; or the surface of the first electrode layer is flat, and the surface of the second electrode layer is flat.

The material of the first electrode layer includes: a metal or metal nitride; the material of the second electrode layer includes: a metal or metal nitride; the metal includes: combinations of one or more of copper, aluminum, tungsten, cobalt, nickel, and tantalum; the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride. In this embodiment, before the capacitor 180 is formed, a plurality of capacitor conductive structures 181 are formed on the third doped region 170, and each capacitor conductive structure 181 is respectively connected to 1 capacitor 180 and 1 third doped region 170.

Due to the formation of the capacitor conductive structure 181, the risk of disconnection between the capacitor 180 and the third doped region 170 is reduced, the process window for forming the capacitor 180 is increased, and the improvement of the flexibility of the arrangement mode of the capacitor 180 is facilitated.

Specifically, in the present embodiment, the projection of the capacitor 180 on the second surface 102 coincides with the projection of the capacitor conductive structure 181 on the second surface 102. The capacitor 180 may be offset in any direction relative to the capacitor conductive structure 181.

The material of the capacitive conductive structure 181 includes: a metal or metal nitride; the metal includes: combinations of one or more of copper, aluminum, tungsten, cobalt, nickel, and tantalum; the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride. In other embodiments, the capacitor conductive structure is not formed, and the capacitor is directly connected with the third doped region, so that the forming steps of the semiconductor structure are simplified, and the efficiency is improved. In this embodiment, a projection of the capacitance onto the second face at least partially coincides with the third doped region.

In this embodiment, the method for forming the capacitive conductive structure 181 includes: forming a lower second interlayer dielectric layer (not shown) on the second surface 102; forming a plurality of capacitor conductive structure openings (not shown) in the lower second interlayer dielectric layer, wherein the capacitor conductive structure openings expose a portion of the surface of the third doped region 170; and filling the material of the capacitor conductive structure 181 in the opening of the capacitor conductive structure.

In this embodiment, the method for forming the capacitor 180 includes: forming an upper second interlayer dielectric layer (not shown) on the surfaces of the lower second interlayer dielectric layer and the capacitor conductive structure 181; forming a plurality of capacitor openings in the upper second interlayer dielectric layer, wherein the capacitor openings expose the top surface of the capacitor conductive structure 181; the capacitor opening is filled with the material of the capacitor 180.

The upper second interlayer dielectric layer and the lower second interlayer dielectric layer form a second interlayer dielectric layer 190 surrounding the capacitor conductive structure 181 and the capacitor 180.

Accordingly, an embodiment of the present invention further provides a semiconductor structure formed by the above method, with reference to fig. 21, including: a first substrate 100, the first substrate 100 including a first side 101 and a second side 102 opposite to each other, the first substrate 100 including a plurality of first active regions B and a plurality of second active regions T that are separated from each other, the plurality of first active regions B and the plurality of second active regions T being arranged at intervals along a first direction X, the first active regions B and the second active regions T being parallel to a second direction Y, respectively, the first direction X and the second direction Y being perpendicular to each other; a plurality of word line gate structures 120 located in the first substrate 100, the plurality of word line gate structures 120 being arranged along a second direction Y, and the plurality of word line gate structures 120 penetrating through the plurality of first active regions B and the plurality of second active regions T along a first direction X; a plurality of first effective doping regions R1 and a plurality of first ineffective doping regions U1 located in the first active region B, the first face 101 exposes the first effective doping regions R1 and the first ineffective doping regions U1, the first effective doping regions R1 and the first ineffective doping regions U1 are arranged at intervals along the second direction Y, and two sides of each word line gate structure 120 are respectively provided with a first effective doping region R1 and a first ineffective doping region U1; a plurality of second active doping regions R2 and a plurality of second inactive doping regions U2 (as shown in fig. 13) located in the second active region T, wherein the first surface 101 exposes the second active doping regions R2 and the second inactive doping regions U2, the second active doping regions R2 and the second inactive doping regions U2 are arranged at intervals along the second direction Y, two sides of each word line gate structure 120 are respectively provided with second active doping regions R2 and second inactive doping regions U2, the first active doping regions R1 and the second inactive doping regions U2 are arranged at intervals along the first direction X, and the second active doping regions R2 and the first inactive doping regions U1 are arranged at intervals along the first direction X; a plurality of third doped regions 170 located within the first active region B and the second active region T, the second face 102 exposing the third doped regions 170; a first conductive structure 141 (shown in fig. 13) located on each first effective doping region R1; a plurality of first bit lines 143, each of the first bit lines 143 being connected to the first conductive structures 141 on 1 of the first active regions B; second conductive structures 142 (shown in fig. 13) located on each second effective doping region R2; a plurality of second bit lines 144, each second bit line 144 connected to the second conductive structure 144 on 1 second active region T.

Since the first conductive structures 141 are located on the first active doping region R1, each first bit line 143 is connected to the first conductive structures 141 on 1 first active region B, the second conductive structure 142 is located on the second active doping region R2, and each second bit line 144 is connected to the second conductive structures 144 on 1 second active region T, the first active doping region R1 and the second active doping region R2 are enabled, and the first inactive doping region U1 and the second inactive doping region U2 are disabled. Furthermore, since the first surface 101 exposes the first and second effective doping regions R1 and R2, and the second surface 102 exposes the third doping region 170, a channel along the normal direction of the first surface 101 can be formed between 1 third doping region 170 and 1 first effective doping region R1, and a channel along the normal direction of the first surface 101 can be formed between 1 third doping region 170 and 1 second effective doping region R2. Specifically, each of the third doped regions 170 is independent from the first active doped region R1, the second active doped region R2, the first inactive doped region U1 and the second inactive doped region U2, and a vertical channel is formed between the third doped region 170 and the first active doped region R1, and between the third doped region 170 and the second active doped region R2. Thus, the formed channel occupies a space in the normal direction of the first face 101, and the occupation areas of the doped regions for forming the channel on the surface (the first face 101 and the second face 102) of the first substrate 100 coincide, so that the integration of the semiconductor structure is high.

On this basis, since the third doped region 170 and the first and second effective doped regions R1 and R2 are exposed on the opposite surfaces (the first and second faces 101 and 102) of the first substrate 100, and the first and second effective doped regions R1 and U1, and the second and second effective doped regions R2 and U2 are respectively arranged at intervals along the second direction Y, both sides of each word line gate structure 120 respectively have the first and second effective doped regions R1 and U1, and the second and second effective doped regions R2 and U2, the first and second effective doped regions R1 and U2, and the second and first effective doped regions R2 and U1 are arranged at intervals along the first direction X. Therefore, on the one hand, the mutual interference between the electrical device (capacitor 180) electrically connected to the third doped region 170 and the first bit line 143 and the second bit line 144 in the circuit arrangement is small, so that the circuit arrangement of the semiconductor structure can be simpler and the integration of the semiconductor structure is higher; on the other hand, while the circuit arrangement of the semiconductor structure is simple, the distances between the adjacent first conductive structures 141, between the adjacent second conductive structures 142, and between the adjacent first conductive structures 141 and second conductive structures 142 are all large, so that the process window of the manufacturing process for forming the first conductive structures 141 and the second conductive structures 142 is large, and the difficulty of the manufacturing process of the memory is small.

In this embodiment, the capping dielectric layer 123 is flush with the first surface 101.

In other embodiments, the cap dielectric layer is higher than the first side.

In other embodiments, the gate is a composite gate, the gate includes a first gate and a second gate on a top surface of the first gate, and the first gate and the second gate are made of different materials. The material of the first gate electrode comprises a metal material, and the second gate electrode structure comprises polysilicon.

In this embodiment, the semiconductor structure further includes: a first isolation structure 110 located between adjacent first and second active regions B and T, the first isolation structure 110 separating the adjacent first and second active regions B and T.

In this embodiment, the semiconductor structure further includes: a plurality of second isolation structures 160 located in the first active region B and the second active region T, wherein the second face 102 exposes a surface of the second isolation structures 160, the second isolation structures 160 located in the first active region B penetrate the first active region B along the first direction X, the second isolation structures 160 located in the second active region T penetrate the second active region T along the first direction X, and the second isolation structures 160 are located between adjacent word line gate structures 120 in the second direction Y, and a thickness H1 of the second isolation structures 160 is greater than a depth H2 of the third doped region 170 in a normal direction of the second face 102.

Thereby, adjacent third doped regions 170 can be spaced apart by the second isolation structure 160.

In this embodiment, the semiconductor structure further includes: a plurality of capacitors 180 located on the second side 102, each capacitor 180 being electrically connected to 1 third doped region 170.

The capacitor 180 includes: a first electrode layer (not shown), a second electrode layer (not shown), and a dielectric layer (not shown) between the first electrode layer and the second electrode layer. The shape of the dielectric layer includes: planar or "U" shaped.

When the shape of the dielectric layer is planar, the surface of the first electrode layer is flat, and the surface of the second electrode layer is flat. When the dielectric layer is in a U shape, the surface of the first electrode layer is an uneven surface, and the surface of the second electrode layer is an uneven surface; or the surface of the first electrode layer is flat, and the surface of the second electrode layer is flat.

The material of the first electrode layer includes: a metal or metal nitride; the material of the second electrode layer includes: a metal or metal nitride; the metal includes: combinations of one or more of copper, aluminum, tungsten, cobalt, nickel, and tantalum; the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride.

In this embodiment, the semiconductor structure further includes: a plurality of capacitor conductive structures 181, wherein each capacitor conductive structure 181 is connected to 1 capacitor 180 and 1 third doped region 170, respectively.

Through the capacitor conductive structure 181, the risk of the open circuit between the capacitor 180 and the third doped region 170 is reduced, the process window for forming the capacitor 180 is increased, and the improvement of the flexibility of the arrangement mode of the capacitor 180 is facilitated.

The material of the capacitive conductive structure 181 includes: a metal or metal nitride; the metal includes: combinations of one or more of copper, aluminum, tungsten, cobalt, nickel, and tantalum; the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride.

In other embodiments, the capacitor conductive structure is not provided, and the capacitor is directly connected with the third doped region, so that the forming steps of the semiconductor structure are simplified, and the efficiency is improved. In this embodiment, a projection of the capacitance onto the second face at least partially coincides with the third doped region.

In this embodiment, the semiconductor structure further includes: and a second interlayer dielectric layer 190 surrounding the capacitor conductive structure 181 and the capacitor 180.

In this embodiment, the semiconductor structure further includes: and a second substrate 200 bonded to the first substrate 100, the second substrate 200 having a surface facing the first face 101.

In this embodiment, the second substrate 200 has a logic circuit (not shown) therein. The logic circuits are electrically connected to the word line gate structure 120, the first bit line 143, and the second bit line 144, respectively. Thus, voltages can be applied to the word line gate structure 120, the first bit line 143, and the second bit line 144, respectively, by the logic circuit to control writing and reading of the memory.

In this embodiment, the semiconductor structure further includes: a plurality of first interconnect layers (not shown) electrically connected to the first bit lines 143, a plurality of second interconnect layers (not shown) electrically connected to the second bit lines 144, a plurality of third interconnect layers electrically connected to the word line gate structures 120, and a first interlayer dielectric layer (not shown) surrounding the first, second, and third interconnect layers, a surface of the first interlayer dielectric layer exposing top surfaces of the first, second, and third interconnect layers.

The first interconnect layer, the second interconnect layer and the third interconnect layer are used for being respectively connected with circuits in the second substrate 200, so that the first bit line 143, the second bit line 144 and the word line gate structure 120 are respectively electrically connected with the circuits in the second substrate 200.

In other embodiments, the first interconnect layer, the second interconnect layer, the third interconnect layer, and the first interlevel dielectric layer are absent.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A semiconductor structure, comprising:

the first substrate comprises a first face and a second face which are opposite, the first substrate comprises a plurality of first active regions and a plurality of second active regions which are separated from each other, the first active regions and the second active regions are arranged at intervals along a first direction, the first active regions and the second active regions are respectively parallel to a second direction, and the first direction and the second direction are perpendicular to each other;

the word line grid structures are arranged in the first substrate and penetrate through the first active regions and the second active regions along the first direction;

the first active area is provided with a plurality of first active doping areas and a plurality of first inactive doping areas, the first active doping areas and the first inactive doping areas are exposed on the first surface, the first active doping areas and the first inactive doping areas are arranged at intervals along the second direction, and the two sides of each word line gate structure are respectively provided with the first active doping areas and the first inactive doping areas;

the first surface exposes the second effective doping regions and the second ineffective doping regions, the second effective doping regions and the second ineffective doping regions are arranged at intervals along a second direction, the second effective doping regions and the second ineffective doping regions are respectively arranged on two sides of each word line gate structure, the first effective doping regions and the second ineffective doping regions are arranged at intervals along a first direction, and the second effective doping regions and the first ineffective doping regions are arranged at intervals along the first direction;

a plurality of third doped regions separated from each other within the first active region and the second active region, the second face exposing the third doped regions;

a first conductive structure located on each first active doping region;

a plurality of first bit lines, each of which is connected to the first conductive structures on 1 of the first active regions;

a second conductive structure located on each second active doping region;

and a plurality of second bit lines, each of which is connected with the second conductive structures on the 1 second active regions.

2. The semiconductor structure of claim 1, further comprising: and a plurality of capacitors on the second surface, each capacitor electrically connected to 1 third doped region.

3. The semiconductor structure of claim 2, further comprising: and each capacitor conductive structure is respectively connected with 1 capacitor and 1 third doped region.

4. The semiconductor structure of claim 2 or 3, further comprising: the projection of the capacitance on the second face at least partially coincides with the third doped region.

5. The semiconductor structure of claim 1, further comprising: and the second substrate is bonded with the first substrate, and the surface of the second substrate faces the first surface.

6. The semiconductor structure of claim 5, wherein the second substrate has logic circuitry therein, the logic circuitry being electrically connected to the word line gate structure, the first bit line, and the second bit line, respectively.

7. The semiconductor structure of claim 1, further comprising: a first isolation structure between adjacent first and second active regions, the first isolation structure separating the adjacent first and second active regions.

8. The semiconductor structure of claim 1, further comprising: the second isolation structures are positioned in the first active region and the second active region, the surface of each second isolation structure is exposed on the second face, the second isolation structures positioned in the first active region penetrate through the first active region along the first direction, the second isolation structures positioned in the second active region penetrate through the second active region along the first direction, in addition, the second isolation structures are arranged between the adjacent word line gate structures in the second direction, and in the normal direction of the second face, the thickness of each second isolation structure is larger than the depth of each third doped region.

9. The semiconductor structure of claim 1, wherein the word line gate structure comprises: the gate structure comprises a gate and a gate dielectric layer positioned between the gate and a first substrate.

10. The semiconductor structure of claim 9, wherein the gate is a composite gate, the gate comprises a first gate and a second gate on a top surface of the first gate, and wherein the first gate and the second gate are different materials.

11. The semiconductor structure of claim 9, wherein a top surface of the gate is lower than the first surface, the gate structure further comprising: and the cover dielectric layer is positioned on the top surface of the grid and is flush with or higher than the first surface.

12. The semiconductor structure of claim 9, wherein the word line gate structure further comprises: the word line layer is positioned on the top surface of the grid electrode, the surface of the word line layer is lower than the top surface of the first conductive structure, the surface of the word line layer is lower than the top surface of the second conductive structure, and the word line layer is respectively insulated from the first conductive structure and the second conductive structure.

13. A method of forming a semiconductor structure, comprising:

providing a first substrate, wherein the first substrate comprises a first face and a second face which are opposite to each other, the first substrate comprises a plurality of first active regions and a plurality of second active regions which are separated from each other, the first active regions and the second active regions are arranged at intervals along a first direction, the first active regions and the second active regions are respectively parallel to a second direction, and the first direction and the second direction are perpendicular to each other;

forming a plurality of word line grid structures in the first substrate, wherein the word line grid structures are arranged along a second direction, and the word line grid structures penetrate through a plurality of first active regions and a plurality of second active regions along a first direction;

forming a plurality of first effective doping regions and a plurality of first ineffective doping regions in the first active region, wherein the first effective doping regions and the first ineffective doping regions are exposed on the first surface, the first effective doping regions and the first ineffective doping regions are arranged at intervals along a second direction, and the first effective doping regions and the first ineffective doping regions are respectively arranged on two sides of each word line gate structure;

forming a plurality of second effective doping regions and a plurality of second ineffective doping regions in the second active region, wherein the second effective doping regions and the second ineffective doping regions are exposed on the first surface, the second effective doping regions and the second ineffective doping regions are arranged at intervals along a second direction, the second effective doping regions and the second ineffective doping regions are respectively arranged on two sides of each word line gate structure, the first effective doping regions and the second ineffective doping regions are arranged at intervals along a first direction, and the second effective doping regions and the first ineffective doping regions are arranged at intervals along the first direction;

forming a first conductive structure on each first effective doping area;

forming a second conductive structure on each second effective doping area;

forming a plurality of first bit lines and a plurality of second bit lines, wherein each first bit line is connected with the first conductive structures on 1 first active region, and each second bit line is connected with the second conductive structures on 1 second active region;

after the first bit line and the second bit line are formed, a plurality of third doped regions which are separated from each other are formed in the first active region and the second active region, and the second surface exposes the third doped regions.

14. The method of forming a semiconductor structure of claim 13, further comprising: a first isolation structure is formed between adjacent first and second active regions, the first isolation structure separating the adjacent first and second active regions.

15. The method of forming a semiconductor structure of claim 13, further comprising: providing a second substrate; and bonding the second substrate with the first substrate, wherein the surface of the second substrate faces to the first surface.

16. The method of forming a semiconductor structure of claim 15, further comprising: after the first substrate and the second substrate are bonded, forming the third doped region in the first active region and the second active region; after the third doped regions are formed, a plurality of capacitors are formed on the second face, each capacitor being electrically connected to 1 third doped region.

17. The method of forming a semiconductor structure of claim 15, further comprising: after the first substrate and the second substrate are bonded, a plurality of second isolation structures are formed in the first active region and the second active region, the surfaces of the second isolation structures are exposed by the second surface, the second isolation structures in the first active region penetrate through the first active region along the first direction, the second isolation structures in the second active region penetrate through the second active region along the first direction, in addition, the second isolation structures are arranged between the adjacent word line gate structures in the second direction, and in the normal direction of the second surface, the thickness of the second isolation structures is larger than the depth of the third doping region.