CN113488472B

CN113488472B - Semiconductor structure and forming method thereof

Info

Publication number: CN113488472B
Application number: CN202110795354.XA
Authority: CN
Inventors: 余兴; 华文宇; 刘藩东
Original assignee: ICLeague Technology Co Ltd
Current assignee: ICLeague Technology Co Ltd
Priority date: 2021-07-14
Filing date: 2021-07-14
Publication date: 2024-05-14
Anticipated expiration: 2041-07-14
Also published as: CN113488472A

Abstract

A semiconductor structure and method of forming the same, the semiconductor structure comprising: the first substrate comprises a plurality of first active area groups and a plurality of second active area groups which are arranged at intervals along a first direction, wherein the first active area groups comprise a plurality of first active areas, the second active area groups comprise a plurality of second active areas, and the first projection and the second projection are diamond-shaped, round or oval-shaped with the same shape; a first isolation layer located between the first active regions and the second active regions; a plurality of mutually independent word line grating structures, wherein the word line grating structures are positioned in the first substrate and the first isolation layer; a plurality of bit line structures, each bit line structure located on 1 first active granule or 1 second active granule; the capacitor structures and the bit line structures are respectively positioned on two opposite surfaces of the first substrate. The semiconductor structure can improve the performance of the dynamic random access memory and reduce the process difficulty of forming the dynamic random access memory.

Description

Semiconductor structure and forming method thereof

Technical Field

The present disclosure relates to semiconductor devices, and particularly to a semiconductor structure and a method for forming the same.

Background

A dynamic random access memory (Dynamic Random Access Memory, abbreviated as DRAM) is a semiconductor memory, and the main principle of operation is to use the magnitude of stored charges in a capacitor to represent whether a binary bit (bit) is a1 or a0.

A basic memory cell of a Dynamic Random Access Memory (DRAM) is composed of one transistor and one storage capacitor, and a memory array is composed of a plurality of memory cells. Therefore, the size of the memory chip area depends on the area size of the basic memory cell.

The existing dynamic random access memory needs to be improved.

Disclosure of Invention

The invention solves the technical problem of providing a semiconductor structure and a forming method thereof, so as to improve the performance of a dynamic random access memory and reduce the process difficulty of forming the dynamic random access memory.

In order to solve the above technical problems, the technical solution of the present invention provides a semiconductor structure, including: the first substrate comprises a plurality of first active area groups and a plurality of second active area groups, the plurality of first active area groups and the plurality of second active area groups are arranged at intervals along a first direction, each first active area group comprises a plurality of first active areas arranged along a second direction, each second active area group comprises a plurality of second active areas arranged along the second direction, the first direction and the second direction are mutually perpendicular, the first active areas are provided with first projections on the surface of the first substrate, the second active areas are provided with second projections on the surface of the first substrate, the first projections and the second projections are diamond-shaped, round or oval-shaped with the same shape, diagonal lines of the diamond-shaped are parallel to the first direction or the second direction, and central lines of the adjacent first projections and central lines of the adjacent second projections are not overlapped in the second direction; a first isolation layer located between the first active regions and the second active regions; the word line grating structures are located in the first substrate and the first isolation layer, extend along a first direction and are distributed along a second direction, and each word line grating structure penetrates through 1 row of first active areas and 1 row of second active areas adjacent to each other along the first direction; a plurality of bit line structures, each bit line structure located on 1 first active granule or 1 second active granule; and the capacitor structures and the bit line structures are respectively positioned on two surfaces opposite to the first substrate.

Optionally, the method further comprises: and a plurality of second isolation structures positioned in the first substrate, wherein the heights of the second isolation structures are smaller than those of the first isolation layers in the direction perpendicular to the surface of the first substrate, the second isolation structures are positioned between the adjacent word line grid structures, and each second isolation structure penetrates through 1 row of first active regions or 1 row of second active regions along the first direction.

Optionally, the first substrate includes a first face and a second face opposite to each other, the bit line structure is located on the first face, the capacitor structure is located on the second face, and the second face exposes a surface of the second isolation structure.

Optionally, the first doped regions are located on a first side of each first active region and each second active region, and in the second direction, each bit line structure is electrically connected to the first doped regions of 1 column of the first active regions or 1 column of the second active regions.

Optionally, the top plane of the second isolation structure in the direction towards the first face is higher than half the height of the word line gate structure.

Optionally, in the plurality of capacitor structures, each 2 capacitor structures are located on the second face of 1 first active region or 1 second active region, and in the second direction, the 2 capacitor structures are located on two sides of the second isolation structure penetrating through the 1 first active region or the 1 second active region, respectively.

Optionally, the second doped regions are located on the second face of each first active region and each second active region, in the second direction, the second doped regions are located on two sides of the second isolation structure, in the direction perpendicular to the second face, the depth of the second doped regions is smaller than the height of the second isolation structure, and each capacitor structure is electrically connected with the second doped region on one of two sides of the second isolation structure.

Optionally, a projection of the capacitor structure on the second surface is at least partially coincident with the second doped region.

Optionally, the first substrate includes a first face and a second face opposite to each other, the capacitor structure is located on the first face, the bit line structure is located on the second face, and the first face exposes a surface of the second isolation structure.

Optionally, the first doped regions are located on the second sides of each first active region and each second active region, and in the second direction, each bit line structure is electrically connected to the first doped regions of 1 column of the first active regions or 1 column of the second active regions.

Optionally, the bottom plane of the second isolation structure in the direction towards the second face is lower than half the height of the word line gate structure.

Optionally, in the plurality of capacitor structures, each 2 capacitor structures are located on a first face of 1 first active region or 1 second active region, and in the second direction, the 2 capacitor structures are located on two sides of a second isolation structure penetrating through the 1 first active region or the 1 second active region, respectively.

Optionally, the second doped regions are located on the first face of each first active region and each second active region, in the second direction, the second doped regions are located on two sides of the second isolation structure, in the direction perpendicular to the first face, the depth of the second doped regions is smaller than the height of the second isolation structure, and each capacitor structure is electrically connected with the second doped region on one of two sides of the second isolation structure.

Optionally, a projection of the capacitor structure on the first surface at least partially coincides with the second doped region.

Optionally, the method further comprises: a first conductive structure located on each of the first doped regions.

Optionally, the method further comprises: and a second conductive structure positioned between each capacitor structure and the second doped region.

Optionally, the connecting lines of centers of the adjacent first projection and second projection extend along a third direction, and an included angle between the third direction and the second direction ranges from 15 degrees to 75 degrees.

Optionally, a first distance is provided between centers of adjacent first projections and second projections in a first direction, the first distance is less than 2 times T1, and T1 is a maximum distance between the center of the first projection and an edge of the first projection in the first direction.

Optionally, a second distance is provided between centers of adjacent first projections and second projections in a second direction, the second distance is smaller than 2 times T2, and T2 is a maximum distance between the center of the first projection and an edge of the first projection in the second direction.

Correspondingly, the technical scheme of the invention also provides a method for forming the semiconductor structure, which comprises the following steps: providing a first substrate, wherein the first substrate comprises a plurality of first active area groups and a plurality of second active area groups, the plurality of first active area groups and the plurality of second active area groups are arranged at intervals along a first direction, each first active area group comprises a plurality of first active areas arranged along a second direction, each second active area group comprises a plurality of second active areas arranged along the second direction, the first direction and the second direction are mutually perpendicular, the first active areas have a first projection on the surface of the first substrate, the second active areas have a second projection on the surface of the first substrate, the first projection and the second projection are diamond-shaped, round or oval-shaped with the same shape, the diagonal line of the diamond-shaped is parallel to the first direction or the second direction, and the central lines of the adjacent first projection and the central line of the second projection are not overlapped in the second direction; forming a first isolation layer and a plurality of mutually independent word line grating structures, wherein the first isolation layer is positioned between a plurality of first active areas and a plurality of second active areas, the word line grating structures are positioned in the first substrate and the first isolation layer, extend along a first direction and are distributed along a second direction, and each word line grating structure penetrates through 1 row of first active areas and 1 row of second active areas which are adjacent to each other along the second direction along the first direction; after forming the first isolation layer and the word line gate structures, forming a plurality of bit line structures, each bit line structure being located on 1 first active area group or 1 second active area group; after the first isolation layer and the word line gate structure are formed, a plurality of capacitor structures are formed on the first active regions and the second active regions, and the capacitor structures and the bit line structures are respectively located on two surfaces opposite to the first substrate.

Optionally, the method for forming the first isolation layer and the plurality of word line gate structures includes: forming a first dielectric layer between the first active areas and the second active areas; forming a plurality of first grooves in the first dielectric layer, the first active areas and the second active areas, wherein the first grooves extend along a first direction and are arranged along a second direction, the depth of each first groove is smaller than the height of the first dielectric layer, and the inner wall surface of each first groove exposes the first dielectric layer, and 1 row of first active areas and 1 row of second active areas which are adjacent to each other along the second direction; forming a plurality of word line grating structures in the plurality of first grooves; and forming a second dielectric layer on the top surface of the word line grating structure, wherein the first dielectric layer and the second dielectric layer form the first isolation layer.

Optionally, in a direction perpendicular to a surface of the first substrate, the first substrate includes a first face and a second face opposite to each other, the bit line structure is located on the first face, and the capacitor structure is located on the second face.

Optionally, the method further comprises: after forming the first isolation layer and the word line gate structure, and before forming the bit line structure, a first doped region is formed on a first side of each first active region and each second active region.

Optionally, the method further comprises: providing a second substrate; after the bit line structure is formed, the first substrate and the second substrate are bonded, the first face facing a surface of the second substrate.

Optionally, the method further comprises: after bonding the first substrate and the second substrate, flattening the first substrate from the second surface of the first substrate until the bottom surface of the first isolation layer is exposed; after the first substrate is flattened from the second surface of the first substrate, a plurality of second isolation structures are formed in the first substrate, the second surface is exposed out of the second isolation structures, the height of the second isolation structures is smaller than that of the first isolation layers in the direction perpendicular to the second surface, the second isolation structures are located between adjacent word line grid structures, and each second isolation structure penetrates through 1 row of first active regions or 1 row of second active regions along the first direction.

Optionally, the method further comprises: after forming the second isolation structures and before forming the capacitor structures, forming second doped regions on the second face of each first active region and each second active region, wherein the second doped regions are positioned on two sides of the second isolation structures in the second direction, and the depth of the second doped regions is smaller than the height of the second isolation structures in the direction perpendicular to the second face.

Optionally, the first substrate includes a first side and a second side opposite to each other, the capacitor structure is located on the first side, and the bit line structure is located on the second side.

Optionally, the method further comprises: after the first isolation layer and the word line gate structure are formed, and before the capacitor structure is formed, a plurality of second isolation structures are formed in the first substrate, the second isolation structures are exposed from the first surface, the height of the second isolation structures is smaller than that of the first isolation layers in the direction perpendicular to the first surface, the second isolation structures are located between adjacent word line gate structures, and each second isolation structure penetrates through 1 row of first active regions or 1 row of second active regions along the first direction.

Optionally, the method further comprises: after forming the second isolation structures and before forming the capacitor structures, forming second doped regions on the first surface of each first active region and the first surface of each second active region, wherein the second doped regions are positioned on two sides of the second isolation structures in the second direction, and the depth of the second doped regions is smaller than the height of the second isolation structures in the direction perpendicular to the first surface.

Optionally, the method further comprises: providing a second substrate; after forming the capacitor structure, bonding the first substrate and the second substrate, the first face facing a surface of the second substrate.

Optionally, the method further comprises: after bonding the first substrate and the second substrate, flattening the first substrate from the second surface of the first substrate until the bottom surface of the first isolation layer is exposed; after planarizing the first substrate from the second side of the first substrate and before forming the bit line structures, first doped regions are formed at the second side of each first active region and each second active region.

Optionally, the method further comprises: a first conductive structure is formed on each of the first doped regions prior to forming the bit line structures.

Optionally, the method further comprises: a second conductive structure is formed on the second doped region on each side of the second isolation structure in the second direction prior to forming the capacitor structure.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:

in the semiconductor structure provided by the technical scheme of the invention, on one hand, the bit line structure and the capacitor structure are respectively positioned on the two opposite surfaces of the first substrate, and meanwhile, the word line gate structure is positioned in the first isolation layer and the first substrate, so that the wiring of the semiconductor structure is simpler, and the space between the bit line structure and the capacitor structure is larger, thereby reducing parasitic capacitance generated by the wiring, parasitic capacitance generated between the bit line structure and the capacitor structure, and the like, and further reducing the manufacturing difficulty of the capacitor of the memory. On the other hand, through the shapes of the first projection and the second projection, the arrangement mode of the first active areas and the second active areas, and the positions and the arrangement mode of the word line grating structures, the space in the direction perpendicular to the surface of the first substrate can be efficiently utilized, so that the area required to be occupied in the direction along the surface of the first substrate is greatly saved, the density of the memory array unit is effectively improved, and the memory capacity is improved, so that the performance of the semiconductor structure is improved.

In the method for forming the semiconductor structure provided by the technical scheme of the invention, on one hand, the bit line structure and the capacitor structure are respectively formed on the two opposite surfaces of the first substrate, and the word line grating structure is formed in the first isolation layer and the first substrate, so that the positions of the capacitor structure, the word line grating structure and the bit line structure do not need to be mutually avoided, the wiring modes of the word line grating structure and the bit line structure can be simplified, the freedom degree of the arrangement positions of the capacitor structure is improved, and the difficulty of a manufacturing process is reduced. On the other hand, by the shapes of the first projections and the second projections and the arrangement mode of the first active areas and the second active areas, the first active areas and the second active areas can be distributed in the first substrate in a uniform grid mode, so that in the process of forming a bit line structure or a capacitor structure on one of two opposite surfaces of the first substrate, the stop positions of the planarization process performed on the surface of the first substrate in each region of the first substrate can be close to or the same as each other, and the uniformity of the characteristics of each region of the semiconductor structure is good. In addition, through the shapes of the first projection and the second projection, the arrangement mode of the first active areas and the second active areas and the positions and the arrangement mode of the word line grating structures, the space in the direction perpendicular to the surface of the first substrate can be efficiently utilized, so that the area required to be occupied in the direction along the surface of the first substrate is greatly saved, the density of the memory array units is effectively improved, and the memory capacity is improved, so that the performance of the semiconductor structure is improved.

Drawings

FIG. 1 is a schematic diagram of a semiconductor structure;

Fig. 2 to 23 are schematic structural views illustrating steps in a method for forming a semiconductor structure according to an embodiment of the present invention;

fig. 24 to 33 are schematic structural views of steps in a method for forming a semiconductor structure according to another embodiment of the present invention.

Detailed Description

As described in the background, there is a need for improvement in existing dynamic random access memories. The analysis will now be described with reference to specific examples.

Fig. 1 is a schematic structural diagram of a semiconductor structure.

Referring to fig. 1, the method includes: a substrate 100; a word line gate structure 101 located within the substrate 100; a source doped region 103 and a drain doped region 102 in the substrate 100 on both sides of the word line gate structure 101; a bit line structure 105 electrically connected to the source doped region 103 through a source plug 104; a capacitor structure 107 electrically connected to the drain doped region 102 through a capacitor plug 106.

The formation process of the semiconductor structure comprises the following steps: the source and drain doped regions 103 and 102 are formed first, then the word line gate structure 101 is formed in the substrate 100, then the source plug 104 and the bit line structure 105 are formed, then the capacitor plug 106 is formed, and finally the capacitor structure 107 is formed. The channel of the semiconductor structure is U-shaped, and the source doped region 103 and the drain doped region 102 are arranged on two horizontal sides of the word line gate structure 101. The bit line structure 105 and the capacitor structure 107 are on the same side of the transistor, and are both located above the substrate in the process.

On the one hand, the capacitor plug 106 of the capacitor structure 107 needs to penetrate through the bit line structure 105, so that the overall process complexity is high, and extremely high requirements are imposed on the photolithography process and the alignment. On the other hand, the channel direction of the transistor extends along the direction of the surface of the substrate 100, and thus, the source doped region 103, the drain doped region 102, and the channel in the transistor occupy a large amount of the surface area of the substrate 100, resulting in low integration and low storage capacity of the dynamic random access memory.

In order to solve the technical problems, the technical scheme of the invention provides a semiconductor structure and a forming method thereof, wherein a bit line structure and a capacitor structure are respectively positioned on two opposite surfaces of a first substrate, and meanwhile, a word line grid electrode structure is positioned in a first isolation layer and the first substrate, so that wiring can be simplified, and parasitic capacitance can be reduced. Meanwhile, through the shapes of the first projection and the second projection, the arrangement modes of the first active areas and the second active areas and the positions and the arrangement modes of the word line grating structures, the space in the direction perpendicular to the surface of the first substrate can be efficiently utilized, so that the occupied area in the direction along the surface of the first substrate is greatly saved, the density of the memory array unit is effectively improved, and the memory capacity is improved, so that the performance of the semiconductor structure is improved.

In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.

Fig. 2 to 23 are schematic structural views illustrating steps in a method for forming a semiconductor structure according to an embodiment of the present invention.

Referring to fig. 2 to 4, fig. 2 is a schematic top view of fig. 3 and 4 along a direction M, fig. 3 is a schematic cross-sectional view of fig. 2 along a direction A1-A2, and fig. 4 is a schematic cross-sectional view of fig. 2 along a direction A3-A4, wherein a first substrate 200 is provided.

The first substrate 200 includes: the first active area groups I and the second active area groups II are arranged at intervals along the first direction X.

Each of the first active area groups I includes a plurality of first active areas 201 aligned in the second direction Y, and each of the second active area groups II includes a plurality of second active areas 202 aligned in the second direction Y. Wherein the second direction Y is perpendicular to the first direction X.

The first active region 201 has a first projection 2011 on the surface of the first substrate 200, and the second active region 202 has a second projection 2021 on the surface of the first substrate 200.

In this embodiment, the first projection 2011 and the second projection 2021 are diamond-shaped with the same shape, the diagonal of the diamond-shaped is parallel to the first direction X or the second direction Y, and the center lines of the adjacent first projection 2011 and second projection 2021 do not overlap in the second direction Y.

In other embodiments, the first projection and the second projection are circular or elliptical in shape and the centerlines of adjacent first and second projections do not coincide in the second direction.

In the present embodiment, the line 2023 between the centers of the adjacent first projection 2011 and second projection 2021 extends along the third direction Z, and the included angle α between the third direction Z and the second direction Y ranges from 15 degrees to 75 degrees.

The first substrate 200 has opposite surfaces.

Specifically, the first substrate 200 includes opposing first and second faces 203, 204 in a direction perpendicular to the surface of the first substrate 200.

The material of the first substrate 200 is a semiconductor material.

In this embodiment, the material of the first substrate 200 is silicon. In other embodiments, the material of the first substrate comprises silicon carbide, silicon germanium, a multi-component semiconductor material of group iii-v elements, silicon-on-insulator (SOI), or germanium-on-insulator. Wherein the iii-v element comprising multi-component semiconductor material comprises InP, gaAs, gaP, inAs, inSb, inGaAs or InGaAsP.

It is to be understood that only a partial region of the first substrate 200 is schematically shown in fig. 2 to 4. Thus, a number of first active regions 201 and a number of second active regions 202 located at the edges of the region, only a portion of the first active regions 201, a portion of the second active regions 202 are shown in fig. 2 to 4.

Next, a first isolation layer and a plurality of mutually independent word line gate structures are formed, the first isolation layer is located between the plurality of first active regions 201 and the plurality of second active regions 202, the word line gate structures are located in the first substrate 200 and the first isolation layer, the word line gate structures extend along a first direction X and are arranged along a second direction Y, and each word line gate structure penetrates through 1 row of first active regions 201 and 1 row of second active regions 202 adjacent to each other in the second direction Y along the first direction X. The specific method for forming the first isolation layer and the word line gate structures is shown in fig. 5 to 11.

Referring to fig. 5 and 6, fig. 5 is a schematic top view of fig. 6 along a direction M, fig. 6 is a schematic cross-sectional view of fig. 5 along a direction A1-A2, and a first dielectric layer 210 is formed between a plurality of first active regions 201 and a plurality of second active regions 202.

In this embodiment, the method for forming the first dielectric layer 210 includes: etching the first substrate 200 to form first isolation grooves (not shown) between the first active regions 201 and the second active regions 202, the first faces 203 exposing the first isolation grooves; the first dielectric layer 210 is formed within the first isolation recess.

In this embodiment, the method of etching the first substrate 200 to form a first isolation groove between the plurality of first active regions 201 and the plurality of second active regions 202 includes: forming a first isolation trench mask layer (not shown) on the first face 203, the first isolation trench mask layer exposing the first face 203 between the plurality of first active regions 201 and the plurality of second active regions 202; and etching the first substrate 200 by taking the first isolation groove mask layer as a mask to form the first isolation groove.

In the present embodiment, the process of etching the first substrate 200 to form the first isolation recess includes at least one of a dry etching process and a wet etching process.

In this embodiment, the method for forming the first dielectric layer 210 in the first isolation groove includes: forming a first dielectric material layer (not shown) within the first face 203 and the first isolation recess; the first dielectric material layer is planarized until the first face 203 is exposed. The process for forming the first dielectric material layer comprises the following steps: at least one of a chemical vapor deposition process (CVD), a flowable chemical vapor deposition process (FCVD), a physical vapor deposition Process (PVD), and a spin-on process. The process of planarizing the first dielectric material layer includes a chemical mechanical polishing process (CMP).

Referring to fig. 7 to 9, fig. 7 is a schematic top view of fig. 8 along a direction M, fig. 8 is a schematic cross-sectional view of fig. 7 along a direction B1-B2, fig. 9 is a schematic perspective view of 1 first active region and a portion of first grooves in fig. 7, and a plurality of first grooves 211 are formed in the first dielectric layer 210, the plurality of first active regions 201, and the plurality of second active regions 202, wherein the plurality of first grooves 211 extend along a first direction X and are aligned along a second direction Y.

The first grooves 211 provide space for forming the word line gate structure later.

The depth D1 of the first grooves 211 is smaller than the height H1 of the first dielectric layer 210 in a direction perpendicular to the first face 203, and the inner wall surface of each first groove 211 exposes the first dielectric layer 210, and 1 row of first active regions 201 and 1 row of second active regions 202 adjacent in the second direction Y.

It is to be understood that fig. 9 only schematically illustrates 1 first active region 201 in fig. 7, and a portion of first recess 211 within first active region 201. In addition, since the second active region 202 has the same shape as the first active region 201, for the three-dimensional structure of 1 second active region 202 in fig. 7 and a portion of the first recess 211 in the second active region 202, please refer to the first active region 201 and the first recess 211 shown in fig. 9.

In this embodiment, the method for forming the first grooves 211 in the first dielectric layer 210, the first active regions 201 and the second active regions 202 includes: forming a first recess mask layer (not shown) on the first surface 203 and the first dielectric layer 210, where the first recess mask layer exposes a portion of the first surface 203 and a portion of the top surface of the first dielectric layer 210; the first substrate 200 and the first dielectric layer 210 are etched using the first recess mask layer as a mask to form the first recess 211.

Referring to fig. 10 and 11, fig. 10 is a schematic top view of fig. 11 along a direction M, fig. 11 is a schematic cross-sectional view of fig. 10 along a direction B1-B2, and a plurality of word line gate structures 220 are formed in the plurality of first grooves 211.

The word line gate structures 220 are located in the first substrate 200 and the first dielectric layer 210, the word line gate structures 220 extend along a first direction X and are arranged along a second direction Y, and each word line gate structure 220 extends through 1 row of the first active regions 201 and 1 row of the second active regions 202 adjacent to each other in the second direction Y along the first direction X.

For ease of understanding, the schematic representation in fig. 10 shows: a first projection 2011 of 1 row of first active regions 201 and a second projection 2021 of 1 row of second active regions 202 adjacent in the second direction Y.

In this embodiment, the top surface of the word line gate structure 220 is lower than the first surface 203.

In this embodiment, the word line gate structure 220 includes: a gate electrode (not shown) located within the first recess 211, and a gate dielectric layer (not shown) located between the gate electrode and the surface of the first substrate 200.

In this embodiment, the material of the gate dielectric layer includes silicon oxide or a low K (K is less than 3.9) material.

In other embodiments, the material of the gate dielectric layer comprises a high-K material (K greater than 3.9) comprising aluminum oxide or hafnium oxide.

In this embodiment, the gate is a single layer. The material of the gate is, for example, polysilicon or a metal material.

In other embodiments, the gate is a composite gate, the gate includes a first gate and a second gate on a top surface of the first gate, and materials of the first gate and the second gate are different. The material of the first gate electrode comprises a metal material, and the second gate electrode structure comprises polysilicon. Because the grid electrode comprises the first grid electrode and the second grid electrode which are made of different materials, the threshold voltage of the word line grid structure can be adjusted through the proportion adjustment of the volumes of the first grid electrode and the second grid electrode so as to meet different device design requirements. Wherein the metallic material comprises tungsten.

In this embodiment, the method for forming the word line gate structure 220 includes: forming a gate dielectric film (not shown) on the surface of the first substrate 200 exposed in the first recess 211 and the first surface 203; after forming the gate dielectric film, forming a gate material layer (not shown) in the first recess 211, on the first surface 203, and on the surface of the first dielectric layer 210, wherein the gate material layer fills the first recess 211; and etching the gate material layer and the gate dielectric film until the top surface of the gate material layer and the top surface of the gate dielectric film are lower than the first surface 203, thereby forming the gate and the gate dielectric layer.

With continued reference to fig. 10 and 11, a second dielectric layer 230 is formed on the top surface of the word line gate structure 220, and the first dielectric layer 210 and the second dielectric layer 230 form a first isolation layer (not labeled in the figure).

Through the second dielectric layer 230 on the top surface of the word line grating structure 220, on one hand, the word line grating structure 220 can be protected in a subsequent process, and damage to the word line grating structure 220 caused by the subsequent process is reduced, and on the other hand, insulation between the word line grating structure 220 and a subsequently formed bit line structure can be realized, so that the circuit design requirement of a memory is met.

Specifically, the second dielectric layer 230 is located in the first groove 211, and the top surface of the second dielectric layer 230 is flush with the first surface 203. By locating the second dielectric layer 230 in the first recess 211, the internal space of the first substrate 200 can be effectively utilized, thereby further improving the integration level of the semiconductor structure, reducing the influence of the position of the second dielectric layer 230 on the positions of other semiconductor structures, and being beneficial to simplifying the circuit layout of the semiconductor structure.

The process of forming the second dielectric layer 230 includes: at least one of a chemical vapor deposition process, a flowable chemical vapor deposition process, a physical vapor deposition process, and a spin-on process.

In this embodiment, the material of the first isolation layer includes a dielectric material including silicon oxide or a low K (K less than 3.9) material. The purpose of using low-K materials is to further reduce parasitic capacitance by low dielectric constant materials.

In this embodiment, T3 is greater than WB, where T3 is the maximum spacing between edges of each first projection 2011 in the first direction X, and WB is the line width of the subsequently formed bit line structure in the first direction X (as shown in fig. 15). Therefore, the short circuit risk between adjacent bit line structures is reduced, and the reliability of the semiconductor structure is improved.

In the present embodiment, a first distance W1 is provided between centers of adjacent first projections 2011 and second projections 2021 in a first direction X, the first distance W1 is less than 2 times T1, and the T1 is a maximum distance between the center of the first projection 2011 and an edge of the first projection 2011 in the first direction X.

Since the first spacing W1 is smaller than 2 times T1, that is, the plurality of first active regions 201 and the plurality of second active regions 202 are staggered in the first direction X, the utilization efficiency of the surface of the first substrate 200 is further improved, and thus, the integration of the semiconductor structure can be better improved.

In this embodiment, t1=t3/2.

In the present embodiment, the centers of the adjacent first projection 2011 and second projection 2021 have a second spacing W2 therebetween in the second direction Y, and the second spacing W2 is greater than the width WZ of the word line gate structure 220 in the second direction.

Specifically, neither the first projection 2011 nor the second projection 2021 is centered within the projection of any word line gate structure 220 onto the first face 203. Thereby, it is ensured that there is no contact between adjacent word line gate structures 220 in the second direction Y.

In this embodiment, the second distance W2 is also smaller than 2 times T2, where T2 is the maximum distance between the center of the first projection 2011 and the edge of the first projection 2011 in the second direction Y.

Since the second spacing W2 is smaller than 2 times T2, that is, the plurality of first active regions 201 and the plurality of second active regions 202 are staggered in the second direction Y, the utilization efficiency of the surface of the first substrate 200 is further improved, and thus, the integration of the semiconductor structure can be better improved.

Referring to fig. 12 and 13, fig. 12 is a schematic top view of fig. 13 along a direction M, and fig. 13 is a schematic cross-sectional view of fig. 12 along a direction B1-B2, wherein a first doped region U1 is formed on a first surface 203 of each of the first active regions 201 and each of the second active regions 202.

In this embodiment, the method for forming the first doped region U1 includes: after the first isolation layer is formed, an ion implantation process is performed on the first surface 203 to implant dopant ions into the first substrate 200, thereby forming the first doped region U1. Wherein the doping ions comprise N-type ions or P-type ions, and the N-type ions comprise phosphorus ions, arsenic ions or antimony ions; the P-type ions include boron ions, boron fluoride ions, or indium ions.

Referring to fig. 14, fig. 14 is consistent with the view direction of fig. 12, a first conductive structure 240 is formed on each first doped region U1.

The first conductive structure 240 is used to electrically connect the subsequently formed bit line structure with the first doped region U1 of 1 first active set I (shown in fig. 2) or 1 second active set II (shown in fig. 2).

The process window size for the subsequent formation of the bit line structure can be increased by the first conductive structure 240. Specifically, the flexibility of the structure of the first conductive structure 240 is high, so by adjusting the structure of the first conductive structure 240, for example, offsetting the projection of the first conductive structure 240 on the first surface 203 with respect to the projection of the first doped region U1 on the first surface 203, or making the projection range of the first conductive structure 240 on the first surface 203 exceed the range of the first doped region U1, etc., the limitation on the position of the bit line structure and the limitation on the size of the line width WB (as shown in fig. 15) can be reduced, thereby increasing the size of the process window for forming the bit line structure later.

In addition, the bit line structure formed later is lifted by the first conductive structure 240, and thus, the space between the bit line structure and the word line gate structure 220 is increased, thereby improving insulation reliability between the bit line structure and the word line gate structure 220, and reducing parasitic capacitance between the word line gate structure 220 and the bit line structure 250.

In other embodiments, the first conductive structure is not formed and the bit line structure is in direct contact with the first doped region. Thus, the process steps are reduced, and the manufacturing efficiency is improved.

In this embodiment, the method of forming the plurality of first conductive structures 240 includes: forming a third dielectric layer 261 (as shown in fig. 16) on the surfaces of the word line gate structure 220, the first isolation layer and the first doped region U1; forming a first mask layer (not shown) on the third dielectric layer 261, wherein the first mask layer exposes a part of the surface of the third dielectric layer 261; etching the third dielectric layer 261 with the first mask layer as a mask until the surface of the first doped region U1 is exposed, so as to form a plurality of first conductive openings (not shown); forming a first conductive structure material layer (not shown) in the first conductive opening and on the surface of the third dielectric layer 261, wherein the surface of the first conductive structure material layer is higher than the surface of the third dielectric layer 261; the first conductive structure material layer is planarized until the surface of the third dielectric layer 261 is exposed.

In this embodiment, the process of forming the third dielectric layer 261 includes: at least one of a chemical vapor deposition process, a flowable chemical vapor deposition process, a physical vapor deposition process, and a spin-on process.

In the present embodiment, the etching process for forming the first conductive opening includes at least one of a dry etching process and a wet etching process.

In this embodiment, the process of forming the first conductive structure material layer includes a metal plating process, a chemical vapor deposition process, and the like.

In this embodiment, the process of planarizing the first conductive structure material layer includes a chemical mechanical polishing process.

It should be noted that, in order to facilitate understanding of the position of the first conductive structure 240, the third dielectric layer 261 is not shown in fig. 14.

In this embodiment, the first conductive structure 240 is a conductive plug.

In this embodiment, the material of the first conductive structure 240 includes a metal or silicon, and the metal includes one or more of copper, aluminum, tungsten, cobalt, nickel, and tantalum.

In this embodiment, the material of the third dielectric layer 261 includes a dielectric material, and the dielectric material includes silicon oxide or a low-K material. The purpose of using low-K materials is to further reduce parasitic capacitance by low dielectric constant materials.

Referring to fig. 15 and 16, fig. 15 is a schematic top view of fig. 16 along a direction M, fig. 16 is a schematic cross-sectional view of fig. 15 along a direction B1-B2, after forming the first conductive structures 240, a plurality of bit line structures 250 are formed, and each bit line structure 250 is located on 1 first active area group I (shown in fig. 2) or 1 second active area group II (shown in fig. 2).

Specifically, the bit line structure 250 in this embodiment is located on the first surface 203. Also, in the second direction Y, each bit line structure 250 is electrically connected to 1 column of the first active region 201 or 1 column of the first doped region U1 of the second active region 202.

In this embodiment, the material of the bit line structure 250 comprises a metal comprising a combination of one or more of copper, aluminum, tungsten, cobalt, nickel, and tantalum.

In this embodiment, the method of forming the bit line structures 250 includes: forming a fourth dielectric layer 262 on the surfaces of the first conductive structure 240 and the third dielectric layer 261; forming a second mask layer (not shown) on the surface of the fourth dielectric layer 262, where the second mask layer exposes a portion of the surface of the fourth dielectric layer 262; etching the fourth dielectric layer 262 with the second mask layer as a mask until the top surface of the first conductive structure 240 is exposed, and forming a plurality of bit line openings (not shown) in the fourth dielectric layer 262; forming a bit line material layer (not shown) within the bit line openings and on a surface of the fourth dielectric layer 262, the bit line material layer surface being higher than the fourth dielectric layer 262 surface; the bit line material layer is planarized until the surface of the fourth dielectric layer 262 is exposed.

In this embodiment, the process of forming the fourth dielectric layer 262 includes: at least one of a chemical vapor deposition process, a flowable chemical vapor deposition process, a physical vapor deposition process, and a spin-on process.

In the present embodiment, the etching process for forming the bit line opening includes at least one of a dry etching process and a wet etching process.

In this embodiment, the process of forming the bit line material layer includes a metal plating process, a chemical vapor deposition process, and the like.

In this embodiment, the process of planarizing the bit line material layer includes a chemical mechanical polishing process.

In this embodiment, the material of the fourth dielectric layer 262 includes a dielectric material, and the dielectric material includes silicon oxide or a low-K material. The purpose of using low-K materials is to further reduce parasitic capacitance by low dielectric constant materials.

In this embodiment, after the bit line structure 250 is formed, a fifth dielectric layer 263 is formed on the surfaces of the bit line structure 250 and the fourth dielectric layer 262.

In this embodiment, the process of forming the fifth dielectric layer 263 includes: at least one of a chemical vapor deposition process, a flowable chemical vapor deposition process, a physical vapor deposition process, and a spin-on process.

In this embodiment, the material of the fifth dielectric layer 263 includes a dielectric material, and the dielectric material includes silicon oxide or a low-K material. The purpose of using low-K materials is to further reduce parasitic capacitance by low dielectric constant materials.

For ease of understanding, the fifth dielectric layer 263 on the surface of the bit line structure 250 and the surface of the fourth dielectric layer 262 is not shown in fig. 15.

Referring to fig. 17 and 18, fig. 17 is a schematic top view of fig. 18 along a direction N, and fig. 18 is a schematic cross-sectional view of fig. 17 along a direction C1-C2, wherein a second substrate 300 is provided.

In this embodiment, the second substrate 300 has a logic circuit (not shown) therein.

In this embodiment, the logic circuit includes 1 or more of a row address decoder, a data input buffer, a data output buffer, a sense amplifier, a column address decoder, and a driving circuit.

In other embodiments, the second substrate has no logic circuitry therein.

With continued reference to fig. 17 and 18, after the fifth dielectric layer 263 is formed, the first substrate 200 and the second substrate 300 are bonded, and the first surface 203 faces the surface of the second substrate 300.

The logic circuit is electrically connected to the word line gate structure 220 and the bit line structure 250, respectively.

Through the logic circuit, voltages can be applied to the word line gate structure 220, the bit line structure 250, respectively, to control writing and reading of the memory.

With continued reference to fig. 17 and 18, after bonding the first substrate 200 and the second substrate 300, the first substrate 200 is planarized from the second surface 204 of the first substrate 200 until the bottom surface of the first isolation layer is exposed.

In this embodiment, the process of planarizing the first substrate 200 from the second side 204 of the first substrate 200 includes a chemical mechanical polishing process.

Referring to fig. 19 and 20, fig. 19 is a schematic top view of fig. 20 along a direction N, fig. 20 is a schematic cross-sectional view of fig. 19 along a direction C1-C2, after the first substrate 200 is planarized from the second surface 204 of the first substrate 200, a plurality of second isolation structures 270 are formed in the first substrate 200, and the second surface 204 exposes the surfaces of the second isolation structures 270.

The height H2 of the second isolation structure 270 is smaller than the height of the first isolation layer in a direction perpendicular to the second face 204.

Specifically, the height H2 of the second isolation structure 270 is smaller than the height H1 of the first dielectric layer 210 (as shown in fig. 8).

The second isolation structures 270 are located between adjacent word line gate structures 220, and each second isolation structure 270 extends through 1 row of the first active regions 201 or 1 row of the second active regions 202 in the first direction X.

The second isolation structure 270 is used to separate adjacent second doped regions formed later, so as to insulate the adjacent second doped regions from each other.

In this embodiment, the top plane of the second isolation structure 270 in the direction towards the first face 203 is higher than half the height of the word line gate structure 220. Thus, leakage current between adjacent word line gate structures 220 is further reduced, and reliability of the semiconductor structure is improved.

In this embodiment, the method of forming the second isolation structure 270 includes: forming a second isolation structure mask layer (not shown) on the second surface 204, wherein the second isolation structure mask layer exposes a part of the surfaces of the first active regions 201, a part of the surfaces of the second active regions 202, and a part of the surfaces of the first isolation layers; etching the first substrate 200 from the second surface 204 by using the second isolation structure mask layer as a mask, and forming a plurality of second isolation openings (not shown) in the first substrate 200; forming a second isolation material layer (not shown) in the second isolation openings, on the bottom surface of the first isolation layer and on the second surface 204, wherein the surface of the second isolation material layer is higher than that of the first isolation layer; the second spacer material layer is planarized until the first spacer surface and the second face 204 are exposed.

In this embodiment, the process of forming the second isolation material layer includes a deposition process or a spin-on process, where the deposition process is, for example, a chemical vapor deposition process or a physical vapor deposition process. The process of planarizing the second isolation material layer includes a chemical mechanical polishing process or the like.

In this embodiment, the material of the second isolation structure 270 includes a dielectric material, which includes silicon oxide or a low-K material. The purpose of using low-K materials is to further reduce parasitic capacitance by low dielectric constant materials.

Referring to fig. 21, the view direction of fig. 21 is consistent with that of fig. 19, after the second isolation structures 270 are formed, second doped regions U2 are formed on the second sides 204 of each first active region 201 and each second active region 202, and in the second direction Y, the second doped regions U2 are located on both sides of the second isolation structures 270, and in the direction perpendicular to the second sides 204, the depth of the second doped regions U2 is smaller than the height H2 of the second isolation structures 270 (as shown in fig. 20).

In this embodiment, the method for forming the second doped region U2 includes: after forming the second isolation structure 270, an ion implantation process is performed on the second surface 204 to implant dopant ions into the first substrate 200 to form the second doped region U2. Wherein the doping ions comprise N-type ions or P-type ions.

In this embodiment, the second isolation structure 270 is formed prior to the second doped region U2.

In other embodiments, the second isolation structure is formed after the second doped region is formed.

Referring to fig. 22 and 23, fig. 22 is a schematic top view of fig. 23 along a direction N, fig. 23 is a schematic cross-sectional view of fig. 22 along a direction C1-C2, after forming the second isolation structures 270, a plurality of capacitor structures 280 are formed on the plurality of first active regions 201 and the plurality of second active regions 202, and the capacitor structures 280 and the bit line structures 250 are respectively located on two opposite surfaces of the first substrate 200.

Specifically, several capacitor structures 280 in the present embodiment are located on the second surface 204.

On the one hand, since the bit line structure 250 and the capacitor structure 280 are formed on the two opposite surfaces (the first surface 203 and the second surface 204) of the first substrate 200, and the word line structure 220 is formed in the first isolation layer and the first substrate 200, the positions of the capacitor structure 280, the word line structure 220 and the bit line structure 250 do not need to be avoided, so that the wiring mode of the word line structure 220 and the bit line structure 250 can be simplified, the freedom degree of the arrangement position of the capacitor structure 280 is improved, and the difficulty of the manufacturing process is reduced.

On the other hand, by the shapes of the first projection 2011 and the second projection 2021 and the arrangement manner of the plurality of first active regions 201 and the plurality of second active regions 202, the plurality of first active regions 201 and the plurality of second active regions 202 can be distributed in the first substrate 200 in a uniform grid form, and thus, in the planarization process (as shown in fig. 17) of planarizing the first substrate 200 from the second surface 204 of the first substrate 200, the stop positions of the respective regions of the first substrate 200 can be close to or the same as each other, thereby being beneficial to making uniformity of characteristics of the respective regions of the semiconductor structure good.

In addition, by the shapes of the first projections 2011 and the second projections 2021, the arrangement of the plurality of first active regions 201 and the plurality of second active regions 202, and the positions and arrangement of the word line gate structures 220, space in a direction perpendicular to the surface of the first substrate 200 can be efficiently utilized, thereby greatly saving an area required to be occupied in the direction along the surface of the first substrate 200, effectively improving the density of memory array units, and improving the memory capacity to improve the performance of the semiconductor structure.

In the present embodiment, each 2 capacitor structures 280 are located on the second face 204 of 1 first active region 201 or 1 second active region 202, and in the second direction Y, the 2 capacitor structures 280 are located on two sides of the second isolation structure 270 penetrating the 1 first active region 201 or 1 second active region 202, respectively. Specifically, each capacitor structure 280 is electrically connected to the second doped region U2 on one of two sides of the second isolation structure 270. Thereby, the storage capacity of the memory is further increased.

In this embodiment, the projection of the capacitor structure 280 on the second surface 204 at least partially coincides with the second doped region U2.

Since the projection of the capacitor structure 280 on the second surface 204 at least partially coincides with the second doped region U2, the electrical connection between the capacitor structure 280 and the second doped region U2 can be achieved, so that the freedom of the arrangement position and the structural shape of the capacitor structure 280 is large, and the capacitor structure 280 can have a larger volume to increase the capacity of the memory.

In this embodiment, the capacitor structure 280 includes: a first electrode layer (not shown), a second electrode layer (not shown), and a dielectric layer (not shown) between the first electrode layer and the second electrode layer.

The shape of the dielectric layer includes: planar or "U" shaped.

When the dielectric layer is planar, the surface of the first electrode layer is flat, and the surface of the second electrode layer is flat.

When the dielectric layer is U-shaped, the surface of the first electrode layer is an uneven surface, and the surface of the second electrode layer is an uneven surface; or the surface of the first electrode layer is flat, and the surface of the second electrode layer is flat.

The material of the first electrode layer includes: a metal or metal nitride; the material of the second electrode layer includes: a metal or metal nitride; the metal comprises: a combination of one or more of copper, aluminum, tungsten, cobalt, nickel, and tantalum; the metal nitride includes one or more combinations of tantalum nitride and titanium nitride.

The material of the dielectric layer comprises: high-K materials such as titanium oxide, zirconium oxide, and hafnium oxide.

In the present embodiment, before forming the capacitor structure 280, a second conductive structure 281 is formed on the second doped region U2 on each side of the second isolation structure 270 along the second direction Y.

The second conductive structure 281 is configured to electrically connect the capacitor structure 280 and the second doped region U2.

The process window size for forming the capacitor structure 280 can be increased by the second conductive structure 281. Specifically, the second conductive structure 281 has high structural flexibility in contact with the second doped region U2. Meanwhile, by adjusting the structure of the second conductive structure 281, for example, making the projection of the second conductive structure 281 on the second surface 204 offset with respect to the projection of the second doped region U2 on the second surface 204, or making the projection range of the second conductive structure 281 on the second surface 204 exceed the projection range of the second doped region U2 on the second surface 204, the flexibility of the arrangement manner of the capacitor structure 280 and the limitation of the shape structure of the capacitor structure 280 can be further improved, so that the size of the process window for forming the capacitor structure 280 is increased. In addition, the risk of the capacitor structure 280 being disconnected from the second doped region U2 is reduced by the second conductive structure 281.

Specifically, the projection of the capacitor structure 280 on the second surface 204 at least partially coincides with the projection of the second conductive structure 281 on the second surface 204. The capacitive structure 280 may be offset in any direction relative to the second conductive structure 281.

In this embodiment, the second conductive structure 281 is a conductive plug.

The materials of the second conductive structure 281 include: a metal or metal nitride; the metal comprises: a combination of one or more of copper, aluminum, tungsten, cobalt, nickel, and tantalum; the metal nitride includes one or more combinations of tantalum nitride and titanium nitride.

In other embodiments, the second conductive structure is not formed and the capacitive structure is in direct contact electrical connection with the second doped region.

In this embodiment, the method for forming the second conductive structure 281 includes: forming a sixth dielectric layer 290 on the second side 204; forming a plurality of second conductive structure openings (not shown) in the sixth dielectric layer 290, wherein the second conductive structure openings expose a portion of the surface of the second doped region U2; the second conductive structure openings are filled with the material of the second conductive structure 281.

In this embodiment, the material of the sixth dielectric layer 290 includes a dielectric material, and the dielectric material includes silicon oxide or a low-K material. The purpose of using low-K materials is to further reduce parasitic capacitance by low dielectric constant materials.

In this embodiment, after the capacitor structures 280 are formed, a conductive layer 282 is formed between each capacitor structure 280. The material of the conductive layer 282 includes a material having good conductivity and good filling ability, such as SiG and tungsten.

It should be noted that, for ease of understanding, the conductive layer 282 is not shown in fig. 22.

Accordingly, an embodiment of the present invention further provides a semiconductor structure formed by the above method, please continue to refer to fig. 22 and 23, which includes:

A first substrate 200, the first substrate 200 including a plurality of first active area groups I (shown in fig. 2) and a plurality of second active area groups II (shown in fig. 2), the plurality of first active area groups I and the plurality of second active area groups II being arranged at intervals along a first direction X, each first active area group I including a plurality of first active areas 201 (shown in fig. 2) arranged along a second direction Y, each second active area group II including a plurality of second active areas 202 (shown in fig. 2) arranged along the second direction Y, the first direction X and the second direction Y being perpendicular to each other;

A first isolation layer between the first plurality of active regions 201 and the second plurality of active regions 202;

A plurality of mutually independent word line gate structures 220, the word line gate structures 220 being located within the first substrate 200 and the first isolation layer, the word line gate structures 220 extending along a first direction X and being arranged along a second direction Y, each word line gate structure 220 penetrating through 1 row of first active regions 201 and1 row of second active regions 202 adjacent in the second direction Y along the first direction X;

a number of bit line structures 250, each bit line structure 250 being located on 1 first active granule I or 1 second active granule II;

A plurality of capacitor structures 280 located on the plurality of first active regions 201 and the plurality of second active regions 202, and the capacitor structures 280 and the bit line structures 250 are respectively located on opposite surfaces of the first substrate 200.

The first active region 201 has a first projection 2011 (shown in fig. 2) on the surface of the first substrate 200, and the second active region 202 has a second projection 2021 (shown in fig. 2) on the surface of the first substrate 200.

On the one hand, since the bit line structure 250 and the capacitor structure 280 are respectively located on two opposite surfaces of the first substrate 200, and at the same time, the word line gate structure 220 is located in the first isolation layer and the first substrate 200, the wiring of the semiconductor structure is simpler, and the space between the bit line structure 250 and the capacitor structure 280 is larger, so that parasitic capacitance generated by the wiring, parasitic capacitance generated between the bit line structure 280 and the capacitor structure 280, and the like are reduced, and thus, the manufacturing difficulty of the capacitor of the memory is reduced.

On the other hand, by the shapes of the first projections 2011 and the second projections 2021, the arrangement of the plurality of first active regions 201 and the plurality of second active regions 202, and the positions and arrangement of the word line gate structures 220, space in the direction perpendicular to the surface of the first substrate 200 can be efficiently utilized, and thus, an area required to be occupied in the direction along the surface of the first substrate 200 is greatly saved, thereby effectively improving the density of the memory array unit, and improving the memory capacity to improve the performance of the semiconductor structure.

Specifically, the first substrate 200 includes a first surface 203 and a second surface 204 opposite to each other, the bit line structure 250 is located on the first surface 203, the capacitor structure 280 is located on the second surface 204, and the second surface 204 exposes a bottom surface of the first isolation layer.

The material of the first substrate 200 is a semiconductor material.

In this embodiment, T3 (shown in fig. 10) is greater than WB (shown in fig. 15), where T3 is the maximum spacing between edges of each first projection 2011 in the first direction X, and WB is the line width of the bit line structure 250 in the first direction X. Therefore, the short circuit risk between adjacent bit line structures is reduced, and the reliability of the semiconductor structure is improved.

In the present embodiment, a first distance W1 (as shown in fig. 10) is provided between centers of adjacent first projections 2011 and second projections 2021 in a first direction, the first distance W1 is less than 2 times T1 (as shown in fig. 10), and the T1 is a maximum distance between the center of the first projection 2011 and an edge of the first projection 2011 in the first direction X.

In this embodiment, t1=t3/2.

In the present embodiment, a second space W2 (as shown in fig. 10) is provided between centers of adjacent first projections 2011 and second projections 2021 in the second direction Y, and the second space W2 is greater than a width WZ (as shown in fig. 10) of the word line gate structure 220 in the second direction.

In this embodiment, the second distance W2 is also smaller than 2 times T2 (as shown in fig. 10), where T2 is the maximum distance between the center of the first projection 2011 and the edge of the first projection 2011 in the second direction Y.

In this embodiment, the word line gate structure 220 includes: a gate electrode (not shown) located within the first recess 211 (shown in fig. 7 and 8), and a gate dielectric layer (not shown) located between the gate electrode and the surface of the first substrate 200.

In this embodiment, the first isolation layer includes: a first dielectric layer 210 located between the first plurality of active regions 201 and the second plurality of active regions 202; and a second dielectric layer 230 on top of the word line gate structure 220.

In this embodiment, the material of the first isolation layer includes a dielectric material, and the dielectric material includes silicon oxide or a low-K material. The purpose of using low-K materials is to further reduce parasitic capacitance by low dielectric constant materials.

The shape of the dielectric layer includes: planar or "U" shaped.

In this embodiment, the semiconductor structure further includes: the first doped regions U1 located at the first side 203 of each first active region 201 and each second active region 202, and each bit line structure 250 is electrically connected to the first doped regions U1 of 1 column of the first active regions 201 or 1 column of the second active regions 202 in the second direction Y.

The first doped region U1 has doped ions therein. The doping ions comprise N-type ions or P-type ions, and the N-type ions comprise phosphorus ions, arsenic ions or antimony ions; the P-type ions include boron ions, boron fluoride ions, or indium ions.

In this embodiment, the semiconductor structure further includes: a first conductive structure 240 located on each first doped region U1.

The first conductive structures 240 are used to electrically connect each bit line structure 250 to the first doped region U1 of either 1 first active set I (shown in fig. 2) or 1 second active set II (shown in fig. 2).

In this embodiment, the first conductive structure 240 is a conductive plug.

In other embodiments, there is no first conductive structure between the bit line structure and the first doped region, which is in direct contact with the first doped region surface.

In this embodiment, the semiconductor structure further includes: and the third dielectric layer 261 is positioned on the surface of the first isolation layer and the side wall surface of the first conductive structure 240, and the top surface of the first conductive structure 240 is exposed on the surface of the third dielectric layer 261.

In this embodiment, the semiconductor structure further includes: a fourth dielectric layer 262 (as shown in fig. 15) disposed on the top surface of the first conductive structure 240 and on the surface of the third dielectric layer 261, where the fourth dielectric layer 262 is further disposed on the sidewall surface of the bit line structure 250.

In this embodiment, the semiconductor structure further includes: and a fifth dielectric layer 263 on the bit line structure 250 and on the surface of the fourth dielectric layer 262.

The material of the third dielectric layer 261 includes a dielectric material, the material of the fourth dielectric layer 262 includes a dielectric material, and the material of the fifth dielectric layer 263 includes a dielectric material. The dielectric material comprises silicon oxide or a low-K material. The purpose of using low-K materials is to further reduce parasitic capacitance by low dielectric constant materials.

In this embodiment, the semiconductor structure further includes: a plurality of second isolation structures 270 located within the first substrate 200, the second face 204 exposing a surface of the second isolation structures 270, the second isolation structures 270 being located between adjacent word line gate structures 220, and each second isolation structure 270 extending through 1 row of the first active regions 201 or 1 row of the second active regions 202 along the first direction X.

The height H2 (shown in fig. 20) of the second isolation structure 270 is smaller than the height of the first isolation layer in a direction perpendicular to the second face 204.

In this embodiment, the top plane of the second isolation structure 270 in the direction towards the first face 203 is higher than half the height of the word line gate structure 220.

In the present embodiment, each 2 capacitor structures 280 are located on the second face 204 of 1 first active region 201 or 1 second active region 202, and in the second direction Y, the 2 capacitor structures 280 are located on two sides of the second isolation structure 270 penetrating the 1 first active region 201 or 1 second active region 202, respectively.

In this embodiment, the semiconductor structure further includes: and second doped regions U2 located on the second sides 204 of each of the first active regions 201 and each of the second active regions 202, the second doped regions U2 being located on both sides of the second isolation structure 270 in the second direction Y.

In this embodiment, in the direction perpendicular to the second surface 204, the depth of the second doped region U2 is smaller than the height H2 of the second isolation structure 270 (as shown in fig. 20), and each capacitor structure 280 is electrically connected to the second doped region U2 on one of two sides of the second isolation structure 270.

The second doped region U2 has doped ions therein. The doping ions comprise N-type ions or P-type ions, and the N-type ions comprise phosphorus ions, arsenic ions or antimony ions; the P-type ions include boron ions, boron fluoride ions, or indium ions.

In this embodiment, the semiconductor structure further includes: a second conductive structure 281 is located between each capacitor structure 280 and the second doped region U2.

Specifically, in the present embodiment, the projection of the capacitor structure 280 on the second surface 204 overlaps with the projection of the second conductive structure 281 on the second surface 204. The capacitive structure 280 may be offset in any direction relative to the second conductive structure 281.

In this embodiment, the second conductive structure 281 is a conductive plug.

In other embodiments, the capacitor structure and the second doped region do not have a second conductive structure therebetween, and the capacitor structure is in direct contact electrical connection with the second doped region.

In this embodiment, the semiconductor structure further includes: a second dielectric layer 290 between each second conductive structure 281.

The material of the second dielectric layer 290 includes a dielectric material including silicon oxide or a low-K material.

In this embodiment, the semiconductor structure further includes: a conductive layer 282 is located between each of the capacitor structures 280. The material of the conductive layer 282 includes a material having good conductivity and good filling ability, such as SiG and tungsten.

In this embodiment, the semiconductor structure further includes: a second substrate 300 bonded to the first substrate 200, the first face 203 facing a surface of the second substrate.

In other embodiments, the second substrate has no logic circuitry therein.

Referring to fig. 24 and 25 on the basis of fig. 10 and 11, fig. 24 is a schematic top view of fig. 25 along the direction M, fig. 25 is a schematic cross-sectional view of fig. 24 along the direction L1-L2, after forming the first isolation layer and the word line gate structure 220, a plurality of second isolation structures 470 are formed in the first substrate 200, and the first surface 203 exposes the second isolation structures 470.

The height P2 of the second isolation structure 470 is smaller than the height of the first isolation layer in a direction perpendicular to the first face 203.

Specifically, the height P2 of the second isolation structure 470 is smaller than the height H1 of the first dielectric layer 210.

The second isolation structures 470 are located between adjacent word line gate structures 220, and each second isolation structure 470 penetrates through 1 row of the first active regions 201 or 1 row of the second active regions 202 in the first direction X.

The second isolation structure 470 is used to separate adjacent second doped regions formed later, so as to insulate the adjacent second doped regions from each other.

In this embodiment, the bottom plane of the second isolation structure 470 in the direction towards the second face 204 is lower than half the height of the word line gate structure 220. Thus, leakage current between adjacent word line gate structures 220 is further reduced, and reliability of the semiconductor structure is improved.

In this embodiment, the method of forming the second isolation structure 470 includes: forming a second isolation structure mask layer (not shown) on the first surface 203, wherein the second isolation structure mask layer exposes a part of the surfaces of the first active regions 201, a part of the surfaces of the second active regions 202, and a part of the surfaces of the first isolation layers; etching the first substrate 200 from the first surface 203 by using the second isolation structure mask layer as a mask, and forming a plurality of second isolation openings (not shown) in the first substrate 200; forming a second isolation material layer (not shown) within the plurality of second isolation openings, on the first isolation layer surface and on the first face 203, the second isolation material layer surface being higher than the first isolation layer surface; the second spacer material layer is planarized until the first spacer surface and the first face 203 are exposed.

In this embodiment, the material of the second isolation structure 470 includes a dielectric material, and the dielectric material includes silicon oxide or a low-K material. The purpose of using low-K materials is to further reduce parasitic capacitance by low dielectric constant materials.

For ease of understanding, fig. 24 schematically shows: a first projection 2011 of 1 row of first active regions 201 and a second projection 2021 of 1 row of second active regions 202 adjacent in the second direction Y.

With continued reference to fig. 26, fig. 26 is consistent with the view direction of fig. 24, after forming the second isolation structures 470, second doped regions Q2 are formed at the first face 203 of each first active region 201 and each second active region 202.

In the second direction Y, the second doped regions Q2 are located on two sides of the second isolation structure 470, and in the direction perpendicular to the first surface 203, the depth of the second doped regions Q2 is smaller than the height P2 of the second isolation structure 470 (as shown in fig. 25).

For ease of understanding, fig. 26 schematically shows: a first projection 2011 of 1 row of first active regions 201 and a second projection 2021 of 1 row of second active regions 202 adjacent in the second direction Y.

In this embodiment, the method for forming the second doped region Q2 includes: after forming the second isolation structure 470, an ion implantation process is performed on the first surface 203 to implant dopant ions into the first substrate 200, thereby forming the second doped region Q2. Wherein the doping ions comprise N-type ions or P-type ions, and the N-type ions comprise phosphorus ions, arsenic ions or antimony ions; the P-type ions include boron ions, boron fluoride ions, or indium ions.

Referring to fig. 27 and 28, fig. 27 is a schematic top view of fig. 28 along a direction M, fig. 28 is a schematic cross-sectional view of fig. 27 along a direction L1-L2, and a plurality of capacitor structures 480 are formed on the plurality of first active regions 201 and the plurality of second active regions 202.

Specifically, several capacitor structures 480 in this embodiment are located on the first surface 203.

In the present embodiment, every 2 capacitor structures 480 are located on the first face 203 of 1 first active region 201 or 1 second active region 202, and in the second direction Y, the 2 capacitor structures 480 are located on two sides of the second isolation structure 470 penetrating the 1 first active region 201 or 1 second active region 202, respectively. Specifically, each capacitor structure 480 is electrically connected to the second doped region Q2 of one of the two sides of the second isolation structure 470. Thereby, the storage capacity of the memory is further increased.

In this embodiment, the projection of the capacitor structure 480 on the first surface 203 at least partially coincides with the second doped region Q2.

The projection of the capacitor structure 480 on the first surface 203 at least partially coincides with the second doped region Q2, so that the capacitor structure 480 and the second doped region Q2 can be electrically connected, and thus, the freedom of the arrangement and the structural shape of the capacitor structure 480 is large, and the capacitor structure 480 can have a larger volume to increase the capacity of the memory.

In this embodiment, the capacitor structure 480 includes: a first electrode layer (not shown), a second electrode layer (not shown), and a dielectric layer (not shown) between the first electrode layer and the second electrode layer.

The shape of the dielectric layer includes: planar or "U" shaped.

In this embodiment, before forming the capacitor structure 480, a second conductive structure 481 is formed on the second doped region Q2 on each side of the second isolation structure 470 along the second direction Y.

The second conductive structure 481 is used to electrically connect the capacitor structure 480 and the second doped region Q2.

The process window size for forming the capacitance structure 480 can be increased by the second conductive structure 481. Specifically, the second conductive structure 481 has high structural flexibility in contact with the second doped region Q2. Meanwhile, by adjusting the structure of the second conductive structure 481, for example, offsetting the projection of the second conductive structure 481 on the first surface 203 relative to the projection of the second doped region Q2 on the first surface 203, or making the projection range of the second conductive structure 481 on the first surface 203 exceed the projection range of the second doped region Q2 on the first surface 203, the flexibility of the arrangement mode of the capacitor structure 480 and the limitation of the shape structure of the capacitor structure 480 can be further improved, so that the size of the process window for forming the capacitor structure 480 is increased. In addition, the risk of the capacitive structure 480 being disconnected from the second doped region Q2 is also reduced by the second conductive structure 481.

Specifically, in the present embodiment, the projection of the capacitor structure 480 on the first surface 203 overlaps with the projection of the second conductive structure 481 on the first surface 203. The capacitance structure 480 may be offset in any direction relative to the second conductive structure 481.

In this embodiment, the second conductive structure 481 is a conductive plug.

The materials of the second conductive structure 481 include: a metal or metal nitride; the metal comprises: a combination of one or more of copper, aluminum, tungsten, cobalt, nickel, and tantalum; the metal nitride includes one or more combinations of tantalum nitride and titanium nitride.

In this embodiment, the method for forming the second conductive structure 481 includes: forming a sixth dielectric layer 490 on the first side 203; forming a plurality of second conductive structure openings (not shown) in the sixth dielectric layer 490, wherein the second conductive structure openings expose at least a portion of the surface of the second doped region Q2; the second conductive structure opening is filled with the material of the second conductive structure 481.

In this embodiment, the material of the sixth dielectric layer 490 includes a dielectric material including silicon oxide or a low-K material. The purpose of using low-K materials is to further reduce parasitic capacitance by low dielectric constant materials.

In this embodiment, after the capacitor structures 480 are formed, a conductive layer 482 is formed between the capacitor structures 480, and the surface of the conductive layer 482 is higher than the surface of the capacitor structures 480. The material of the conductive layer 482 includes a material having good conductivity and good filling ability such as SiG and tungsten.

For ease of understanding, the conductive layer 482 is not shown in fig. 27.

Referring to fig. 29 and 30, fig. 29 is a schematic top view of fig. 30 along the direction N, and fig. 30 is a schematic cross-sectional view of fig. 29 along the direction L3-L4, wherein a second substrate 500 is provided.

In this embodiment, the second substrate 500 has a logic circuit (not shown) therein.

In other embodiments, the second substrate has no logic circuitry therein.

With continued reference to fig. 29 and 30, after the conductive layer 482 is formed, the first substrate 200 and the second substrate 500 are bonded with the first face 203 facing the surface of the second substrate 500.

The logic circuits are electrically connected to the word line gate structure 220 and the subsequently formed bit line structure, respectively.

Through the logic circuit, voltages can be applied to the word line gate structure 220 and the bit line structure, respectively, to control writing and reading of the memory.

With continued reference to fig. 29 and 30, after bonding the first substrate 200 and the second substrate 300, the first substrate 200 is planarized from the second surface 204 of the first substrate 200 until the bottom surface of the first isolation layer is exposed.

Referring to fig. 31, in fig. 31, the view direction is consistent with that of fig. 29, and after the first substrate 200 is planarized from the second surface 204 of the first substrate 200, a first doped region Q1 is formed on the second surface 204 of each of the first active regions 201 and each of the second active regions 202.

In this embodiment, the method for forming the first doped region Q1 includes: after the first substrate 200 is planarized from the second surface 204 of the first substrate 200, an ion implantation process is performed on the second surface 204 to implant dopant ions into the first substrate 200 to form the first doped region Q1. Wherein the doping ions comprise N-type ions or P-type ions, and the N-type ions comprise phosphorus ions, arsenic ions or antimony ions; the P-type ions include boron ions, boron fluoride ions, or indium ions.

Referring to fig. 32 and 33, fig. 32 is a schematic top view of fig. 33 along a direction N, fig. 33 is a schematic cross-sectional view of fig. 32 along a direction L3-L4, after forming the first doped region Q1, a plurality of bit line structures 450 are formed, each bit line structure 450 is located on 1 first active area group I (as shown in fig. 2) or 1 second active area group II (as shown in fig. 2), and the capacitor structures 480 and the bit line structures 450 are respectively located on two opposite surfaces of the first substrate 200.

On the one hand, since the bit line structure 450 and the capacitor structure 480 are formed on the two opposite surfaces of the first substrate 200, and the word line grating structure 220 is formed in the first isolation layer and the first substrate 200, the positions of the capacitor structure 480, the word line grating structure 220 and the bit line structure 450 do not need to be mutually avoided, so that the wiring mode of the word line grating structure 220 and the bit line structure 450 can be simplified, the freedom degree of the arrangement position of the capacitor structure 480 is improved, and the difficulty of the manufacturing process is reduced.

On the other hand, by the shapes of the first projections 2011 and the second projections 2021 and the arrangement manner of the plurality of first active regions 201 and the plurality of second active regions 202, the plurality of first active regions 201 and the plurality of second active regions 202 can be distributed in the first substrate 200 in a uniform grid form, and thus, in the planarization process (as shown in fig. 29 and 30) of planarizing the first substrate 200 from the second surface 204 of the first substrate 200, the stop positions of the respective regions of the first substrate 200 can be close to or the same as each other, thereby being beneficial to making uniformity of characteristics of the respective regions of the semiconductor structure good.

Specifically, the bit line structure 450 is located on the second side 204. Also, in the second direction Y, each bit line structure 450 is electrically connected to the 1-column first active region 201 or the 1-column first doped region Q1 of the second active region 202.

In this embodiment, the maximum spacing T3 (shown in fig. 10) between the edges of each first projection 2011 in the first direction X is greater than WM (shown in fig. 32), which is the line width of the bit line structure 450 in the first direction X. Therefore, the short circuit risk between adjacent bit line structures is reduced, and the reliability of the semiconductor structure is improved.

In this embodiment, the method of forming the bit line structures 450 includes: forming a fourth dielectric layer 460 on the second side 204; forming a second mask layer (not shown) on the surface of the fourth dielectric layer 460, where the second mask layer exposes a portion of the surface of the fourth dielectric layer 460; etching the fourth dielectric layer 460 by using the second mask layer as a mask until the surface of the first doped region Q1 is exposed, and forming a plurality of bit line openings (not shown) in the fourth dielectric layer 460; forming a bit line material layer (not shown) within the bit line opening and on a surface of the fourth dielectric layer 460, the bit line material layer surface being higher than the fourth dielectric layer 460 surface; the bit line material layer is planarized until the surface of the fourth dielectric layer 460 is exposed.

In this embodiment, the process of forming the fourth dielectric layer 460 includes: at least one of a chemical vapor deposition process, a flowable chemical vapor deposition process, a physical vapor deposition process, and a spin-on process.

In this embodiment, the material of the bit line structure 450 includes a metal including one or more of copper, aluminum, tungsten, cobalt, nickel, and tantalum.

In this embodiment, the material of the fourth dielectric layer 460 includes a dielectric material, which includes silicon oxide or a low-K material. The purpose of using low-K materials is to further reduce parasitic capacitance by low dielectric constant materials.

In other embodiments, a first conductive structure is formed on each first doped region prior to forming the bit line structure, the first conductive structure being used to electrically connect the bit line structure with the first doped regions of 1 first active set or 1 second active set. The first conductive structure is a conductive plug, and the material of the first conductive structure comprises a metal or silicon, wherein the metal comprises one or a combination of a plurality of copper, aluminum, tungsten, cobalt, nickel and tantalum.

Accordingly, another embodiment of the present invention further provides a semiconductor structure formed by the above method, please continue to refer to fig. 32 and 33, which includes:

a number of bit line structures 450, each bit line structure 450 being located on 1 first active granule I or 1 second active granule II;

A plurality of capacitor structures 480 located on the plurality of first active regions 201 and the plurality of second active regions 202, and the capacitor structures 480 and the bit line structures 450 are located on opposite surfaces of the first substrate 200, respectively.

On the one hand, since the bit line structure 450 and the capacitor structure 480 are respectively located on two opposite surfaces of the first substrate 200, and at the same time, the word line gate structure 220 is located in the first isolation layer and the first substrate 200, the wiring of the semiconductor structure is simpler, and the space between the bit line structure 450 and the capacitor structure 480 is larger, so that parasitic capacitance generated by the wiring, parasitic capacitance generated between the bit line structure 450 and the capacitor structure 480, and the like are reduced, and thus, the difficulty in manufacturing the capacitor of the memory is reduced.

Specifically, the first substrate 200 includes a first surface 203 and a second surface 204 opposite to each other, a plurality of capacitor structures 480 are disposed on the first surface 203, a bit line structure 450 is disposed on the second surface 204, and the second surface 204 exposes a bottom surface of the first isolation layer.

For a specific explanation of the first substrate 200, the word line gate structure 220, and the first isolation layer in this embodiment, refer to the explanation in the embodiment shown in fig. 2 to 23, and the description is omitted here.

The shape of the dielectric layer includes: planar or "U" shaped.

In this embodiment, the semiconductor structure further includes: a plurality of second isolation structures 470 are located within the first substrate 200, the first face 203 exposes the second isolation structures 470, the second isolation structures 470 are located between adjacent word line gate structures 220, and each second isolation structure 470 extends through 1 row of the first active regions 201 or 1 row of the second active regions 202 along the first direction X.

The height P2 (shown in fig. 25) of the second isolation structure 470 is smaller than the height of the first isolation layer in a direction perpendicular to the first face 203.

Specifically, the height P2 of the second isolation structure 470 is smaller than the height H1 of the first dielectric layer 210 (as shown in fig. 25).

The second isolation structures 470 are used to space adjacent second doped regions Q2 apart to insulate between the adjacent second doped regions Q2.

In the present embodiment, every 2 capacitor structures 480 are located on the first face 203 of 1 first active region 201 or 1 second active region 202, and in the second direction Y, the 2 capacitor structures 480 are located on two sides of the second isolation structure 470 penetrating the 1 first active region 201 or 1 second active region 202, respectively.

In this embodiment, the semiconductor structure further includes: and a second doped region Q2 located on the first surface 203 of each of the first active regions 201 and each of the second active regions 202, the second doped region Q2 being located on both sides of the second isolation structure 470 in the second direction Y.

In this embodiment, in the direction perpendicular to the first surface 203, the depth of the second doped region Q2 is smaller than the height P2 of the second isolation structure 470 (as shown in fig. 25), and each capacitor structure 480 is electrically connected to the second doped region Q2 on one of two sides of the second isolation structure 470.

The second doped region Q2 has doped ions therein. The doping ions comprise N-type ions or P-type ions, and the N-type ions comprise phosphorus ions, arsenic ions or antimony ions; the P-type ions include boron ions, boron fluoride ions, or indium ions.

In this embodiment, the semiconductor structure further includes: a second conductive structure 481 located on the second doped region Q2 on each side of the second isolation structure 470 in the second direction Y.

Specifically, the projection of the capacitor structure 480 on the first surface 203 coincides with the projection of the second conductive structure 481 on the first surface 203. The capacitance structure 480 may be offset in any direction relative to the second conductive structure 481.

In this embodiment, the second conductive structure 481 is a conductive plug.

In this embodiment, the semiconductor structure further includes: a sixth dielectric layer 490 is located between each second conductive structure 481.

In this embodiment, the material of the sixth dielectric layer 490 includes a dielectric material including silicon oxide or a low-K material.

In this embodiment, the semiconductor structure further includes: the conductive layer 482 between the capacitor structures 480 is located at a surface of the conductive layer 482 higher than the surface of the capacitor structures 480 in a direction from the second face 204 toward the first face 203. The material of the conductive layer 482 includes a material having good conductivity and good filling ability such as SiG and tungsten.

In this embodiment, the semiconductor structure further includes: the first doped regions Q1 on the second side 204 of each first active region 201 and each second active region 202, and each bit line structure 450 is electrically connected to the first doped regions Q1 of 1 column of the first active regions 201 or 1 column of the second active regions 202 in the second direction Y.

The first doped region Q1 has doped ions therein. The doping ions comprise N-type ions or P-type ions, and the N-type ions comprise phosphorus ions, arsenic ions or antimony ions; the P-type ions include boron ions, boron fluoride ions, or indium ions.

In this embodiment, the semiconductor structure further includes: a fourth dielectric layer 460 on the bottom surface of the first spacer layer and on the second side 204, and a bit line structure 450 is located within the fourth dielectric layer 460.

In other embodiments, the semiconductor structure further comprises: and the first conductive structure is positioned on each first doping region and is used for electrically connecting the bit line structure with the first doping region of 1 first active area group or 1 second active area group. The first conductive structure is a conductive plug, and the material of the first conductive structure comprises a metal or silicon, wherein the metal comprises one or a combination of a plurality of copper, aluminum, tungsten, cobalt, nickel and tantalum.

In this embodiment, the semiconductor structure further includes: a second substrate 500 bonded to the first substrate 200, the first face 203 facing the surface of the second substrate 500.

The logic circuit is electrically connected to the word line gate structure 220 and the bit line structure 450, respectively.

Through the logic circuit, voltages can be applied to the word line gate structure 220, the bit line structure 450, respectively, to control writing and reading of the memory.

In other embodiments, the second substrate has no logic circuitry therein.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims

1. A semiconductor structure, comprising:

The first substrate comprises a plurality of first active area groups and a plurality of second active area groups, the plurality of first active area groups and the plurality of second active area groups are arranged at intervals along a first direction, each first active area group comprises a plurality of first active area groups arranged along a second direction, each second active area group comprises a plurality of second active area groups arranged along the second direction, the first direction and the second direction are perpendicular to each other, the first active area has a first projection on the surface of the first substrate, the second active area has a second projection on the surface of the first substrate, the first projection and the second projection are diamond-shaped or elliptic, the central lines of the adjacent first projection and the adjacent second projection are not overlapped along the second direction, and when the first projection and the second projection are diamond-shaped, the diagonal line of the diamond-shaped is parallel to the first direction or the second direction;

A first isolation layer located between the first active regions and the second active regions;

The word line grating structures are located in the first substrate and the first isolation layer, extend along a first direction and are distributed along a second direction, and each word line grating structure penetrates through 1 row of first active areas and 1 row of second active areas adjacent to each other along the first direction;

A plurality of second isolation structures located in the first substrate, the second isolation structures having a height smaller than the height of the first isolation layer in a direction perpendicular to the surface of the first substrate, the second isolation structures being located between adjacent word line gate structures, and each second isolation structure penetrating through 1 row of the first active regions or 1 row of the second active regions in the first direction;

A plurality of bit line structures, each bit line structure located on 1 first active granule or 1 second active granule;

And the capacitor structures and the bit line structures are respectively positioned on two surfaces opposite to the first substrate.

2. The semiconductor structure of claim 1, wherein the first substrate comprises opposing first and second sides, the bit line structure is on the first side, the capacitor structure is on the second side, and the second side exposes a surface of the second isolation structure.

3. The semiconductor structure of claim 2, wherein the first doped regions are located on a first side of each first active region and each second active region, and wherein each bit line structure is electrically connected to 1 column of the first active regions or 1 column of the first doped regions of the second active regions in the second direction.

4. The semiconductor structure of claim 2, wherein a top plane of the second isolation structure in a direction toward the first face is higher than one half a height of the word line gate structure.

5. The semiconductor structure of claim 2, wherein each 2 capacitor structures are located on a second face of 1 first active region or 1 second active region among the plurality of capacitor structures, and wherein the 2 capacitor structures are located on both sides of a second isolation structure extending through the 1 first active region or 1 second active region, respectively, in the second direction.

6. The semiconductor structure of claim 5, wherein a second doped region located at a second face of each first active region and each second active region, in the second direction, the second doped regions being located on both sides of the second isolation structure, in a direction perpendicular to the second face, the second doped regions having a depth less than a height of the second isolation structure, and each capacitance structure being electrically connected to the second doped region on one of both sides of the second isolation structure.

7. The semiconductor structure of claim 6, wherein a projection of the capacitive structure on the second face at least partially coincides with the second doped region.

8. The semiconductor structure of claim 1, wherein the first substrate comprises opposing first and second sides, the capacitance structure is located on the first side, the bit line structure is located on the second side, and the first side exposes a surface of the second isolation structure.

9. The semiconductor structure of claim 8, wherein the first doped regions are located on the second side of each first active region and each second active region, and wherein each bit line structure is electrically connected to 1 column of the first active regions or 1 column of the first doped regions of the second active regions in the second direction.

10. The semiconductor structure of claim 8, wherein a bottom plane of the second isolation structure in a direction toward the second face is less than one half a height of the word line gate structure.

11. The semiconductor structure of claim 8, wherein each 2 of the capacitor structures are located on a first side of 1 first active region or 1 second active region, and wherein the 2 capacitor structures are located on both sides of a second isolation structure extending through the 1 first active region or 1 second active region, respectively, in the second direction.

12. The semiconductor structure of claim 11, wherein a second doped region located at a first side of each first active region and each second active region, the second doped region being located at both sides of the second isolation structure in the second direction, the second doped region having a depth less than a height of the second isolation structure in a direction perpendicular to the first side, and each capacitance structure being electrically connected to the second doped region at one of both sides of the second isolation structure.

13. The semiconductor structure of claim 12, wherein a projection of the capacitive structure on the first face at least partially coincides with the second doped region.

14. The semiconductor structure of claim 3 or 9, further comprising: a first conductive structure located on each of the first doped regions.

15. The semiconductor structure of claim 7 or 13, further comprising: and a second conductive structure positioned between each capacitor structure and the second doped region.

16. The semiconductor structure of claim 1, wherein a line connecting centers of adjacent first and second projections extends along a third direction, and wherein an included angle between the third direction and the second direction ranges from 15 degrees to 75 degrees.

17. The semiconductor structure of claim 1, wherein centers of adjacent first and second projections have a first spacing therebetween in a first direction, the first spacing being less than 2 times T1, the T1 being a maximum spacing between a center of a first projection and an edge of the first projection in the first direction.

18. The semiconductor structure of claim 1, wherein centers of adjacent first and second projections have a second spacing therebetween in a second direction, the second spacing being less than 2 times T2, the T2 being a maximum spacing between a center of the first projection and an edge of the first projection in the second direction.

19. A method of forming a semiconductor structure, comprising:

Providing a first substrate, wherein the first substrate comprises a plurality of first active area groups and a plurality of second active area groups, the plurality of first active area groups and the plurality of second active area groups are arranged at intervals along a first direction, each first active area group comprises a plurality of first active areas arranged along a second direction, each second active area group comprises a plurality of second active areas arranged along the second direction, the first direction and the second direction are perpendicular to each other, the first active areas have a first projection on the surface of the first substrate, the second active areas have a second projection on the surface of the first substrate, the first projection and the second projection are diamond-shaped or elliptic-shaped, the central lines of the adjacent first projections and second projections are not overlapped along the second direction, and when the first projection and the second projection are diamond-shaped, the diagonal line of the diamond-shaped is parallel to the first direction or the second direction;

Forming a first isolation layer and a plurality of mutually independent word line grating structures, wherein the first isolation layer is positioned between a plurality of first active areas and a plurality of second active areas, the word line grating structures are positioned in the first substrate and the first isolation layer, extend along a first direction and are distributed along a second direction, and each word line grating structure penetrates through 1 row of first active areas and 1 row of second active areas which are adjacent to each other along the second direction along the first direction;

Forming a plurality of second isolation structures in the first substrate, wherein the heights of the second isolation structures are smaller than those of the first isolation layers, the second isolation structures are positioned between adjacent word line grating structures, and each second isolation structure penetrates through 1 row of first active areas or 1 row of second active areas along the first direction;

after forming the first isolation layer and the word line gate structures, forming a plurality of bit line structures, each bit line structure being located on 1 first active area group or 1 second active area group;

after the first isolation layer and the word line gate structure are formed, a plurality of capacitor structures are formed on the first active regions and the second active regions, and the capacitor structures and the bit line structures are respectively located on two surfaces opposite to the first substrate.

20. The method of forming a semiconductor structure of claim 19, wherein the method of forming the first isolation layer and the plurality of word line gate structures comprises: forming a first dielectric layer between the first active areas and the second active areas; forming a plurality of first grooves in the first dielectric layer, the first active areas and the second active areas, wherein the first grooves extend along a first direction and are arranged along a second direction, the depth of each first groove is smaller than the height of the first dielectric layer, and the inner wall surface of each first groove exposes the first dielectric layer, and 1 row of first active areas and 1 row of second active areas which are adjacent to each other along the second direction; forming a plurality of word line grating structures in the plurality of first grooves; and forming a second dielectric layer on the top surface of the word line grating structure, wherein the first dielectric layer and the second dielectric layer form the first isolation layer.

21. The method of forming a semiconductor structure of claim 19, wherein the first substrate comprises opposing first and second sides in a direction perpendicular to a surface of the first substrate, the bit line structure being located on the first side and the capacitor structure being located on the second side.

22. The method of forming a semiconductor structure of claim 21, further comprising: after forming the first isolation layer and the word line gate structure, and before forming the bit line structure, a first doped region is formed on a first side of each first active region and each second active region.

23. The method of forming a semiconductor structure of claim 22, further comprising: providing a second substrate; after the bit line structure is formed, the first substrate and the second substrate are bonded, the first face facing a surface of the second substrate.

24. The method of forming a semiconductor structure of claim 23, further comprising: after bonding the first substrate and the second substrate, flattening the first substrate from the second surface of the first substrate until the bottom surface of the first isolation layer is exposed; and after the first substrate is flattened from the second surface of the first substrate, forming a plurality of second isolation structures in the first substrate, wherein the second surface is exposed out of the second isolation structures, and the height of the second isolation structures is smaller than that of the first isolation layers in the direction perpendicular to the second surface.

25. The method of forming a semiconductor structure of claim 24, further comprising: after forming the second isolation structures and before forming the capacitor structures, forming second doped regions on the second face of each first active region and each second active region, wherein the second doped regions are positioned on two sides of the second isolation structures in the second direction, and the depth of the second doped regions is smaller than the height of the second isolation structures in the direction perpendicular to the second face.

26. The method of forming a semiconductor structure of claim 19, wherein the first substrate comprises opposing first and second sides, the capacitor structure being located on the first side and the bit line structure being located on the second side.

27. The method of forming a semiconductor structure of claim 26, further comprising: after the first isolation layer and the word line gate structure are formed, and before the capacitor structure is formed, a plurality of second isolation structures are formed in the first substrate, the second isolation structures are exposed from the first surface, the height of the second isolation structures is smaller than that of the first isolation layers in the direction perpendicular to the first surface, the second isolation structures are located between adjacent word line gate structures, and each second isolation structure penetrates through 1 row of first active regions or 1 row of second active regions along the first direction.

28. The method of forming a semiconductor structure of claim 27, further comprising: after forming the second isolation structures and before forming the capacitor structures, forming second doped regions on the first surface of each first active region and the first surface of each second active region, wherein the second doped regions are positioned on two sides of the second isolation structures in the second direction, and the depth of the second doped regions is smaller than the height of the second isolation structures in the direction perpendicular to the first surface.

29. The method of forming a semiconductor structure of claim 28, further comprising: providing a second substrate; after forming the capacitor structure, bonding the first substrate and the second substrate, the first face facing a surface of the second substrate.

30. The method of forming a semiconductor structure of claim 29, further comprising: after bonding the first substrate and the second substrate, flattening the first substrate from the second surface of the first substrate until the bottom surface of the first isolation layer is exposed; after planarizing the first substrate from the second side of the first substrate and before forming the bit line structures, first doped regions are formed at the second side of each first active region and each second active region.

31. The method of forming a semiconductor structure of claim 22 or 30, further comprising: a first conductive structure is formed on each of the first doped regions prior to forming the bit line structures.

32. The method of forming a semiconductor structure of claim 25 or 28, further comprising: a second conductive structure is formed on the second doped region on each side of the second isolation structure in the second direction prior to forming the capacitor structure.