CN113517292A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN113517292A CN113517292A CN202110774725.6A CN202110774725A CN113517292A CN 113517292 A CN113517292 A CN 113517292A CN 202110774725 A CN202110774725 A CN 202110774725A CN 113517292 A CN113517292 A CN 113517292A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
- H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/05—Making the transistor
- H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/488—Word lines
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Abstract
A semiconductor structure and a method of forming the same, wherein the method comprises: thinning the substrate from the second side until the surface of the first isolation layer is exposed; forming second isolation layers in the active regions, wherein projections of the second isolation layers on the surface of the substrate are positioned between projections of adjacent word line gate structures on the surface of the substrate; forming a plurality of bit lines on the first surface, forming a plurality of capacitors on the thinned second surface, wherein the bit lines are parallel to the second direction, each bit line is electrically connected with a plurality of active regions, and each active region is electrically connected with two capacitors; or, form a plurality of bit lines on the thick second face of thinning form a plurality of electric capacity on the first face, the bit line is on a parallel with the second direction, and every bit line is connected with a plurality of active area electricity, every the active area is connected with two electric capacity electricity, has simplified the degree of difficulty of technology, has improved the level of integrating of chip.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
With the rapid development of technology, semiconductor memories are widely used in electronic devices. Dynamic Random Access Memory (DRAM), which is a volatile memory, is the most commonly utilized solution for applications that store large amounts of data.
The basic memory cell of the dynamic random access memory is composed of a memory transistor and a memory capacitor, and the memory array is composed of a plurality of memory cells. The storage capacitor is used for storing charges representing stored information, the storage transistor is a switch for controlling the charge flowing in and discharging of the storage capacitor, and the storage transistor is also connected with an internal circuit in storage and receives a control signal of the internal circuit. The storage transistor is formed with a source region, a drain region and a gate electrode, the gate electrode is used for controlling current flowing between the source region and the drain region and is connected to a word line, the drain region is used for forming a bit line contact region and is connected to the bit line source region and is used for forming a storage node contact region and is connected to a storage capacitor. With the continuous development of integrated circuit manufacturing technology, the device density of the memory chip needs to be further increased to obtain larger data storage capacity.
In summary, the conventional dram has yet to be improved.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, which can improve the performance of a memory.
To solve the above technical problem, an aspect of the present invention provides a semiconductor structure, including: the substrate is provided with a first surface and a second surface which are opposite, the substrate comprises a plurality of active regions and first isolation layers which are arrayed along a first direction and a second direction, the first isolation layers are positioned between adjacent active regions, an acute included angle is formed between the second direction and the first direction, the projection pattern of each active region on the first surface or the second surface is rectangular, and the long side direction of the rectangle is perpendicular to the first direction; the first grooves extend from the first surface to the second surface and are arranged in parallel along a third direction, the third direction is perpendicular to the first direction, each first groove is positioned between two adjacent rows of active regions, two sides of each first groove along the third direction penetrate through the active regions, and the side walls and the bottoms of the first grooves expose partial surfaces of the active regions; the word line grid structure is positioned in the first groove; the projections of the second isolation layers on the surface of the substrate are positioned between the projections of the adjacent word line gate structures on the surface of the substrate; the bit lines are parallel to the second direction, each bit line is electrically connected with a group of the active regions, and each active region is electrically connected with two capacitors; or, the bit lines are positioned on the second surface and the plurality of capacitors are positioned on the first surface, the bit lines are electrically connected with the active regions, the bit lines are parallel to the second direction and are arranged along the first direction, and each active region is electrically connected with two capacitors.
Optionally, the bit lines are located on a first surface, the capacitors are located on a second surface, and the method further includes: the second isolation layers are positioned in the second grooves, the second grooves extend from the second face to the first face, the second grooves are arranged along a third direction, the third direction is perpendicular to the first direction, the second grooves penetrate through the active regions along the first direction, the projections of the second grooves on the surface of the substrate are positioned between the projections of adjacent word line gate structures on the surface of the substrate, and the size of the second grooves along the normal direction of the surface of the substrate is smaller than that of the first isolation layers along the normal direction of the surface of the substrate; and the first source-drain regions are positioned in the active regions on two sides of the second isolation layer, and one capacitor is electrically connected with one first source-drain region.
Optionally, the bit line is located on the second surface, and the plurality of capacitors are located on the first surface, further including: the second isolation layer is positioned in the second groove, the second groove extends from the first surface to the second surface, the second grooves are arranged along a third direction, the third direction is perpendicular to the first direction, the second groove penetrates through the active regions along the first direction, the projection of the second groove on the surface of the substrate is positioned between the projections of adjacent word line gate structures on the surface of the substrate, and the size of the second groove in the normal direction of the surface of the substrate is smaller than that of the first isolation layer in the normal direction of the surface of the substrate; and the first source drain regions are positioned in the active regions at two sides of the second isolation layer, extend from the first surface to the second surface, and one capacitor is electrically connected with one first source drain region.
Correspondingly, the technical scheme of the invention also provides a forming method for forming the semiconductor structure, which comprises the following steps: providing a substrate, wherein the substrate is provided with a first surface and a second surface which are opposite, the substrate comprises a plurality of active regions and first isolation layers which are arranged along a first direction and a second direction, the first isolation layers are positioned between adjacent active regions, an acute included angle is formed between the second direction and the first direction, the projection pattern of each active region on the first surface or the second surface is rectangular, and the long side direction of the rectangle is perpendicular to the first direction; forming a plurality of first grooves in the substrate, wherein the first grooves extend from a first surface to a second surface, the first grooves are arranged in parallel along a third direction, the third direction is perpendicular to the first direction, each first groove is positioned between two adjacent rows of active regions, two sides of each first groove along the third direction penetrate through the active regions, and the side walls and the bottoms of the first grooves expose partial surfaces of the active regions; forming a word line gate structure in the first groove; thinning the substrate from the second side until the surface of the first isolation layer is exposed; forming second isolation layers in the active regions, wherein projections of the second isolation layers on the surface of the substrate are positioned between projections of adjacent word line gate structures on the surface of the substrate; forming a plurality of bit lines on the first surface, forming a plurality of capacitors on the thinned second surface, wherein the bit lines are parallel to the second direction, each bit line is electrically connected with a plurality of active regions, and each active region is electrically connected with two capacitors; or forming a plurality of bit lines on the thinned second surface, forming a plurality of capacitors on the first surface, wherein the bit lines are parallel to the second direction, each bit line is electrically connected with a plurality of active regions, and each active region is electrically connected with two capacitors.
Optionally, the bit lines are located on the first surface, and the capacitors are located on the second surface; the method for forming the second isolation layer comprises the following steps: after the thinning treatment, before the capacitors are formed, a plurality of second grooves are formed in the substrate, the second grooves extend from the second surface to the first surface, the second grooves are arranged along a third direction, the third direction is perpendicular to the first direction, the second grooves penetrate through the active regions along the first direction, the projections of the second grooves on the surface of the substrate are located between the projections of adjacent word line gate structures on the surface of the substrate, and the size of the second grooves in the normal direction of the surface of the substrate is smaller than that of the first isolation layer in the normal direction of the surface of the substrate; and forming a second isolation layer in the second groove.
Optionally, after forming the second isolation layer and before forming the plurality of capacitors, the method further includes: and injecting first doping ions into the active region from the second surface to form a first source drain region in the active region.
Optionally, the forming method of the plurality of capacitors includes: after the first source drain region is formed, forming a first dielectric layer on the second surface and the first source drain region; forming a plurality of third grooves in the first dielectric layer, wherein the third grooves expose the surface of the first source drain region; and forming a plurality of capacitors in the third groove, wherein one capacitor is electrically connected with one first source drain region.
Optionally, a capacitor plug is further disposed between the capacitor and the first source drain region; the forming method of the capacitor plug comprises the following steps: a first opening is further formed in the third groove, and the first opening exposes the surface of the first source drain region; and forming the capacitor plug in the first opening.
Optionally, the bit line is located on the first surface, and the method for forming the bit line includes: forming a second dielectric layer on the first surface; forming a plurality of fourth grooves in the second dielectric layer, wherein the fourth grooves extend along the second direction, and one fourth groove exposes partial surfaces of the active regions; and forming the bit line in the fourth groove.
Optionally, after forming the word line gate structure and before forming the bit line, the method further includes: and injecting second doping ions into the active region from the first surface to form a second source drain region in the active region.
Optionally, a bit line plug is further provided between the bit line and the active region, and a projection of the bit line plug on the substrate surface is located between projections of adjacent word line gate structures on the substrate surface; the bit line plug forming method comprises the following steps: a second opening is further formed in the fourth groove, and the second source drain region is exposed out of the second opening; and forming the bit line plug in the second opening.
Optionally, the capacitors are located on the first surface; the method for forming the second isolation layer comprises the following steps: forming a plurality of second grooves in the substrate, wherein the second grooves extend from the first surface to the second surface, the second grooves are arranged along a third direction, the third direction is perpendicular to the first direction, the second grooves penetrate through the active regions along the first direction, the projections of the second grooves on the surface of the substrate are positioned between the projections of adjacent word line gate structures on the surface of the substrate, and the size of the second grooves along the normal direction of the surface of the substrate is smaller than that of the first isolation layer along the normal direction of the surface of the substrate; and forming a second isolation layer in the second groove.
Optionally, after forming the second isolation layer and before forming the plurality of capacitors, the method further includes: and injecting first doping ions into the active region from the first surface to form a first source drain region in the active region.
Optionally, the forming method of the plurality of capacitors includes: after the first source drain region is formed, forming a first dielectric layer on the first surface and the first source drain region; forming a plurality of third grooves in the first dielectric layer, wherein the third grooves expose the surface of the first source drain region; and forming the capacitors in the third groove, wherein one capacitor is electrically connected with one first source drain region.
Optionally, a capacitor plug is further disposed between the capacitor and the first source-drain region, and a forming method of the capacitor plug includes: a first opening is further formed in the third groove, and the first opening exposes the surface of the first source drain region; and forming the capacitor plug in the first opening.
Optionally, the bit line is located on the second surface, and the method for forming the bit line includes: after the thinning treatment, forming a second dielectric layer on the second surface; forming a plurality of fourth grooves in the second dielectric layer, wherein the fourth grooves extend along the second direction, and one fourth groove exposes partial surfaces of the active regions; and forming the bit line in the fourth groove.
Optionally, after forming the word line gate structure and before forming the bit line, the method further includes: and injecting second doping ions into the active region from the second surface to form a second source drain region in the active region.
Optionally, a bit line plug is further provided between the bit line and the active region, and a projection of the bit line plug on the substrate surface is located between projections of adjacent word line gate structures on the substrate surface; the bit line plug forming method comprises the following steps: a second opening is further formed in the fourth groove, and the second source drain region is exposed out of the second opening; and forming the bit line plug in the second opening.
Optionally, an angle between the second direction and the first direction is in a range from 15 degrees to 75 degrees.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
the technical scheme of the invention providesIn the forming method of the semiconductor structure, a plurality of bit lines are formed on the first surface, a plurality of capacitors are formed on the thinned second surface, the bit lines are parallel to the second direction, each bit line is electrically connected with a group of a plurality of active regions, and each active region is electrically connected with two capacitors; or, forming a plurality of bit lines on the second surface with reduced thickness, forming a plurality of capacitors on the first surface, wherein the bit lines are parallel to the second direction, each bit line is electrically connected with a plurality of active regions, each active region is electrically connected with two capacitors, and the capacitors and the bit lines do not need special alignment process in the forming process, thereby simplifying the process difficulty, and meanwhile, from the memory cell array, the bit lines and the capacitors are respectively positioned at two sides of the active region, and the unit memory cell is 4F2The structure of (2) occupies a small area, and improves the integration level of the chip.
In the semiconductor structure provided by the technical scheme of the invention, a plurality of bit lines are positioned on a first surface, and a plurality of capacitors are positioned on a second surface, wherein the bit lines are parallel to the second direction, each bit line is electrically connected with a group of a plurality of active regions, and each active region is electrically connected with two capacitors; or, the bit lines are positioned on the second surface and the plurality of capacitors are positioned on the first surface, the bit lines are electrically connected with the active regions, the bit lines are parallel to the second direction and are arranged along the first direction, and each active region is electrically connected with two capacitors. The bit line and the capacitor are respectively arranged at two sides of the active region, and the unit memory cell is 4F2The memory cell array occupies a small area, and the integration level of the chip is improved.
Drawings
FIG. 1 is a schematic diagram of a semiconductor structure in one embodiment;
fig. 2 to 15 are schematic structural views of steps in a method for forming a semiconductor structure according to an embodiment of the present invention;
fig. 16 to 21 are schematic structural views of steps in a method for forming a semiconductor structure according to another embodiment of the present invention.
Detailed Description
It should be noted that "surface" and "upper" in the present specification are used to describe a relative positional relationship in space, and are not limited to direct contact or not.
As described in the background, the existing dynamic random access memory has yet to be improved. The analysis will now be described with reference to specific examples.
FIG. 1 is a schematic diagram of a semiconductor structure according to an embodiment.
Please refer to fig. 1, which includes: a substrate 100; a word line gate structure 101 located within the substrate 100; a source doped region 103 and a drain doped region 102 in the substrate 100 at two sides of the word line gate structure 101; a bit line structure 105 electrically connected to the source doped region 103 through the source plug 104; and a capacitor structure 107 electrically connected to the drain doped region 102 through the capacitor plug 106.
The forming process of the semiconductor structure comprises the following steps: the source doping region 103 and the drain doping region 102 are formed, the word line gate structure 101 is formed in the substrate 100, the source plug 104 and the bit line structure 105 are formed, the capacitor plug 106 is formed, and the capacitor structure 107 is formed. The channel of the semiconductor structure is U-shaped, and the source doped region 103 and the drain doped region 102 are on the horizontal sides of the word line gate structure 101. The bit line structure 105 and the capacitor structure 107 are on the same side of the transistor and are located above the substrate in the fabrication process. The capacitor plug 106 of the capacitor structure 107 needs to pass through the bit line structure 105, so that the overall process complexity is high, the requirements on the photolithography process and the alignment degree are extremely high, and meanwhile, from the viewpoint of the memory cell array, the unit memory cell is 6F2The structure of (2) occupies a large area, and is not beneficial to the integrated development of the chip.
In order to solve the above technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, in which a bit line is formed on the first surface or the thinned second surface, the bit line extends along the second direction, and the bit line is electrically interconnected with the active region; forming a plurality of capacitors on the thinned second surface or the first surface, wherein the capacitors and the bit lines are positioned on two opposite surfaces of the substrate, and the capacitors and the bit lines are not formed in the forming processSpecial alignment process is required, thereby simplifying the process, and simultaneously, the bit line and the capacitor are respectively positioned at two sides of the active area from the view point of the memory cell array, and the unit memory cell is 4F2The structure of (2) occupies a small area, and improves the integration level of the chip.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 2 to fig. 15 are schematic structural diagrams of steps in a method for forming a semiconductor structure according to an embodiment of the invention.
Referring to fig. 2 and fig. 3, fig. 2 is a schematic top view structure diagram of fig. 3, fig. 3 is a schematic cross-sectional structure diagram along the direction DD1 in fig. 2, providing a substrate 201, where the substrate 201 has a first face 201a and a second face 201b opposite to each other, the substrate 201 includes a plurality of active regions 202 and first isolation layers 203 arranged along a first direction X and a second direction Y, the first isolation layers 203 are located between adjacent active regions 202, the second direction Y forms an acute included angle with the first direction X, a projection pattern of each active region 202 on the first face 201a or the second face 201b is a rectangle, and a long side direction of the rectangle is perpendicular to the first direction X.
The angle between the second direction Y and the first direction X ranges from 15 degrees to 75 degrees.
In this embodiment, the substrate 201 is made of silicon. In other embodiments, the substrate 201 material includes silicon carbide, silicon germanium, a multi-component semiconductor material of group iii-v elements, silicon-on-insulator (SOI), or germanium-on-insulator. The multielement semiconductor material formed by III-V group elements comprises InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.
Referring to fig. 4 and 5, fig. 4 is a schematic top view structure diagram of fig. 5, fig. 5 is a schematic cross-sectional structure diagram along EE1 direction in fig. 4, a plurality of first grooves 204 are formed in the substrate 201, the first grooves 204 extend from the first surface 201a to the second surface 201b, the plurality of first grooves 204 are arranged in parallel along a third direction Z, the third direction Z is perpendicular to the first direction X, each first groove 204 is located between two adjacent rows of active regions 202, two sides of the first grooves 204 along the third direction Z further penetrate through a plurality of active regions 202, and sidewalls and bottoms of the first grooves 204 expose a portion of the surfaces of the active regions 202.
The forming process of the first groove 204 includes one or a combination of a dry etching process and a wet etching process. In this embodiment, the forming process of the first groove 204 is a dry etching process. The dry etching process is beneficial to forming a better groove shape.
Referring to fig. 6 and 7, fig. 6 is a schematic top view of fig. 7, and fig. 7 is a schematic cross-sectional view taken along EE1 in fig. 6, wherein a word line gate structure 205 is formed in the first trench 204.
The method for forming the word line gate structure 205 includes: forming a gate dielectric material layer (not shown) on the surface of the sidewall and the bottom of the first groove 204 and the surface of the first face 201 a; forming a gate material layer (not shown) on the gate dielectric material layer; flattening the gate material layer and the gate dielectric material layer until the surface of the first surface 201 is exposed to form an initial word line gate structure; and etching back the initial word line gate structure until part of the side wall of the first groove 204 is exposed to form the word line gate structure 205.
The material of the gate material layer comprises metal or silicon; the material of the gate dielectric material layer comprises oxide. In this embodiment, the gate material layer is made of tungsten; the gate dielectric material layer is made of hafnium oxide.
The top surface of the word line gate structure 205 in the direction toward the first surface 201a of the substrate is lower than the surface of the first surface 201a of the active region 202, so as to provide a physical space for forming a first source drain region on the first surface 201a of the active region 202 in the following step.
In this embodiment, the top surface of the word line gate structure 205 in the direction toward the first side 201a is lower than the substrate first side 201a surface. In another embodiment, the top surface of the word line gate structure 205 in a direction toward the first side 201a is higher than the substrate first side 201a surface.
In this embodiment, the method for forming the word line gate structure 205 includes: forming a word line gate material layer on the surface of the first face 201a in the first groove 204; planarizing the word line gate material layer until the first face 201a is exposed; after the planarization process, the word line gate material layer is etched back to form the word line gate structure 205.
In this embodiment, after the word line gate structure 205 is formed, an insulating layer 206 is further formed in the first groove 204, and a surface of the insulating layer 206 is flush with the first surface 201 a.
In this embodiment, subsequently, second isolation layers in the active regions 202 are formed, and projections of the second isolation layers on the surface of the substrate 201 are located between projections of the adjacent word line gate structures 205 on the surface of the substrate 201; thinning the substrate 201 from the second side 201b until the surface of the first isolation layer 203 is exposed; forming a plurality of bit lines on the first surface 201a, forming a plurality of capacitors on the thinned second surface 201b, wherein the bit lines are parallel to the second direction Y, each bit line is electrically connected with a plurality of active regions 202, and each active region 202 is electrically connected with two capacitors. The second isolation layer, the bit line, and the capacitors are formed as shown in fig. 8 to 15.
In another embodiment, subsequently, forming second isolation layers in the active regions, wherein projections of the second isolation layers on the surface of the substrate are located between projections of the adjacent word line gate structures on the surface of the substrate; thinning the substrate from the second side until the surface of the first isolation layer is exposed; and forming a plurality of bit lines on the thinned second surface, forming a plurality of capacitors on the first surface, wherein the bit lines are parallel to the second direction, each bit line is electrically connected with the active regions, and each active region is electrically connected with two capacitors.
Referring to fig. 8 and 9, fig. 8 is a schematic top view of fig. 9, fig. 9 is a schematic cross-sectional view taken along EE1 direction of fig. 8, forming a second isolation layer 207 in each active region 202, wherein a projection of the second isolation layer 207 on the surface of the substrate 201 is located between projections of the adjacent word line gate structures 205 on the surface of the substrate 200.
In this embodiment, the method for forming the second isolation layer 207 includes: forming a plurality of second grooves (not labeled) in the substrate 201, the second grooves extending from the first surface 201a to the second surface 201b, the plurality of second grooves being arranged along a third direction Z, the third direction Z being perpendicular to the first direction X, and the plurality of second grooves penetrating through the plurality of active regions 202 along the first direction X, projections of the second grooves on the surface of the substrate 201 being located between projections of adjacent word line gate structures 205 on the surface of the substrate 201, and a dimension of the second grooves along a normal direction of the surface of the substrate 201 being smaller than a dimension of the first isolation layer 203 along the normal direction of the surface of the substrate 201; a second isolation layer 207 is formed within the second recess.
After forming the second isolation layer 207 and before forming the plurality of capacitors, the method further includes: first doping ions are implanted into the active region 202 from the first surface 201, and a first source drain region 208 is formed in the active region 202.
The first doping ions comprise N-type ions or P-type ions. In this embodiment, the first doping ions are N-type ions.
In this embodiment, after the first source-drain regions 208 are formed, the plurality of capacitors are formed, and please refer to fig. 10 and fig. 11 for a method for forming the plurality of capacitors.
Referring to fig. 10 and fig. 11, fig. 10 is a schematic top view structure diagram of fig. 11, fig. 11 is a schematic cross-sectional structure diagram along EE1 direction in fig. 10, and after forming the first source/drain region 208, a first dielectric layer 209 is formed on the first surface 201a and the first source/drain region 208; forming a plurality of third grooves (not labeled in the figure) in the first dielectric layer 209, where the surfaces of the first source drain regions 208 are exposed by the third grooves; the capacitors 210 are formed in the third groove, and one capacitor 210 is electrically connected to one first source drain region 208.
The capacitor 210 includes: a first electrode layer (not shown), a second electrode layer (not shown), and a dielectric layer (not shown) between the first electrode layer and the second electrode layer.
The shape of the dielectric layer includes: planar or "U" shaped.
When the shape of the dielectric layer is planar, the surface of the first electrode layer is flat, and the surface of the second electrode layer is flat.
When the dielectric layer is in a U shape, the surface of the first electrode layer is an uneven surface, and the surface of the second electrode layer is an uneven surface; or the surface of the first electrode layer is flat, and the surface of the second electrode layer is flat.
The material of the first electrode layer includes: a metal or metal nitride; the material of the second electrode layer includes: a metal or metal nitride; the metal includes: combinations of one or more of copper, aluminum, tungsten, cobalt, nickel, and tantalum; the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride.
In this embodiment, a capacitor plug 211 is further disposed between the capacitor 210 and the first source drain region 208; the method for forming the capacitor plug 211 comprises the following steps: a first opening (not shown) is further formed in the third groove, and the first opening exposes the surface of the first source drain region 208; the capacitor plug 211 is formed in the first opening. In other embodiments, the capacitor may be in direct contact with the first source drain region without forming the capacitor plug.
The material of the capacitor plug 211 includes: a metal or metal nitride; the metal includes: combinations of one or more of copper, aluminum, tungsten, cobalt, nickel, and tantalum; the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride.
Referring to fig. 12 and 13, fig. 12 is a schematic top view of fig. 13, and fig. 13 is a schematic cross-sectional view taken along FF1 of fig. 12, wherein the substrate 201 is thinned from the second side 201b until the surface of the first isolation layer 203 is exposed.
Specifically, in this embodiment, after the capacitor 210 is formed, the substrate 201 is thinned from the second surface 201 b.
In this embodiment, the thinning processing method includes: providing a substrate 300; bonding the surface of the substrate 300 with the surface of a second dielectric layer 209; and turning over the base 300 and the substrate 201 to thin the second surface 201b of the substrate 201.
The thinning treatment process comprises a mechanical chemical grinding process.
Referring to fig. 14 and 15, fig. 14 is a schematic top view of fig. 15 without the second dielectric layer, fig. 15 is a schematic cross-sectional view along FF1 of fig. 14, and a plurality of bit lines 212 are formed on the thinned second surface 201 b.
The bit line 212 is located on the second surface 201b, and the method for forming the bit line 212 includes: after the thinning treatment, a second dielectric layer 213 is formed on the second surface 201 b; forming a plurality of fourth grooves (not labeled in the figure) in the second dielectric layer 213, where the fourth grooves extend along the second direction Y, and one fourth groove exposes a part of the surfaces of the plurality of active regions 202; the bit lines 212 are formed within the fourth recesses.
The bit lines 212 extend in the second direction Y and the word lines 205 extend in the first direction X, with an angle between the bit lines 212 and the word lines 205. Therefore, the distance between adjacent bit lines 212 is increased and the parasitic capacitance between the bit lines 212 is reduced for the same chip unit area, thereby improving the performance of the device.
The material of the bit line 212 includes a metal. In this embodiment, the metal is copper. In other embodiments, the metal may be aluminum, tungsten, or the like.
In this embodiment, after forming the word line 205 and before forming the bit line 212, the method further includes: second doping ions are implanted into the active region 202 from the second surface 201b, and a second source-drain region 214 is formed in the active region 202. Specifically, after the thinning process, the second source drain region 214 is formed.
The second doping ions comprise N-type ions or P-type ions. In this embodiment, the second doping ions are N-type ions.
A channel is formed between the first source-drain region 208 and the second source-drain region 214, and the channel is a vertical channel, which is beneficial to improving the density of the device and increasing the integration level of the device.
In this embodiment, the bit line 212 directly contacts the second source/drain region 214. In other embodiments, a bit line plug is further disposed between the bit line 212 and the active region 202. Specifically, a bit line plug is further arranged between the bit line 212 and the second source drain region 214, and a projection of the bit line plug on the surface of the substrate 201 is located between projections of adjacent word line gate structures on the surface of the substrate 201.
To this end, in the formed semiconductor structure, the capacitors 210 and the bit lines 212 do not need a special alignment process in the formation process, thereby simplifying the difficulty of the process; meanwhile, from the memory cell array, the unit memory cell is 4F2The structure of (2) occupies a small area, and improves the integration level of the chip.
Accordingly, an embodiment of the present invention further provides a semiconductor structure formed by the above method, with reference to fig. 14 and fig. 15, including: a substrate 201, where the substrate 201 has a first surface 201a and a second surface 201b opposite to each other, the substrate 201 includes a plurality of active regions 202 and first isolation layers 203 arranged in an array along a first direction X and a second direction Y, the first isolation layers 203 are located between adjacent active regions 202, the second direction Y forms an acute included angle with the first direction X, a projection pattern of each active region 202 on the first surface 201a or the second surface 201b is a rectangle, and a long side direction of the rectangle is perpendicular to the first direction X; a plurality of first grooves (not labeled in the figure) located in the substrate 201, the first grooves extending from the first surface 201a to the second surface 201b, the plurality of first grooves being arranged in parallel along a third direction Z, the third direction Z being perpendicular to the first direction X, each first groove being located between two adjacent rows of active regions 202, two sides of the first groove along the third direction Z further penetrating through the plurality of active regions 202, and sidewalls and bottoms of the first grooves exposing a portion of surfaces of the active regions 202; a word line gate structure 205 located within the first recess; a second isolation layer 207 located in each active region 202, a projection of the second isolation layer 207 on the surface of the substrate 201 being located between projections of the adjacent word line gate structures 205 on the surface of the substrate 201; a bit line 212 located on the second side 201b and a plurality of capacitors 210 located on the first side 201a, wherein the bit line 212 is electrically connected to the active regions 202, the bit line 212 is parallel to the second direction Y and arranged along the first direction X, and each of the active regions 202 is electrically connected to two capacitors 210.
In the semiconductor structure, the bit line 212 and the capacitors 210 are respectively located at two sides of the active region from the view point of the memory cell array, and the unit memory cell is 4F2The structure of (2) occupies a small area, and improves the integration level of the chip.
The bit lines 212 are located on the second surface 201b, and the capacitors 210 are located on the first surface 201a, further including: a plurality of second grooves (not labeled) in the substrate 201, wherein the second isolation layer 207 is located in the second grooves, the second grooves extend from the first surface 201a to the second surface 201b, the plurality of second grooves are arranged along a third direction Z, the third direction Z is perpendicular to the first direction X, the second grooves penetrate through the plurality of active regions 202 along the first direction X, projections of the second grooves on the surface of the substrate 201 are located between projections of adjacent word line gate structures 205 on the surface of the substrate 201, and a dimension of the second grooves along a normal direction of the surface of the substrate 201 is smaller than a dimension of the first isolation layer 203 along the normal direction of the surface of the substrate 201; the first source-drain regions 208 are located in the active region 202 on two sides of the second isolation layer 207, the first source-drain regions 208 extend from the first surface 201a to the second surface 201b, and one capacitor 210 is electrically connected to one first source-drain region 208.
Fig. 16 to 21 are schematic structural views of steps in a method for forming a semiconductor structure according to another embodiment of the present invention.
In this embodiment, the bit lines are located on the first surface, and the capacitors are located on the second surface. The method for forming the bit line is shown in fig. 16 and 17 on the basis of fig. 6 and 7.
Referring to fig. 16 and 17, fig. 16 is a schematic top view of fig. 17 with the second dielectric layer omitted, fig. 17 is a schematic cross-sectional view of fig. 16 taken along HH1, and a second dielectric layer 301 is formed on the first surface 201 a; forming a plurality of fourth grooves (not labeled in the figure) in the second dielectric layer 301, where the fourth grooves extend along the second direction Y, and one fourth groove exposes a part of the surfaces of the plurality of active regions 202; the bit line 302 is formed within the fourth recess.
In this embodiment, specifically, after the insulating layer 206 is formed, the second dielectric layer 301 is formed.
The material of the bit line 302 includes a metal. In this embodiment, the metal is copper. In other embodiments, the metal may be aluminum, tungsten, or the like.
The bit lines 302 extend in the second direction Y and the word lines 205 extend in the first direction X, with an angle between the bit lines 302 and the word lines 205. Therefore, with the same chip unit area, the distance between adjacent bit lines 302 is increased, and the parasitic capacitance between the bit lines 302 is reduced, thereby improving the performance of the device.
In this embodiment, after forming the word line gate structure and before forming the bit line, the method further includes: and injecting second doping ions into the active region 202 from the first surface 201a to form a second source drain region 303 in the active region 202.
The second doping ions comprise N-type ions or P-type ions. In this embodiment, the second doping example is N-type ions.
In this embodiment, a bit line plug 304 is further provided between the bit line 302 and the active region 202, and a projection of the bit line plug 304 on the surface of the substrate 201 is located between projections of adjacent word line gate structures 205 on the surface of the substrate 201; the method for forming the bit line plug 304 includes: a second opening is further formed in the fourth groove, and the second source drain region 303 is exposed out of the second opening; the bit line plugs 304 are formed within the second openings. Specifically, the bit line plug 304 is located between the bit line 302 and the second source/drain region 303.
In other embodiments, the bit line 302 is in direct contact with the active region 202, and the bit line plug may not be formed.
Referring to fig. 18 and 19, fig. 18 is a schematic top view of fig. 19, fig. 19 is a schematic cross-sectional view of fig. 18 along the NN1 direction, and the substrate 201 is thinned from the second surface 201b until the surface of the first isolation layer 203 is exposed.
In this embodiment, specifically, after the bit line 302 is formed, the substrate 201 is thinned from the second surface 201 b.
The thinning processing method comprises the following steps: providing a substrate 400; bonding the surface of the substrate 400 with the surface of a second dielectric layer 301; and turning over the base 400 and the substrate 201, and thinning the second surface 201b of the substrate 201.
The thinning treatment process comprises a mechanical chemical grinding process.
With reference to fig. 18 and fig. 19, after the thinning process, before the capacitors are formed, second grooves (not labeled in the drawings) are formed in the substrate, the second grooves extend from the second surface 201b to the first surface 201a, the second grooves are arranged along a third direction Z, the third direction Z is perpendicular to the first direction X, the second grooves penetrate through the active regions 202 along the first direction X, projections of the second grooves on the surface of the substrate 201 are located between projections of adjacent word line gate structures 205 on the surface of the substrate 201, and a dimension of the second grooves along a normal direction of the surface of the substrate 201 is smaller than a dimension of the first isolation layer 203 along the normal direction of the surface of the substrate 201; a second isolation layer 305 is formed within the second recess.
Referring to fig. 20 and 21, fig. 20 is a schematic top view structure of fig. 21, fig. 21 is a schematic cross-sectional structure of fig. 20 along the NN1 direction, and after forming the second isolation layer 305 and before forming the plurality of capacitors, the method further includes: first doping ions are implanted into the active region 202 from the second surface 201b, and a first source drain region 306 is formed in the active region 202.
The first doping ions comprise N-type ions or P-type ions. In this embodiment, the first doping ions are N-type ions.
A channel is formed between the first source drain region 306 and the second source drain region 303, and the channel is a vertical channel, so that the density of the device is improved, and the integration level of the device is increased.
With continuing reference to fig. 20 and fig. 21, after the first source/drain region 306 is formed, a first dielectric layer 307 is formed on the second surface 201b and the first source/drain region 306; forming a plurality of third grooves (not shown) in the first dielectric layer 307, where the third grooves expose the surface of the first source drain region 306; a plurality of capacitors 308 are formed in the third groove, and one capacitor 308 is electrically connected with one first source drain region 306.
The capacitor 308 includes: a first electrode layer (not shown), a second electrode layer (not shown), and a dielectric layer (not shown) between the first electrode layer and the second electrode layer.
The shape of the dielectric layer includes: planar or "U" shaped.
When the shape of the dielectric layer is planar, the surface of the first electrode layer is flat, and the surface of the second electrode layer is flat.
When the dielectric layer is in a U shape, the surface of the first electrode layer is an uneven surface, and the surface of the second electrode layer is an uneven surface; or the surface of the first electrode layer is flat, and the surface of the second electrode layer is flat.
The material of the first electrode layer includes: a metal or metal nitride; the material of the second electrode layer includes: a metal or metal nitride; the metal includes: combinations of one or more of copper, aluminum, tungsten, cobalt, nickel, and tantalum; the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride.
In this embodiment, a capacitor plug 309 is further disposed between the capacitor 308 and the first source/drain region 306; the method for forming the capacitor plug 309 includes: a first opening (not marked in the figure) is further formed in the third groove, and the first opening exposes the surface of the first source drain region 306; the capacitor plug 309 is formed within the first opening. In other embodiments, the capacitor may be in direct contact with the first source drain region without forming the capacitor plug.
The material of the capacitor plug 309 includes: a metal or metal nitride; the metal includes: combinations of one or more of copper, aluminum, tungsten, cobalt, nickel, and tantalum; the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride.
To this end, the formed semiconductor structure, the capacitors 308 and the bit lines 302 do not need a special alignment process in the formation process, thereby simplifying the process difficulty; meanwhile, from the memory cell array, the bit line and the capacitor are respectively positioned at two sides of the active region, and the unit memory cell is 4F2The structure of (2) occupies a small area, and improves the integration level of the chip.
Accordingly, an embodiment of the present invention further provides a semiconductor structure formed by the above method, with reference to fig. 21, including: a substrate 201, where the substrate 201 has a first surface 201a and a second surface 201b opposite to each other, the substrate 201 includes a plurality of active regions 202 and first isolation layers 203 arranged in an array along a first direction X and a second direction Y, the first isolation layers 203 are located between adjacent active regions 202, the second direction Y forms an acute included angle with the first direction X, a projection pattern of each active region 202 on the first surface 201a or the second surface 201b is a rectangle, and a long side direction of the rectangle is perpendicular to the first direction X; a plurality of first grooves (not labeled in the figure) located in the substrate 201, the first grooves extending from the first surface 201a to the second surface 201b, the plurality of first grooves being arranged in parallel along a third direction Z, the third direction Z being perpendicular to the first direction X, each first groove being located between two adjacent rows of active regions 202, two sides of the first groove along the third direction Z further penetrating through the plurality of active regions 202, and sidewalls and bottoms of the first grooves exposing a portion of surfaces of the active regions 202; a word line gate structure 205 located within the first recess; a second isolation layer 305 located in each active region 202, wherein a projection of the second isolation layer 305 on the surface of the substrate 201 is located between projections of the adjacent word line gate structures 205 on the surface of the substrate 201; a plurality of bit lines 302 on the first side 201a and a plurality of capacitors 308 on the second side 201b, the bit lines 302 being parallel to the second direction Y, and each bit line 302 being electrically connected to a set of a plurality of the active regions 202, each of the active regions 202 being electrically connected to two capacitors 308.
In the semiconductor structure, the bit line and the capacitor are respectively positioned at two sides of the active region from the memory cell array, and the unit memory cell is 4F2The structure of (2) occupies a small area, and improves the integration level of the chip.
The bit lines 302 are located on the first surface 201a, the capacitors 308 are located on the second surface 201b, and further comprising: a plurality of second grooves (not shown) in the substrate 201, wherein the second isolation layer 305 is located in the second grooves, the plurality of second grooves extend from the second surface to the first surface 201b, the plurality of second grooves are arranged along a third direction Z, the third direction Z is perpendicular to the first direction X, the second grooves penetrate the plurality of active regions 202 along the first direction X, a projection of the second grooves on the surface of the substrate 201 is located between projections of adjacent word line gate structures 205 on the surface of the substrate 201, and a dimension of the second grooves along a normal direction of the surface of the substrate 201 is smaller than a dimension of the first isolation layer 203 along the normal direction of the surface of the substrate 201; the first source drain regions 306 and the one capacitor 308 are electrically connected to the first source drain regions 306 in the active region 202 on two sides of the second isolation layer 305.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (19)
1. A semiconductor structure, comprising:
the substrate is provided with a first surface and a second surface which are opposite, the substrate comprises a plurality of active regions and first isolation layers which are arrayed along a first direction and a second direction, the first isolation layers are positioned between adjacent active regions, an acute included angle is formed between the second direction and the first direction, the projection pattern of each active region on the first surface or the second surface is rectangular, and the long side direction of the rectangle is perpendicular to the first direction;
the first grooves extend from the first surface to the second surface and are arranged in parallel along a third direction, the third direction is perpendicular to the first direction, each first groove is positioned between two adjacent rows of active regions, two sides of each first groove along the third direction penetrate through the active regions, and the side walls and the bottoms of the first grooves expose partial surfaces of the active regions;
the word line grid structure is positioned in the first groove;
the projections of the second isolation layers on the surface of the substrate are positioned between the projections of the adjacent word line gate structures on the surface of the substrate;
the bit lines are parallel to the second direction, each bit line is electrically connected with a group of the active regions, and each active region is electrically connected with two capacitors;
or, the bit lines are positioned on the second surface and the plurality of capacitors are positioned on the first surface, the bit lines are electrically connected with the active regions, the bit lines are parallel to the second direction and are arranged along the first direction, and each active region is electrically connected with two capacitors.
2. The semiconductor structure of claim 1, wherein the plurality of bit lines are located on a first side and the plurality of capacitors are located on the second side, further comprising: the second isolation layers are positioned in the second grooves, the second grooves extend from the second face to the first face, the second grooves are arranged along a third direction, the third direction is perpendicular to the first direction, the second grooves penetrate through the active regions along the first direction, the projections of the second grooves on the surface of the substrate are positioned between the projections of adjacent word line gate structures on the surface of the substrate, and the size of the second grooves along the normal direction of the surface of the substrate is smaller than that of the first isolation layers along the normal direction of the surface of the substrate; and the first source-drain regions are positioned in the active regions on two sides of the second isolation layer, and one capacitor is electrically connected with one first source-drain region.
3. The semiconductor structure of claim 1, wherein the bit line is located on a second side and the plurality of capacitors are located on a first side, further comprising: the second isolation layer is positioned in the second groove, the second groove extends from the first surface to the second surface, the second grooves are arranged along a third direction, the third direction is perpendicular to the first direction, the second groove penetrates through the active regions along the first direction, the projection of the second groove on the surface of the substrate is positioned between the projections of adjacent word line gate structures on the surface of the substrate, and the size of the second groove in the normal direction of the surface of the substrate is smaller than that of the first isolation layer in the normal direction of the surface of the substrate; and the first source drain regions are positioned in the active regions at two sides of the second isolation layer, extend from the first surface to the second surface, and one capacitor is electrically connected with one first source drain region.
4. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate is provided with a first surface and a second surface which are opposite, the substrate comprises a plurality of active regions and first isolation layers which are arranged along a first direction and a second direction, the first isolation layers are positioned between adjacent active regions, an acute included angle is formed between the second direction and the first direction, the projection pattern of each active region on the first surface or the second surface is rectangular, and the long side direction of the rectangle is perpendicular to the first direction;
forming a plurality of first grooves in the substrate, wherein the first grooves extend from a first surface to a second surface, the first grooves are arranged in parallel along a third direction, the third direction is perpendicular to the first direction, each first groove is positioned between two adjacent rows of active regions, two sides of each first groove along the third direction penetrate through the active regions, and the side walls and the bottoms of the first grooves expose partial surfaces of the active regions;
forming a word line gate structure in the first groove;
thinning the substrate from the second side until the surface of the first isolation layer is exposed;
forming second isolation layers in the active regions, wherein projections of the second isolation layers on the surface of the substrate are positioned between projections of adjacent word line gate structures on the surface of the substrate;
forming a plurality of bit lines on the first surface, forming a plurality of capacitors on the thinned second surface, wherein the bit lines are parallel to the second direction, each bit line is electrically connected with a plurality of active regions, and each active region is electrically connected with two capacitors;
or forming a plurality of bit lines on the thinned second surface, forming a plurality of capacitors on the first surface, wherein the bit lines are parallel to the second direction, each bit line is electrically connected with a plurality of active regions, and each active region is electrically connected with two capacitors.
5. The method of forming a semiconductor structure of claim 4, wherein said plurality of bit lines are located on said first side and said plurality of capacitors are located on said second side; the method for forming the second isolation layer comprises the following steps: after the thinning treatment, before the capacitors are formed, a plurality of second grooves are formed in the substrate, the second grooves extend from the second surface to the first surface, the second grooves are arranged along a third direction, the third direction is perpendicular to the first direction, the second grooves penetrate through the active regions along the first direction, the projections of the second grooves on the surface of the substrate are located between the projections of adjacent word line gate structures on the surface of the substrate, and the size of the second grooves in the normal direction of the surface of the substrate is smaller than that of the first isolation layer in the normal direction of the surface of the substrate; and forming a second isolation layer in the second groove.
6. The method of forming a semiconductor structure of claim 5, wherein after forming the second isolation layer and before forming the plurality of capacitors, further comprising: and injecting first doping ions into the active region from the second surface to form a first source drain region in the active region.
7. The method of forming a semiconductor structure of claim 6, wherein the forming of the plurality of capacitors comprises: after the first source drain region is formed, forming a first dielectric layer on the second surface and the first source drain region; forming a plurality of third grooves in the first dielectric layer, wherein the third grooves expose the surface of the first source drain region; and forming a plurality of capacitors in the third groove, wherein one capacitor is electrically connected with one first source drain region.
8. The method for forming the semiconductor structure according to claim 7, wherein a capacitor plug is further arranged between the capacitor and the first source drain region; the forming method of the capacitor plug comprises the following steps: a first opening is further formed in the third groove, and the first opening exposes the surface of the first source drain region; and forming the capacitor plug in the first opening.
9. The method of forming a semiconductor structure of claim 4, wherein the bit line is located on the first surface, the method comprising: forming a second dielectric layer on the first surface; forming a plurality of fourth grooves in the second dielectric layer, wherein the fourth grooves extend along the second direction, and one fourth groove exposes partial surfaces of the active regions; and forming the bit line in the fourth groove.
10. The method of forming a semiconductor structure of claim 9, wherein after forming the word line gate structure and before forming the bit line, further comprising: and injecting second doping ions into the active region from the first surface to form a second source drain region in the active region.
11. The method of claim 10, further comprising a bit line plug between the bit line and the active region, wherein a projection of the bit line plug on the substrate surface is between projections of adjacent word line gate structures on the substrate surface; the bit line plug forming method comprises the following steps: a second opening is further formed in the fourth groove, and the second source drain region is exposed out of the second opening; and forming the bit line plug in the second opening.
12. The method of forming a semiconductor structure of claim 4, wherein the plurality of capacitors are located on the first side; the method for forming the second isolation layer comprises the following steps: forming a plurality of second grooves in the substrate, wherein the second grooves extend from the first surface to the second surface, the second grooves are arranged along a third direction, the third direction is perpendicular to the first direction, the second grooves penetrate through the active regions along the first direction, the projections of the second grooves on the surface of the substrate are positioned between the projections of adjacent word line gate structures on the surface of the substrate, and the size of the second grooves along the normal direction of the surface of the substrate is smaller than that of the first isolation layer along the normal direction of the surface of the substrate; and forming a second isolation layer in the second groove.
13. The method of forming a semiconductor structure of claim 12, wherein after forming the second isolation layer and before forming the plurality of capacitors, further comprising: and injecting first doping ions into the active region from the first surface to form a first source drain region in the active region.
14. The method of forming a semiconductor structure of claim 13, wherein the forming of the plurality of capacitors comprises: after the first source drain region is formed, forming a first dielectric layer on the first surface and the first source drain region; forming a plurality of third grooves in the first dielectric layer, wherein the third grooves expose the surface of the first source drain region; and forming the capacitors in the third groove, wherein one capacitor is electrically connected with one first source drain region.
15. The method for forming the semiconductor structure according to claim 14, wherein a capacitor plug is further provided between the capacitor and the first source-drain region, and the method for forming the capacitor plug includes: a first opening is further formed in the third groove, and the first opening exposes the surface of the first source drain region; and forming the capacitor plug in the first opening.
16. The method of forming a semiconductor structure of claim 12, wherein the bit line is located on the second side, the method comprising: after the thinning treatment, forming a second dielectric layer on the second surface; forming a plurality of fourth grooves in the second dielectric layer, wherein the fourth grooves extend along the second direction, and one fourth groove exposes partial surfaces of the active regions; and forming the bit line in the fourth groove.
17. The method of forming a semiconductor structure of claim 16, wherein after forming the word line gate structure and before forming the bit line, further comprising: and injecting second doping ions into the active region from the second surface to form a second source drain region in the active region.
18. The method of forming a semiconductor structure of claim 17, further comprising a bitline plug between the bitline and the active region, a projection of the bitline plug at the substrate surface being between projections of adjacent wordline gate structures at the substrate surface; the bit line plug forming method comprises the following steps: a second opening is further formed in the fourth groove, and the second source drain region is exposed out of the second opening; and forming the bit line plug in the second opening.
19. The method of claim 4, wherein an angle between the second direction and the first direction is in a range from 15 degrees to 75 degrees.
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