CN113707660B - Dynamic random access memory and forming method thereof - Google Patents

Dynamic random access memory and forming method thereof Download PDF

Info

Publication number
CN113707660B
CN113707660B CN202111028397.1A CN202111028397A CN113707660B CN 113707660 B CN113707660 B CN 113707660B CN 202111028397 A CN202111028397 A CN 202111028397A CN 113707660 B CN113707660 B CN 113707660B
Authority
CN
China
Prior art keywords
word line
layer
forming
isolation
random access
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202111028397.1A
Other languages
Chinese (zh)
Other versions
CN113707660A (en
Inventor
华文宇
刘藩东
丁潇
朱宏斌
华子群
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ICLeague Technology Co Ltd
Original Assignee
ICLeague Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ICLeague Technology Co Ltd filed Critical ICLeague Technology Co Ltd
Priority to CN202111028397.1A priority Critical patent/CN113707660B/en
Publication of CN113707660A publication Critical patent/CN113707660A/en
Application granted granted Critical
Publication of CN113707660B publication Critical patent/CN113707660B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)

Abstract

A dynamic random access memory and a forming method thereof include: a substrate having a first side and a second side, the substrate comprising a plurality of active regions, each active region comprising a channel region and a word line region; a word line gate structure located within the word line region; a first isolation structure located within each of the word line regions; a second isolation structure located within each of the channel regions; a first source-drain doped region located in the first face of the channel region; a capacitor structure on the first side; a second source-drain doped region located in the second face of the channel region; and a bit line layer on the second side. Through arranging the capacitor structure and the bit line layer on the first surface and the second surface of the substrate, the difficulty of circuit wiring and manufacturing process can be effectively reduced, the occupied area of a single storage structure can be effectively reduced, and the storage density of the memory can be improved.

Description

Dynamic random access memory and forming method thereof
Technical Field
The present disclosure relates to semiconductor manufacturing technology, and more particularly, to a dynamic random access memory and a method for forming the same.
Background
With rapid development of technology nowadays, semiconductor memories are widely used in electronic devices. Dynamic random access memory (dynamic random access memory, DRAM) is one of the most commonly utilized solutions for applications storing large amounts of data.
In general, a dram is composed of a plurality of memory cells, each of which is mainly composed of a transistor and a capacitor controlled by the transistor, and each of which is electrically connected to each other through a word line and a bit line.
However, there are still a number of problems with existing dynamic random access memories.
Disclosure of Invention
The invention solves the technical problem of providing a dynamic random access memory and a forming method thereof, which can effectively reduce the process difficulty and improve the storage density of the memory.
In order to solve the above problems, the present invention provides a dynamic random access memory, comprising: a substrate having opposite first and second sides, the substrate comprising a plurality of active regions separated from each other and parallel to a first direction, the plurality of active regions being arranged along a second direction, the first direction being perpendicular to the second direction, each of the active regions comprising a plurality of word line regions and a plurality of channel regions, and the plurality of word line regions and the plurality of channel regions in each of the active regions being spaced apart along the first direction; a word line gate trench within each of the word line regions, the word line gate trench extending from the first face to the second face, and the word line gate trench extending through the active region in the second direction; two mutually separated word line grating structures positioned in each word line grating groove, and a first isolation opening is arranged between the two word line grating structures; a first isolation structure located within each of the word line regions, the first isolation structure also located within a first isolation opening between two of the word line gate structures; a second isolation structure located within each of the channel regions; a first source-drain doped region located in a first face of each channel region; a plurality of capacitor structures located on the first surface, each capacitor structure being electrically connected to one of the first source-drain doped regions; a second source-drain doped region located in a second face of each channel region; and a plurality of bit line layers parallel to the first direction and positioned on the second surface, wherein each bit line layer is electrically connected with a plurality of second source-drain doped regions in one active region.
Optionally, the method further comprises: and the isolating layers are positioned between the adjacent active areas, and penetrate through the substrate from the first face to the second face.
Optionally, the method further comprises: and the flat layer is positioned at the bottom of the word line grating groove, and the word line grating structure is positioned on the flat layer.
Optionally, the material of the flat layer includes an insulating dielectric material; the insulating dielectric material comprises: and (3) silicon oxide.
Optionally, the depth of the second source-drain doped region is greater than or equal to the spacing between the word line gate structure and the second face of the substrate.
Optionally, the word line gate structure includes: and the word line grating medium layer is positioned on the side wall and the bottom surface of the word line grating groove, and the word line grating layer is positioned on the word line grating medium layer.
Optionally, the word line gate layer includes: a single layer structure or a composite structure.
Optionally, when the word line gate layer has a single layer structure, the material of the word line gate layer includes: metal or polysilicon.
Optionally, when the word line gate layer is a composite structure, the word line gate layer includes a first gate layer and a second gate layer located on the first gate layer, and materials of the first gate layer and the second gate layer are different.
Optionally, the material of the first gate layer includes: metal or polysilicon; the material of the second gate layer includes: polysilicon or metal.
Optionally, a distance between the first isolation structure and the second face is smaller than or equal to a distance between the word line gate structure and the second face.
Optionally, the method further comprises: and the first conductive plugs are positioned on each first source-drain doping region, and each capacitor structure is electrically connected with one first conductive plug.
Optionally, the method further comprises: and the second conductive plugs are used for respectively electrically connecting each bit line layer with the second source-drain doped regions in the corresponding active region.
Optionally, the capacitor structure includes: an upper electrode layer, a lower electrode layer, and a dielectric layer between the upper electrode layer and the lower electrode layer.
Correspondingly, the invention also provides a method for forming the dynamic random access memory, which comprises the following steps: providing a substrate, wherein the substrate is provided with a first surface and a second surface which are opposite, the substrate comprises a plurality of active areas which are mutually separated and parallel to a first direction, the plurality of active areas are arranged along a second direction, the first direction is perpendicular to the second direction, each active area comprises a plurality of word line areas and a plurality of channel areas, and the plurality of word line areas and the plurality of channel areas in each active area are arranged at intervals along the first direction; forming a word line gate trench within each of the word line regions, the word line gate trench extending from the first face to the second face, and the word line gate trench extending through the active region in the second direction; forming an initial word line gate structure in each word line gate trench; etching a part of the initial word line grating structure from the direction of the first face to the second face, forming a plurality of first isolation openings parallel to the second direction in the substrate, penetrating the initial word line grating structure from the direction of the first face to the second face through the first isolation openings, and enabling the initial word line grating structure to form two mutually separated word line grating structures; etching part of the channel region from the first surface to the second surface, and forming a plurality of second isolation openings parallel to the second direction in the substrate; forming a first isolation structure in the first isolation opening; forming a second isolation structure in the second isolation opening; forming a first source-drain doped region in a first surface of each channel region; forming a plurality of capacitor structures on the first surface, wherein each capacitor structure is electrically connected with one first source-drain doped region; thinning the substrate from the second surface to the first surface; forming a second source-drain doped region in a second surface of each channel region; and forming a plurality of bit line layers parallel to the first direction on the second surface, wherein each bit line layer is electrically connected with a plurality of second source-drain doped regions in one active region.
Optionally, before forming the word line gate trench, the method further includes: and forming an isolation layer between adjacent active areas.
Optionally, the forming method of the isolation layer includes: forming a layer of isolation material between adjacent ones of the active regions and on the first face; and carrying out planarization treatment on the isolation material layer until the first surface is exposed, so as to form the isolation layer.
Optionally, after forming the word line gate trench and before forming the initial word line gate structure, the method further comprises: forming a flat layer at the bottom of the word line grating groove; the word line gate structure is located on the planarization layer.
Optionally, the method for forming the flat layer at the bottom of the word line gate trench includes: forming a flat material layer at the bottom of the word line grating groove by adopting a spin coating process, wherein the flat material layer is fluid; and curing the flat material layer to form the flat layer.
Optionally, the material of the flat layer includes an insulating dielectric material; the insulating dielectric material comprises: and (3) silicon oxide.
Optionally, the depth of the second source-drain doped region is greater than or equal to the spacing between the word line gate structure and the second face of the substrate.
Optionally, the word line gate structure includes: and the word line grating medium layer is positioned on the side wall and the bottom surface of the word line grating groove, and the word line grating layer is positioned on the word line grating medium layer.
Optionally, the word line gate layer includes: a single layer structure or a composite structure.
Optionally, when the word line gate layer has a single layer structure, the material of the word line gate layer includes: metal or polysilicon.
Optionally, when the word line gate layer is a composite structure, the word line gate layer includes a first gate layer and a second gate layer located on the first gate layer, and materials of the first gate layer and the second gate layer are different.
Optionally, the material of the first gate layer includes: metal or polysilicon; the material of the second gate layer includes: polysilicon or metal.
Optionally, a distance between the first isolation structure and the second face is smaller than or equal to a distance between the word line gate structure and the second face.
Optionally, before forming the plurality of capacitor structures, the method further includes: and forming a first conductive plug on each first source-drain doped region, wherein each capacitor structure is electrically connected with one first conductive plug.
Optionally, before forming the plurality of bit line layers, the method further includes: and forming a plurality of second conductive plugs, wherein each bit line layer is electrically connected with a plurality of second source-drain doped regions in a corresponding active region through the plurality of second conductive plugs.
Optionally, the capacitor structure includes: an upper electrode layer, a lower electrode layer, and a dielectric layer between the upper electrode layer and the lower electrode layer.
Optionally, the first isolation opening and the second isolation opening are formed simultaneously or not simultaneously.
Optionally, the forming method of the first isolation structure and the second isolation structure includes: forming a layer of isolation material within the first isolation opening, within the second isolation opening, and on the first face; and flattening the isolation material layer until the first surface is exposed, so as to form the first isolation structure and the second isolation structure.
Compared with the prior art, the technical scheme of the invention has the following advantages:
in the structure of the technical scheme of the invention, the capacitor structure and the bit line layer are respectively arranged on the first surface and the second surface of the substrate, so that the space of the capacitor structure and the bit line layer in arrangement can be increased, the difficulty of circuit wiring and manufacturing process can be effectively reduced, the occupied area of a single storage structure can be effectively reduced, and the storage density of a memory can be improved.
In addition, from the perspective of exposure process, since the capacitor structure is in a hole structure, the bit line layer is in a linear structure, the hole structure is exposed with high difficulty, the linear structure is exposed with high difficulty, and the exposure requirement is higher when the process is performed from the second surface. Therefore, the capacitor structure with larger exposure difficulty is arranged on the first surface of the substrate, and the bit line layer with smaller exposure difficulty is arranged on the second surface, so that the difficulty of an exposure process can be effectively reduced.
From the point of signal extraction, the upper electrode plate of the capacitor structure and the bit line layer need to be extracted. In the same DRAM, the upper electrode plates of the capacitor structures are connected with each other, so that a conductive area with a larger area is formed, and the capacitor structures are easier to lead out. The line width of the bit line layer is smaller, and the corresponding extraction is more difficult. Because the signal is led out from the second surface of the substrate in the process of forming the dynamic random access memory, the capacitor structure with smaller lead difficulty is arranged on the first surface, and the bit line layer with larger lead difficulty is arranged on the second surface, so that the process difficulty in signal leading out can be effectively reduced.
Further, the method further comprises the following steps: and the flat layer is positioned at the bottom of the word line grating groove, and the word line grating structure is positioned on the flat layer. The flat layer at the bottom of the word line grating groove can effectively improve the controllability of the subsequent manufacturing process and the stability and reliability of the finally formed device structure.
According to the forming method of the technical scheme, the capacitor structure and the bit line layer are respectively arranged on the first surface and the second surface of the substrate, so that the space of the capacitor structure and the bit line layer in arrangement can be increased, the difficulty of circuit wiring and manufacturing process can be effectively reduced, the occupied area of a single storage structure can be effectively reduced, and the storage density of a memory can be improved. In addition, in the process of forming the capacitor structure and the bit line layer, the capacitor structure and the bit line layer can be respectively carried out from the first surface and the second surface of the substrate, so that the processing efficiency can be effectively improved.
In addition, from the perspective of exposure process, since the capacitor structure is in a hole structure, the bit line layer is in a linear structure, the hole structure is exposed with high difficulty, the linear structure is exposed with high difficulty, and the exposure requirement is higher when the process is performed from the second surface. Therefore, the capacitor structure with larger exposure difficulty is arranged on the first surface of the substrate, and the bit line layer with smaller exposure difficulty is arranged on the second surface, so that the difficulty of an exposure process can be effectively reduced.
From the point of signal extraction, the upper electrode plate of the capacitor structure and the bit line layer need to be extracted. In the same DRAM, the upper electrode plates of the capacitor structures are connected with each other, so that a conductive area with a larger area is formed, and the capacitor structures are easier to lead out. The line width of the bit line layer is smaller, and the corresponding extraction is more difficult. Because the signal is led out from the second surface of the substrate in the process of forming the dynamic random access memory, the capacitor structure with smaller lead difficulty is arranged on the first surface, and the bit line layer with larger lead difficulty is arranged on the second surface, so that the process difficulty in signal leading out can be effectively reduced.
In addition, the forming method of the word line grating structure is that an initial word line grating structure is formed first, and then the initial word line grating structure is divided into two mutually separated word line grating structures by forming the first isolation opening. Because the pattern size of the single word line grating structure is smaller, the distance between the adjacent word line grating structures is smaller, and the corresponding exposure process is more difficult. The initial word line grating structure with larger pattern size and larger adjacent space is formed, so that the difficulty of an exposure process can be effectively reduced.
Further, after forming the word line gate trench and before forming the initial word line gate structure, further comprising: forming a flat layer at the bottom of the word line grating groove; the word line gate structure is located on the planarization layer. By forming the flat layer at the bottom of the word line gate trench, the controllability of the subsequent process and the stability and reliability of the finally formed device structure can be effectively improved.
Drawings
Fig. 1 to 14 are schematic structural diagrams illustrating steps of a method for forming a dynamic random access memory according to an embodiment of the invention.
Detailed Description
As described in the background, there are still many problems with existing dynamic random access memories. The following will specifically explain.
In the existing dynamic random access memory, a bit line and a conductive structure connected with the bit line are also arranged between the capacitor and the word line and the transistor. Therefore, in order to connect the capacitor with the word line and the transistor, the capacitor structure, the bit line and the conductive structure connected with the bit line need to be avoided, so that the memory array area of the memory has complex circuit wiring and high manufacturing process difficulty.
On the basis, the invention provides the dynamic random access memory and the forming method thereof, and the capacitor structure and the bit line layer are respectively arranged on the first surface and the second surface of the substrate, so that the space of the capacitor structure and the bit line layer in arrangement can be increased, the difficulty of circuit wiring and manufacturing process can be effectively reduced, the occupied area of a single memory structure can be effectively reduced, and the memory density of the memory can be improved. In addition, in the process of forming the capacitor structure and the bit line layer, the capacitor structure and the bit line layer can be respectively carried out from the first surface and the second surface of the substrate, so that the processing efficiency can be effectively improved.
In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention briefly described above will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
Fig. 1 to 14 are schematic structural diagrams illustrating steps of a method for forming a dynamic random access memory according to an embodiment of the invention.
Referring to fig. 1 to 3, fig. 2 is a schematic cross-sectional view along line A-A in fig. 1, fig. 3 is a schematic cross-sectional view along line B-B in fig. 1, a substrate 100 is provided, the substrate 100 has a first surface 101 and a second surface 102 opposite to each other, the substrate 100 includes a plurality of active regions 103 separated from each other and parallel to a first direction X, the plurality of active regions 103 are arranged along a second direction Y, the first direction X is perpendicular to the second direction Y, each of the active regions 103 includes a plurality of word line regions 104 and a plurality of channel regions 105, and the plurality of word line regions 104 and the plurality of channel regions 105 in each of the active regions 103 are arranged at intervals along the first direction X.
In this embodiment, the material of the substrate 100 is silicon; in other embodiments, the material of the substrate may also be germanium, silicon carbide, gallium arsenide, or indium gallium.
In this embodiment, the channel region 105 and the word line region 104 are used to form a transistor device later.
Referring to fig. 4, the view directions of fig. 4 and fig. 2 are identical, and an isolation layer 106 is formed between adjacent active regions 103.
In this embodiment, the method for forming the isolation layer 106 includes: forming an initial isolation layer (not shown) between adjacent active regions 103 and on the first surface 101; the initial isolation layer is planarized until the first surface 101 is exposed, forming the isolation layer 106.
In this embodiment, the material of the isolation layer 106 is silicon oxide.
Referring to fig. 5, the view directions of fig. 5 and fig. 3 are identical, a word line gate trench 107 is formed in each word line region 104, the word line gate trench 107 extends from the first face 101 to the second face 102, and the word line gate trench 107 penetrates the active region 103 along the second direction Y.
In this embodiment, the word line gate trench 107 provides space for subsequent formation of word line gate structures within the word line gate trench 107.
In this embodiment, the method for forming the word line gate trench 107 includes: forming a first patterned layer (not shown) on the first side 101 of the substrate 100, the first patterned layer exposing the word line region 104; and etching from the first surface 101 to the second surface 102 by using the first patterned layer as a mask to form the word line gate trench 107.
In this embodiment, the depth of the word line gate trench 107 is less than the depth of the isolation layer 106. In other embodiments, the depth of the word line gate trench may also be equal to the depth of the isolation layer.
In this embodiment, the isolation layer 106 and the word line region 104 need to be etched simultaneously in forming the word line gate trench 107. Because the materials of the isolation layer 106 and the word line region 104 are different, in the etching process, the etching rates of the isolation layer 106 and the word line region 104 are different, which easily results in the uneven bottom of the finally formed word line gate trench 107, and thus easily affects the controllability of the subsequent manufacturing process, and the stability and reliability of the finally formed device structure.
In this embodiment, please continue to refer to fig. 5, a planarization layer 121 is formed at the bottom of the word line gate trench 107.
In this embodiment, the method for forming the planarization layer 121 at the bottom of the word line gate trench 107 includes: forming a flat material layer (not shown) at the bottom of the word line gate trench 107 by a spin coating process, wherein the flat material layer is fluid; the flat material layer is cured to form the flat layer 121.
In this embodiment, the material of the planarization layer 121 includes an insulating dielectric material; the insulating dielectric material is silicon oxide.
By forming the planarization layer 121 at the bottom of the word line gate trench 107, the controllability of the subsequent process and the stability and reliability of the finally formed device structure can be effectively improved.
In other embodiments, the planarization layer may not be formed when the planarization of the bottom of the word line gate trench is higher.
Referring to fig. 6 and 7, fig. 7 is a schematic cross-sectional view along line C-C in fig. 6, and an initial word line gate structure 108 is formed in each of the word line gate trenches 107.
In this embodiment, the initial word line gate structure 108 includes: an initial word line gate dielectric layer located on the sidewalls and bottom surface of the word line gate trench 107, and an initial word line gate layer (not labeled) located on the initial word line gate dielectric layer.
With continued reference to fig. 7, in this embodiment, the initial word line gate structure 108 does not fill the word line gate trench 107, and after forming the initial word line gate structure 108, further includes: a dielectric layer 109 is formed on the first side 101 of the substrate 100, the dielectric layer 109 fills the word line gate trench 107, and the dielectric layer 109 exposes the surface of the channel region 105.
Referring to fig. 8, the view directions of fig. 8 and fig. 7 are consistent, etching a portion of the initial word line gate structure 108 from the first surface 101 toward the second surface 102, forming a plurality of first isolation openings 110 parallel to the second direction Y in the substrate 100, wherein the first isolation openings 110 penetrate the initial word line gate structure 108 from the first surface 101 toward the second surface 102, and forming two mutually separated word line gate structures 111 of the initial word line gate structure 108; a portion of the channel region 105 is etched from the first side 101 toward the second side 102, forming a plurality of second isolation openings 112 in the substrate 100 parallel to the second direction Y.
In the present embodiment, the first isolation opening 110 and the second isolation opening 112 are formed simultaneously. The first isolation opening 110 and the second isolation opening 112 are formed simultaneously by a single exposure process, which can effectively improve the process efficiency.
In this embodiment, the method for forming the first isolation opening 110 and the second isolation opening 112 includes: forming a second patterned layer (not shown) on the first side 101 of the substrate 100, the second patterned layer exposing a portion of the top surface of the dielectric layer 109 and a portion of the top surface of the channel region 105; and etching from the first surface 101 to the second surface 102 by using the first patterned layer as a mask to form the first isolation opening 110 and the second isolation opening 112.
In other embodiments, the first isolation opening and the second isolation opening may also be formed at different times. The first isolation opening and the second isolation opening are formed by adopting a double exposure process, so that the pattern density in a single exposure process can be reduced, and the difficulty of the single exposure process is further reduced.
In this embodiment, the depth of the second isolation opening 112 is greater than or equal to the distance between the second source-drain doped region formed later and the first surface 101 of the substrate 100.
In this embodiment, the method for forming the word line grating structure 111 is to form the initial word line grating structure 108 first, and then divide the initial word line grating structure 108 into two mutually separated word line grating structures 111 by forming the first isolation opening 110. Because the pattern size of the single word line gate structure 111 is smaller, the space between the adjacent word line gate structures 111 is smaller, and the corresponding exposure process is more difficult. The difficulty of the exposure process can be effectively reduced by first forming the initial word line gate structure 108 with a larger pattern size and a larger adjacent pitch.
In this embodiment, the word line gate structure 111 includes: a word line gate dielectric layer on the side walls and bottom surface of the word line gate trench 107, and a word line gate layer (not labeled) on the word line gate dielectric layer.
In this embodiment, the word line gate layer adopts a composite structure, and the word line gate layer includes a first gate layer and a second gate layer (not labeled) located on the first gate layer, where materials of the first gate layer and the second gate layer are different.
In this embodiment, the material of the first gate layer is polysilicon, and the material of the second gate layer is metal; in other embodiments, the material of the first gate layer may also be metal, and the material of the corresponding second gate layer may be polysilicon.
In other embodiments, the word line gate layer may also have a single-layer structure, and when the word line gate layer has a single-layer structure, the material of the word line gate layer may be polysilicon or metal.
In this embodiment, the word line gate structure 111 is located on the planarization layer 121.
Referring to fig. 9, a first isolation structure 113 is formed in the first isolation opening 110; a second isolation structure 114 is formed within the second isolation opening 112.
In the present embodiment, the first isolation structure 113 and the second isolation structure 114 are formed simultaneously; in other embodiments, the first isolation structure and the second isolation structure may also be formed at different times.
In this embodiment, the method for forming the first isolation structure 113 and the second isolation structure 114 includes: forming a layer of isolation material (not shown) within the first isolation opening 110, within the second isolation opening 112, and on the first face 101; the first isolation structure 113 and the second isolation structure 114 are formed by performing planarization treatment on the isolation material layer until the first surface 101 is exposed.
In this embodiment, the first isolation structure 113 is used to connect only one side of the word line gate structure 111 to the channel region 105, so that the transistor is a single-sided channel structure. The DRAM with single-sided channel structure is not easy to generate leakage current during operation.
In this embodiment, the first isolation structure 113 and the second isolation structure 114 are made of silicon oxide.
In this embodiment, the spacing between the first isolation structure 113 and the second face 102 is smaller than the spacing between the word line gate structure 111 and the second face 102. The first isolation structure 113 can completely isolate the two word line gate structures 111 in the word line gate trench 107, so as to effectively prevent the two word line gate structures 111 from being shorted.
In other embodiments, the spacing between the first isolation structures 113 and the second face 102 may also be equal to the spacing between the word line gate structures 111 and the second face 102.
Referring to fig. 10, a first source-drain doped region 115 is formed in the first surface 101 of each channel region 105.
In this embodiment, the method for forming the first source-drain doped regions 115 in the first surface 101 of each channel region 105 includes: first ion implantation is performed from the first surface 101 to the second surface 102 by using an ion implantation process, and a first source-drain doped region 115 is formed in the first surface 101 of each channel region 105.
In this embodiment, the first ion is an N-type ion; in other embodiments, the first ions may also be P-type ions.
Referring to fig. 11, a plurality of capacitor structures 116 are formed on the first surface 101, and each capacitor structure 116 is electrically connected to one of the first source-drain doped regions 115.
In this embodiment, before forming the plurality of capacitor structures 116, further includes: forming a first conductive plug 117 on each of the first source-drain doped regions 115, each of the capacitor structures 116 being electrically connected to one of the first conductive plugs 117; in other embodiments, the first conductive plug may not be formed.
In this embodiment, the capacitor structure 116 includes: an upper electrode layer, a lower electrode layer, and a dielectric layer (not labeled) between the upper electrode layer and the lower electrode layer.
Referring to fig. 12, the substrate 100 is thinned from the second surface 102 toward the first surface 101.
The process of thinning the substrate 100 from the second surface 102 toward the first surface 101 includes a physical mechanical polishing process, a chemical mechanical polishing process, or a wet etching process. In this embodiment, the process of thinning the substrate 100 from the second surface 102 toward the first surface 101 uses a chemical mechanical polishing process.
The thinning process is performed until the surface of the isolation layer 106 is exposed.
In this embodiment, the depth of the first isolation structure 113 and the second isolation structure 114 is equal to the depth of the isolation layer 106. Thus, after the thinning process, the second side of the substrate 100 also exposes the surfaces of the first isolation structures 113 and the second isolation structures 114.
In other embodiments, the depth of the first isolation structure and the second isolation structure may be smaller than the depth of the isolation layer, and the second face of the substrate does not expose the surfaces of the first isolation structure and the second isolation structure after the thinning process.
Referring to fig. 13, a second source-drain doped region 118 is formed in the second face 102 of each channel region 105.
In this embodiment, the method for forming the second source-drain doped regions 118 in the second face 102 of each channel region 105 includes: a second ion implantation process is performed from the second surface 102 to the first surface 101, so as to form a second source-drain doped region 118 in the second surface 102 of each channel region 105.
The second ion is of the same electrical type as the first ion.
In this embodiment, the second ion is an N-type ion; in other embodiments, when the first ion is a P-type ion, the second ion may also be a P-type ion.
In this embodiment, the depth of the second source-drain doped region 118 is greater than the spacing between the word line gate structure 111 and the second face 102 of the substrate 101; in other embodiments, the depth of the second source drain doped region 118 may also be equal to the spacing between the word line gate structure and the second side of the substrate.
From here on, a number of transistors are formed within the substrate 100.
Referring to fig. 14, a plurality of bit line layers 119 parallel to the first direction X are formed on the second surface 102, and each of the bit line layers 119 is electrically connected to a plurality of the second source-drain doped regions 118 in one of the active regions 103.
In this embodiment, by arranging the capacitor structure 116 and the bit line layer 119 on the first surface 101 and the second surface 102 of the substrate 100, the space of the capacitor structure 116 and the bit line layer 119 during arrangement can be increased, so that the difficulty of circuit wiring and manufacturing process can be effectively reduced, the area occupied by a single storage structure can be effectively reduced, and the storage density of the memory can be improved. In addition, in the process of forming the capacitor structure 116 and the bit line layer 119, the process can be performed from the first surface 101 and the second surface 102 of the substrate 100, so as to effectively improve the process efficiency.
In addition, from the perspective of the exposure process, since the capacitor structure 116 is a hole-like structure, the bit line layer 119 is a linear structure, the hole-like structure is exposed with a relatively high difficulty, the linear structure is exposed with a relatively high difficulty, and the exposure requirement is higher when the process is performed from the second surface 102. Therefore, the capacitor structure 116 with relatively high exposure difficulty is arranged on the first surface 101 of the substrate 100, and the bit line layer 119 with relatively low exposure difficulty is arranged on the second surface 102 of the substrate 100, so that the difficulty of the exposure process can be effectively reduced.
From the standpoint of signal extraction, the upper electrode plate of the capacitor structure 116 and the bit line layer 119 need to be extracted. Since the upper electrode plates of the capacitor structures 116 are connected to each other in the same dram, and thus a conductive region with a larger area is formed, the capacitor structures 116 are easily led out. The bit line layer 119 has a smaller line width and is correspondingly more difficult to be led out. Because the signal extraction is completed from the second surface 102 of the substrate 100 during the formation of the dram, the capacitor structure 116 with smaller lead difficulty is arranged on the first surface 101 of the substrate 100, and the bit line layer 119 with larger lead difficulty is arranged on the second surface 102 of the substrate 100, so that the process difficulty during signal extraction can be effectively reduced.
In this embodiment, one of the capacitor structures 116 and one of the transistors are arranged in a two-dimensional matrix as one unit. The basic operation scheme is divided into Read (Read) and Write (Write), and the bit line layer 119 is charged to half the operating voltage during Read, and then the transistor is turned on to cause charge sharing between the bit line layer 119 and the capacitor structure 116. If the internally stored value is 1, the voltage of the bit line layer 119 will be raised by charge sharing to be higher than half the operating voltage; conversely, if the value stored internally is 0, the voltage of the bit line layer 119 is pulled down to be lower than half the operation voltage, and the value inside is determined to be 0 or 1 by an amplifier after the voltage of the bit line layer 119 is obtained. Turning on the transistor when writing, raising the voltage of the bit line layer 119 to an operating voltage to cause the capacitor structure 116 to store an operating voltage if a 1 is to be written; lowering the bit line layer 119 to 0 volts leaves the capacitor structure 116 with no charge inside if a 0 is to be written.
In this embodiment, before forming the plurality of bit line layers 119, the method further includes: forming a plurality of second conductive plugs 120, wherein each bit line layer 119 is electrically connected with a plurality of second source-drain doped regions 118 in a corresponding active region 103 by the plurality of second conductive plugs 120; in other embodiments, the second conductive plug may not be formed.
The material of the bit line layer 119 includes a metal including tungsten, aluminum, copper, and the like. In this embodiment, the material of the bit line layer 119 is tungsten.
In this embodiment, the method for forming the bit line layer 119 includes: forming a bit line material layer (not shown) on the second side 102; forming a third patterned layer (not shown) over the bit line material layer, the third patterned layer exposing a portion of the bit line material layer; and etching the bit line material layer from the second surface 102 to the first surface 101 by using the third patterned layer as a mask, so as to form a plurality of bit line layers 119.
The process of forming the bit line material layer includes: a metal plating process, a selective metal growth process, or a deposition process; the deposition process includes a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process. In this embodiment, the bit line material layer is formed by an atomic layer deposition process.
Accordingly, in an embodiment of the present invention, there is also provided a dynamic random access memory, please continue to refer to fig. 14, including: a substrate 100 having opposite first and second sides 101, 102, the substrate 100 comprising a plurality of active regions 103 separated from each other and parallel to a first direction X, and the plurality of active regions 103 arranged along a second direction Y, the first direction X being perpendicular to the second direction Y, each of the active regions 103 comprising a plurality of word line regions 104 and a plurality of channel regions 105, and the plurality of word line regions 104 and the plurality of channel regions 105 in each of the active regions 103 being spaced apart along the first direction X; a word line gate trench 107 located within each of the word line regions 104, the word line gate trench 107 extending from the first face 101 to the second face 102, and the word line gate trench 107 extending through the active region 103 in the second direction Y; two mutually separated word line gate structures 111 located in each of the word line gate trenches 107, with a first isolation opening 110 between the two word line gate structures 111; a first isolation structure 113 located within each of the word line regions 104, the first isolation structure 113 also being located within a first isolation opening 110 between two of the word line gate structures 111; a second isolation structure 114 located within each of the channel regions 105; a first source drain doped region 115 located within the first side 101 of each of the channel regions 105; a plurality of capacitor structures 116 on the first side 101, each capacitor structure 116 being electrically connected to one of the first source-drain doped regions 115; a second source drain doped region 118 located in the second side 102 of each of the channel regions 105; a plurality of bit line layers 119 located on the second side 102 and parallel to the first direction X, each bit line layer 119 being electrically connected to a plurality of second source drain doped regions 118 in one of the active regions 103.
In this embodiment, the capacitor structure 116 and the bit line layer 119 are respectively arranged on the first surface 101 and the second surface 102 of the substrate 100, so that the space of the capacitor structure 116 and the bit line layer 119 in arrangement can be increased, the difficulty of circuit wiring and manufacturing process can be effectively reduced, the occupied area of a single storage structure can be effectively reduced, and the storage density of the memory can be improved.
In addition, from the perspective of the exposure process, since the capacitor structure 116 is a hole-like structure, the bit line layer 119 is a linear structure, the hole-like structure is exposed with a relatively high difficulty, the linear structure is exposed with a relatively high difficulty, and the exposure requirement is higher when the process is performed from the second surface 102. Therefore, the capacitor structure 116 with relatively high exposure difficulty is arranged on the first surface 101 of the substrate 100, and the bit line layer 119 with relatively low exposure difficulty is arranged on the second surface 102 of the substrate 100, so that the difficulty of the exposure process can be effectively reduced.
From the standpoint of signal extraction, the upper electrode plate of the capacitor structure 116 and the bit line layer 119 need to be extracted. Since the upper electrode plates of the capacitor structures 116 are connected to each other in the same dram, and thus a conductive region with a larger area is formed, the capacitor structures 116 are easily led out. The bit line layer 119 has a smaller line width and is correspondingly more difficult to be led out. Because the signal extraction is completed from the second surface 102 of the substrate 100 during the formation of the dram, the capacitor structure 116 with smaller lead difficulty is arranged on the first surface 101 of the substrate 100, and the bit line layer 119 with larger lead difficulty is arranged on the second surface 102 of the substrate 100, so that the process difficulty during signal extraction can be effectively reduced.
In this embodiment, further comprising: and an isolation layer 106 located between adjacent active regions 103, wherein the isolation layer 106 penetrates through the substrate 100 from the first surface 101 to the second surface 102.
In this embodiment, further comprising: a planarization layer 121 located at the bottom of the word line gate trench 107, and the word line gate structure 111 is located on the planarization layer 121.
The planar layer 121 at the bottom of the word line gate trench 107 can effectively improve the controllability of the subsequent process, and the stability and reliability of the finally formed device structure.
In other embodiments, the planar layer may not be formed.
In this embodiment, the material of the planarization layer 121 includes an insulating dielectric material; the insulating dielectric material is silicon oxide.
In this embodiment, the depth of the second source-drain doped region 118 is greater than the spacing between the word line gate structure 111 and the second face 102 of the substrate 100; in other embodiments, the depth of the second source drain doped region may also be equal to the spacing between the word line gate structure and the second face of the substrate.
In this embodiment, the word line gate structure 111 includes: a word line gate dielectric layer on the side walls and bottom surface of the word line gate trench, and a word line gate layer (not labeled) on the word line gate dielectric layer.
In this embodiment, the word line gate layer adopts a composite structure, and the word line gate layer includes a first gate layer and a second gate layer (not labeled) located on the first gate layer, where materials of the first gate layer and the second gate layer are different.
In this embodiment, the material of the first gate layer is polysilicon, and the material of the second gate layer is metal; in other embodiments, the material of the first gate layer may also be metal, and the material of the corresponding second gate layer may be polysilicon.
In other embodiments, the word line gate layer may also have a single-layer structure, and when the word line gate layer has a single-layer structure, the material of the word line gate layer may be polysilicon or metal.
In this embodiment, the spacing between the first isolation structure 113 and the second face 102 is smaller than the spacing between the word line gate structure 111 and the second face 102. The first isolation structure 113 can completely isolate the two word line gate structures 111 in the word line gate trench 107, so as to effectively prevent the two word line gate structures 111 from being shorted.
In other embodiments, the spacing between the first isolation structure and the second face may also be equal to the spacing between the word line gate structure and the second face.
In this embodiment, further comprising: a first conductive plug 117 located on each of the first source-drain doped regions 115, each of the capacitor structures 116 being electrically connected to one of the first conductive plugs 117; in other embodiments, the first conductive plug may not be formed.
In this embodiment, further comprising: a plurality of second conductive plugs 120, wherein each bit line layer 119 is electrically connected with a plurality of second source-drain doped regions 118 in a corresponding one of the active regions 103 by a plurality of second conductive plugs 120; in other embodiments, the second conductive plug may not be formed.
In this embodiment, the capacitor structure 116 includes: an upper electrode layer, a lower electrode layer, and a dielectric layer (not labeled) between the upper electrode layer and the lower electrode layer.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (32)

1. A dynamic random access memory, comprising:
a substrate having opposite first and second sides, the substrate comprising a plurality of active regions separated from each other and parallel to a first direction, the plurality of active regions being arranged along a second direction, the first direction being perpendicular to the second direction, each of the active regions comprising a plurality of word line regions and a plurality of channel regions, and the plurality of word line regions and the plurality of channel regions in each of the active regions being spaced apart along the first direction;
A word line gate trench within each of the word line regions, the word line gate trench extending from the first face to the second face, and the word line gate trench extending through the active region in the second direction;
two word line grating structures which are positioned in each word line grating groove and are separated from each other, and a first isolation opening is arranged between the two word line grating structures;
a first isolation structure located within each of the word line regions, the first isolation structure also located within a first isolation opening between two of the word line gate structures;
a second isolation structure located within each of the channel regions;
a first source-drain doped region located in a first face of each channel region;
a plurality of capacitor structures located on the first surface, each capacitor structure being electrically connected to one of the first source-drain doped regions;
a second source-drain doped region located in a second face of each channel region;
and a plurality of bit line layers parallel to the first direction and positioned on the second surface, wherein each bit line layer is electrically connected with a plurality of second source-drain doped regions in one active region.
2. The dynamic random access memory of claim 1, further comprising: and the isolating layers are positioned between the adjacent active areas, and penetrate through the substrate from the first face to the second face.
3. The dynamic random access memory of claim 1, further comprising: and the flat layer is positioned at the bottom of the word line grating groove, and the word line grating structure is positioned on the flat layer.
4. The dynamic random access memory of claim 3, wherein the material of the planarization layer comprises an insulating dielectric material; the insulating dielectric material comprises: and (3) silicon oxide.
5. The dynamic random access memory of claim 1, wherein a depth of the second source drain doped region is greater than or equal to a spacing between the word line gate structure and the second side of the substrate.
6. The dynamic random access memory of claim 1, wherein the word line gate structure comprises: and the word line grating medium layer is positioned on the side wall and the bottom surface of the word line grating groove, and the word line grating layer is positioned on the word line grating medium layer.
7. The dynamic random access memory of claim 6, wherein the word line gate layer comprises: a single layer structure or a composite structure.
8. The dynamic random access memory of claim 7, wherein when the word line gate layer is a single layer structure, the material of the word line gate layer comprises: metal or polysilicon.
9. The dynamic random access memory of claim 7, wherein when the word line gate layer is a composite structure, the word line gate layer comprises a first gate layer and a second gate layer on the first gate layer, the first gate layer and the second gate layer being of different materials.
10. The dynamic random access memory of claim 9, wherein the material of the first gate layer comprises: metal or polysilicon; the material of the second gate layer includes: polysilicon or metal.
11. The dynamic random access memory of claim 1, wherein a spacing between the first isolation structure and the second face is less than or equal to a spacing between the word line gate structure and the second face.
12. The dynamic random access memory of claim 1, further comprising: and the first conductive plugs are positioned on each first source-drain doping region, and each capacitor structure is electrically connected with one first conductive plug.
13. The dynamic random access memory of claim 1, further comprising: and the second conductive plugs are used for respectively electrically connecting each bit line layer with the second source-drain doped regions in the corresponding active region.
14. The dynamic random access memory of claim 1, wherein the capacitance structure comprises: an upper electrode layer, a lower electrode layer, and a dielectric layer between the upper electrode layer and the lower electrode layer.
15. A method for forming a dynamic random access memory, comprising:
providing a substrate, wherein the substrate is provided with a first surface and a second surface which are opposite, the substrate comprises a plurality of active areas which are mutually separated and parallel to a first direction, the plurality of active areas are arranged along a second direction, the first direction is perpendicular to the second direction, each active area comprises a plurality of word line areas and a plurality of channel areas, and the plurality of word line areas and the plurality of channel areas in each active area are arranged at intervals along the first direction;
forming a word line gate trench within each of the word line regions, the word line gate trench extending from the first face to the second face, and the word line gate trench extending through the active region in the second direction;
forming an initial word line gate structure in each word line gate trench;
etching a part of the initial word line grating structure from the direction of the first face to the second face, forming a plurality of first isolation openings parallel to the second direction in the substrate, penetrating the initial word line grating structure from the direction of the first face to the second face through the first isolation openings, and enabling the initial word line grating structure to form two mutually separated word line grating structures;
Etching part of the channel region from the first surface to the second surface, and forming a plurality of second isolation openings parallel to the second direction in the substrate;
forming a first isolation structure in the first isolation opening;
forming a second isolation structure in the second isolation opening;
forming a first source-drain doped region in a first surface of each channel region;
forming a plurality of capacitor structures on the first surface, wherein each capacitor structure is electrically connected with one first source-drain doped region;
thinning the substrate from the second surface to the first surface;
forming a second source-drain doped region in a second surface of each channel region;
and forming a plurality of bit line layers parallel to the first direction on the second surface, wherein each bit line layer is electrically connected with a plurality of second source-drain doped regions in one active region.
16. The method of forming a dynamic random access memory of claim 15, further comprising, prior to forming the word line gate trench: and forming an isolation layer between adjacent active areas.
17. The method of forming a dynamic random access memory of claim 16, wherein the method of forming the spacer comprises: forming a layer of isolation material between adjacent ones of the active regions and on the first face; and carrying out planarization treatment on the isolation material layer until the first surface is exposed, so as to form the isolation layer.
18. The method of forming a dynamic random access memory of claim 15, further comprising, after forming the word line gate trench and before forming the initial word line gate structure: forming a flat layer at the bottom of the word line grating groove; the word line gate structure is located on the planarization layer.
19. The method of claim 18, wherein forming a planarization layer at the bottom of the word line gate trench comprises: forming a flat material layer at the bottom of the word line grating groove by adopting a spin coating process, wherein the flat material layer is fluid; and curing the flat material layer to form the flat layer.
20. The method of claim 18, wherein the material of the planarization layer comprises an insulating dielectric material; the insulating dielectric material comprises: and (3) silicon oxide.
21. The method of claim 15, wherein a depth of the second source drain doped region is greater than or equal to a spacing between the word line gate structure and the second side of the substrate.
22. The method of forming a dynamic random access memory of claim 15, wherein said word line gate structure comprises: and the word line grating medium layer is positioned on the side wall and the bottom surface of the word line grating groove, and the word line grating layer is positioned on the word line grating medium layer.
23. The method of forming a dynamic random access memory of claim 22, wherein said word line gate layer comprises: a single layer structure or a composite structure.
24. The method of claim 23, wherein when the word line gate layer has a single layer structure, the material of the word line gate layer comprises: metal or polysilicon.
25. The method of claim 23, wherein when the word line gate layer is a composite structure, the word line gate layer comprises a first gate layer and a second gate layer on the first gate layer, the first gate layer and the second gate layer being of different materials.
26. The method of forming a dynamic random access memory of claim 25, wherein the material of the first gate layer comprises: metal or polysilicon; the material of the second gate layer includes: polysilicon or metal.
27. The method of claim 15, wherein a spacing between the first isolation structure and the second surface is less than or equal to a spacing between the word line gate structure and the second surface.
28. The method of forming a dynamic random access memory of claim 15, further comprising, prior to forming the plurality of capacitor structures: and forming a first conductive plug on each first source-drain doped region, wherein each capacitor structure is electrically connected with one first conductive plug.
29. The method of forming a dynamic random access memory of claim 15, further comprising, prior to forming a plurality of said bit line layers: and forming a plurality of second conductive plugs, wherein each bit line layer is electrically connected with a plurality of second source-drain doped regions in a corresponding active region through the plurality of second conductive plugs.
30. The method of forming a dynamic random access memory of claim 15, wherein said capacitor structure comprises: an upper electrode layer, a lower electrode layer, and a dielectric layer between the upper electrode layer and the lower electrode layer.
31. The method of claim 15, wherein the first isolation opening and the second isolation opening are formed simultaneously or not.
32. The method of forming a dynamic random access memory of claim 15, wherein the method of forming the first isolation structure and the second isolation structure comprises: forming a layer of isolation material within the first isolation opening, within the second isolation opening, and on the first face; and flattening the isolation material layer until the first surface is exposed, so as to form the first isolation structure and the second isolation structure.
CN202111028397.1A 2021-09-02 2021-09-02 Dynamic random access memory and forming method thereof Active CN113707660B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202111028397.1A CN113707660B (en) 2021-09-02 2021-09-02 Dynamic random access memory and forming method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202111028397.1A CN113707660B (en) 2021-09-02 2021-09-02 Dynamic random access memory and forming method thereof

Publications (2)

Publication Number Publication Date
CN113707660A CN113707660A (en) 2021-11-26
CN113707660B true CN113707660B (en) 2024-04-05

Family

ID=78657741

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202111028397.1A Active CN113707660B (en) 2021-09-02 2021-09-02 Dynamic random access memory and forming method thereof

Country Status (1)

Country Link
CN (1) CN113707660B (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114121961B (en) * 2021-11-29 2024-04-05 芯盟科技有限公司 Dynamic random access memory and forming method thereof
CN114023743B (en) * 2022-01-05 2022-04-22 芯盟科技有限公司 Semiconductor structure and method for forming semiconductor structure
CN114220765B (en) * 2022-02-22 2022-06-21 芯盟科技有限公司 Memory and manufacturing method thereof

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6184080B1 (en) * 1998-09-04 2001-02-06 Texas Instruments Incorporated Method of the simultaneous formation for the storage node contacts, bit line contacts, and the contacts for periphery circuits
KR20010091733A (en) * 2000-03-17 2001-10-23 후 훙-치우 Structure of dram with vertical transistor and method of fabricating the same
CN110265398A (en) * 2019-06-28 2019-09-20 芯盟科技有限公司 Memory and forming method thereof
CN112071841A (en) * 2020-09-17 2020-12-11 芯盟科技有限公司 Semiconductor structure and forming method thereof
CN112864158A (en) * 2021-04-07 2021-05-28 芯盟科技有限公司 Dynamic random access memory and forming method thereof
CN112909001A (en) * 2021-04-07 2021-06-04 芯盟科技有限公司 Dynamic random access memory and forming method thereof
CN112951828A (en) * 2021-04-07 2021-06-11 芯盟科技有限公司 Semiconductor structure and forming method thereof
CN113192956A (en) * 2021-06-29 2021-07-30 芯盟科技有限公司 Dynamic random access memory and forming method thereof

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6750499B2 (en) * 2002-08-06 2004-06-15 Intelligent Sources Development Corp. Self-aligned trench-type dram structure and its contactless dram arrays
US10535659B2 (en) * 2017-09-29 2020-01-14 Samsung Electronics Co., Ltd. Semiconductor memory devices

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6184080B1 (en) * 1998-09-04 2001-02-06 Texas Instruments Incorporated Method of the simultaneous formation for the storage node contacts, bit line contacts, and the contacts for periphery circuits
KR20010091733A (en) * 2000-03-17 2001-10-23 후 훙-치우 Structure of dram with vertical transistor and method of fabricating the same
CN110265398A (en) * 2019-06-28 2019-09-20 芯盟科技有限公司 Memory and forming method thereof
CN112071841A (en) * 2020-09-17 2020-12-11 芯盟科技有限公司 Semiconductor structure and forming method thereof
CN112864158A (en) * 2021-04-07 2021-05-28 芯盟科技有限公司 Dynamic random access memory and forming method thereof
CN112909001A (en) * 2021-04-07 2021-06-04 芯盟科技有限公司 Dynamic random access memory and forming method thereof
CN112951828A (en) * 2021-04-07 2021-06-11 芯盟科技有限公司 Semiconductor structure and forming method thereof
CN113192956A (en) * 2021-06-29 2021-07-30 芯盟科技有限公司 Dynamic random access memory and forming method thereof

Also Published As

Publication number Publication date
CN113707660A (en) 2021-11-26

Similar Documents

Publication Publication Date Title
CN112864158B (en) Dynamic random access memory and forming method thereof
CN113707660B (en) Dynamic random access memory and forming method thereof
CN112909001B (en) Dynamic random access memory and forming method thereof
CN112071841A (en) Semiconductor structure and forming method thereof
US9048293B2 (en) Semiconductor device and method for manufacturing the same
CN114121961B (en) Dynamic random access memory and forming method thereof
CN113192956B (en) Dynamic random access memory and forming method thereof
CN115701210A (en) Semiconductor structure and manufacturing method thereof
CN114121821A (en) Method for forming dynamic random access memory
CN113437068B (en) Dynamic random access memory and forming method thereof
CN115295550A (en) Semiconductor structure and forming method thereof
CN115346986B (en) Dynamic random access memory and forming method thereof
CN115377108B (en) Dynamic random access memory and forming method thereof
CN113540094A (en) Semiconductor structure and forming method thereof
CN113437069B (en) Dynamic random access memory and forming method thereof
CN115295549A (en) Semiconductor structure and forming method thereof
CN115295496A (en) Semiconductor device, manufacturing method thereof, memory and storage system
CN113517292A (en) Semiconductor structure and forming method thereof
CN115312519B (en) Dynamic random access memory and forming method thereof
CN116137781A (en) Memory and forming method thereof
KR100570219B1 (en) Double gate line of the semiconductor and method for manufacturing thereof
EP4369881A1 (en) Semiconductor structure, and manufacturing method for semiconductor structure
US20230389261A1 (en) Semiconductor structure and method for forming semiconductor structure
CN117062437A (en) Dynamic random access memory, forming method and working method thereof
TW202415232A (en) Semiconductor structure and manufacturing method thereof

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant