CN112071841A

CN112071841A - Semiconductor structure and forming method thereof

Info

Publication number: CN112071841A
Application number: CN202010980690.7A
Authority: CN
Inventors: 王喜龙; 薛迎飞
Original assignee: ZHEJIANG TSINGHUA YANGTZE RIVER DELTA RESEARCH INSTITUTE; ICLeague Technology Co Ltd
Current assignee: ZHEJIANG TSINGHUA YANGTZE RIVER DELTA RESEARCH INSTITUTE; ICLeague Technology Co Ltd
Priority date: 2020-09-17
Filing date: 2020-09-17
Publication date: 2020-12-11

Abstract

A semiconductor structure and a forming method thereof are provided, wherein the method comprises the following steps: the first substrate is provided with a first surface and a second surface which are opposite, the first substrate is internally provided with a plurality of first doping regions and second doping regions which are overlapped and arranged along the direction vertical to the surface of the first substrate and are mutually separated, and the first surface is exposed out of the surface of the first doping region; the grid electrode is positioned in the first substrate, extends from the first surface to the second surface, and penetrates through 1 first doping region and 1 second doping region; a number of word lines on the first side; a plurality of bit lines on the first side; and the projection of each capacitor on the second surface is at least partially coincided with the projections of the 1 second doping region on the second surface. Therefore, the manufacturing process difficulty of the memory is reduced, and the storage capacity of the memory is improved.

Description

Semiconductor structure and forming method thereof

Technical Field

The present invention relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.

Background

With the rapid development of technology, semiconductor memories are widely used in electronic devices. Dynamic Random Access Memory (DRAM), which is a volatile memory, is the most commonly utilized solution for applications that store large amounts of data.

Generally, a dram is composed of a plurality of memory cells, each of which is mainly composed of a transistor and a capacitor operated by the transistor, and each of the memory cells is electrically connected to each other through a word line and a bit line.

However, in the conventional memory structure, since the capacitor, the bit line and the conductive structure connected to the bit line are further provided between the word line and the transistor, in order to connect the capacitor and the word line and the transistor, the capacitor structure, the bit line and the conductive structure connected to the bit line need to be formed to be away from each other, which results in a complicated circuit wiring and a difficult manufacturing process in the memory array region of the memory.

Furthermore, on the one hand, since the circuit wiring in the memory array region is complicated, the circuits other than the capacitor occupy a large area, which leads to a decrease in the storage density of the memory and a reduction in the storage capacity of the capacitor. On the other hand, since the structure of the capacitor is also affected by the structure of the logic circuit of the memory, for example, the height of a plug connecting different circuits in the logic circuit, the height of the capacitor is limited, the area of the capacitor is small, and the storage capacity of the capacitor is also small.

Disclosure of Invention

The invention provides a semiconductor structure and a forming method thereof, which aims to reduce the manufacturing process difficulty of a memory and improve the storage capacity of the memory.

To solve the above technical problem, an aspect of the present invention provides a semiconductor structure, including: the first substrate is provided with a first surface and a second surface which are opposite, the first substrate is internally provided with a plurality of first doping regions and second doping regions which are overlapped and arranged along the direction vertical to the surface of the first substrate and are mutually separated, and the first surface is exposed out of the surface of the first doping region; the grid electrode is positioned in the first substrate, the grid electrode extends from the first surface to the second surface, each grid electrode penetrates through 1 first doped region and 1 second doped region, the grid electrode comprises an electrode layer and a dielectric layer positioned between the electrode layer and the first substrate, and the first surface is exposed out of the top surface of the electrode layer; a plurality of word lines on the first side, each word line on a top surface of at least 1 electrode layer; the bit lines are positioned on the first surface, each bit line is also at least positioned on the surface of 1 first doping region, and the word lines and the bit lines are insulated; and the projection of each capacitor on the second surface is at least partially coincided with the projections of the 1 second doping region on the second surface.

Optionally, the capacitor includes a first capacitor electrode layer, a capacitor dielectric layer located on a surface of the first capacitor electrode layer, and a second capacitor electrode layer located on a surface of the capacitor dielectric layer.

Optionally, the first substrate has a plurality of capacitor openings therein, projections of the capacitor openings on the second surface are at least partially overlapped with projections of the 1 second doped regions on the second surface, and the first capacitor electrode layer is located on an inner wall surface of the capacitor openings.

Optionally, the method further includes: and the isolation structure is positioned in the first substrate, extends from the first surface to the second surface, is positioned between the adjacent first doping regions, is also positioned between the adjacent second doping regions, and exposes the top surface of the isolation structure.

Optionally, a plurality of the word lines extend along a first direction, a plurality of the bit lines extend along a second direction, and the first direction and the second direction are perpendicular to each other.

Optionally, the gates are arranged in an array along the first direction and the second direction, each word line is located on a top surface of an electrode layer of 1 column of gates arranged along the first direction, and each bit line crosses 1 row of gates in the second direction.

Optionally, the method further includes: a first dielectric structure on the first side, the first dielectric structure surface being higher than the word line surface.

Optionally, the first dielectric structure has a plurality of second openings therein, each second opening exposes at least a part or all of the surface of 1 first doped region, and the bit line is located in the second opening and on the surface of the first dielectric structure.

Optionally, the first substrate includes a storage region, and the word line, the bit line, the gate, and the capacitor are located in the storage region.

Optionally, the first substrate further includes a first logic area, the first substrate further has a first logic circuit therein, and the first logic circuit is located in the first logic area.

Optionally, the first logic circuit includes 1 or more of a row address decoder, a data input buffer, a data output buffer, a sense amplifier, a column address decoder, and a driving circuit.

Optionally, the method further includes: and the second substrate is bonded with the first substrate, the second substrate is provided with a functional surface and a non-functional surface which are opposite, the first surface faces the functional surface, and the second substrate is internally provided with a second logic circuit which is electrically connected with the first logic circuit.

Optionally, the method further includes: a second dielectric structure on the bit line surface and the first side, the second dielectric structure surface being higher than the bit line surface; the first conducting layer is positioned in the second dielectric structure, the first conducting layer is exposed out of the surface of the second dielectric structure, and the first conducting layer is respectively connected with the first logic circuit and the second logic circuit.

Optionally, the method further includes: and the second substrate is bonded with the first substrate, the second substrate is provided with a functional surface and an nonfunctional surface which are opposite, the first surface faces the functional surface, and the second substrate is internally provided with a second logic circuit which is electrically connected with the bit line.

Optionally, the method further includes: a second dielectric structure on the bit line surface and the first side, the second dielectric structure surface being higher than the bit line surface; and the first conducting layer is positioned in the second dielectric structure, is connected with the bit line, and is exposed on the surface of the second dielectric structure.

Optionally, the method further includes: a third media construction on the functional side; and the second conducting layer is positioned in the third dielectric structure and is electrically connected with the second logic circuit, the second interconnection layer is exposed on the surface of the third dielectric structure, and the projection of the first conducting layer on the first surface is at least partially overlapped with the projection of the second conducting layer on the first surface.

Optionally, the second logic circuit includes 1 or more of a row address decoder, a data input buffer, a data output buffer, a sense amplifier, a column address decoder, and a driving circuit.

Correspondingly, the technical scheme of the invention also provides a forming method for forming the semiconductor structure, which comprises the following steps: providing a first substrate, wherein the first substrate is provided with a first surface and a second surface which are opposite, the first substrate is internally provided with a plurality of first doping regions and second doping regions which are overlapped and arranged along the direction vertical to the surface of the first substrate and are mutually separated, and the surface of the first doping region is exposed out of the first surface; forming a plurality of grids extending from the first surface to the second surface in the first substrate, wherein each grid penetrates through 1 first doped region and 1 second doped region, each grid comprises an electrode layer and a dielectric layer positioned between the electrode layer and the first substrate, and the first surface is exposed out of the top surface of the electrode layer; forming a plurality of word lines on the first surface, wherein each word line is positioned on the top surface of at least 1 electrode layer; forming a plurality of bit lines on the first surface, wherein each bit line is at least positioned on the surface of 1 first doping region, and the word lines and the bit lines are insulated; and forming a plurality of capacitors on the second surface, wherein the projection of each capacitor on the second surface is at least partially overlapped with the projection of the 1 second doping region on the second surface.

Optionally, the method for forming the capacitor includes: after forming a plurality of word lines and bit lines, etching the second surface, and forming a plurality of capacitor openings in the first substrate, wherein projections of the capacitor openings on the second surface are at least partially overlapped with projections of the 1 second doping area on the second surface; forming the first capacitance electrode layer on an inner wall surface of each capacitance opening; forming a capacitance dielectric layer on the surface of the first capacitance electrode layer; and forming a second capacitance electrode layer on the surface of the capacitance dielectric layer.

Optionally, the method further includes: the second face is thinned after forming the word lines and bit lines and before forming the capacitance openings.

Optionally, the first substrate further has an isolation structure therein, the isolation structure extends from the first surface toward the second surface, the isolation structure is located between the adjacent first doped regions, the isolation structure is also located between the adjacent second doped regions, and the first surface exposes the top surface of the isolation structure.

Optionally, the method for forming the gate includes: etching the first surface, and forming a plurality of first openings in the first substrate, wherein each first opening penetrates through 1 first doping region and 1 second doping region; forming a dielectric material layer on the first opening and the first surface; forming an electrode material layer on the surface of the dielectric material layer, wherein the surface of the electrode material layer is higher than the first surface; forming a plurality of first mask structures on the surface of the electrode material layer, wherein each first mask structure covers at least 1 first opening and exposes at least part of the surface of the electrode material layer on the first doping region; and etching the electrode material layer and the dielectric material layer by taking the first mask structures as masks until the first surface is exposed.

Optionally, the method for forming a plurality of word lines includes: forming a word line material layer on the surface of the electrode material layer before forming a plurality of first mask structures; before etching the electrode material layer, etching the word line material layer by taking the first mask structures as masks until the surface of the electrode material layer is exposed.

Optionally, the method further includes: after the word line is formed, a first dielectric structure is formed on the first surface before the bit line is formed, and the surface of the first dielectric structure is higher than the surface of the word line.

Optionally, the method for forming the bit line includes: forming a plurality of second openings in the first dielectric structure, wherein each second opening at least exposes partial or all surfaces of 1 first doping region; forming a bit line material layer in the second opening and on the surface of the first dielectric structure; forming a plurality of second mask structures on the surface of the bit line material layer, wherein each second mask structure covers at least 1 second opening; and etching the bit line material layer by taking the second mask structure as a mask until the surface of the first dielectric structure is exposed.

Optionally, the method further includes: after forming the gates and word lines, and before forming bit lines, contact layers are formed on the surfaces of the first doped regions.

Optionally, the top surface of the electrode layer is higher than the first surface; the method for forming the semiconductor structure further comprises the following steps: and before the contact layer is formed, forming a side wall on the side wall surface of the electrode layer on the first surface.

Optionally, the extending direction of the bit line is perpendicular to the extending direction of the word line.

Optionally, the method further includes: providing a second substrate having a second logic circuit therein, the second substrate further having opposing functional and non-functional sides; bonding the first substrate and a second substrate after forming the gate, the word line, and the bit line and before forming the capacitor, the first surface facing the functional surface, and the second logic circuit being electrically connected to the first logic circuit.

Optionally, the method further includes: further comprising: forming a second dielectric structure on the bit line surface and the first face after forming the gate, the word line, and the bit line and before bonding the first substrate and the second substrate, the second dielectric structure surface being higher than the bit line surface; and forming a first conductive layer in the second dielectric structure, wherein the first conductive layer is connected with the first logic circuit, and the first conductive layer is exposed out of the surface of the second dielectric structure.

Optionally, the method further includes: providing a second substrate having a second logic circuit therein, the second substrate further having opposing functional and non-functional sides; bonding the first substrate and a second substrate after forming the gate, the word line, and the bit line and before forming the capacitor, the first surface facing the functional surface, and the second logic circuit being electrically connected to the bit line.

Optionally, the method further includes: forming a second dielectric structure on the bit line surface and the first face after forming the gate, the word line, and the bit line and before bonding the first substrate and the second substrate, the second dielectric structure surface being higher than the bit line surface; and forming a first conductive layer in the second dielectric structure, wherein the first conductive layer is connected with the bit line, and the first conductive layer is exposed out of the surface of the second dielectric structure.

Optionally, the method further includes: forming a third dielectric structure on the functional side prior to bonding the first substrate to the second substrate; and forming a second conducting layer in the third dielectric structure, wherein the second conducting layer is electrically connected with the second logic circuit, the second conducting layer is exposed from the surface of the third dielectric structure, and after the first substrate is bonded with the second substrate, the projection of the first conducting layer on the first surface is at least partially overlapped with the projection of the second conducting layer on the first surface.

Compared with the prior art, the technical scheme of the invention has the following beneficial effects:

in the method for forming a semiconductor structure provided by the technical scheme of the invention, a plurality of grids extending from a first surface to a second surface are formed in the first substrate, word lines are formed on the top surface of the electrode layer exposed from the first surface, bit lines are formed on the surface of the first doped region exposed from the first surface, a plurality of capacitors are formed on the second surface, and the projection of each capacitor on the second surface is at least partially overlapped with the projection of 1 second doped region on the second surface, so that on one hand, the structural association degree between the capacitors and the word lines and between the capacitors and the bit lines is small, thereby simplifying the wiring structures of the word lines and the bit lines, and the capacitors can be connected with the second doped region through a simple structure, thereby reducing the difficulty of the manufacturing process of the memory; on the other hand, since the capacitor is formed on the second surface, the occupied area of the wiring structure is reduced, and thus, the space for forming the capacitor can be increased, and further, the storage density of the memory and the storage capacity of the memory are improved.

Drawings

Fig. 1 to 20 are schematic structural diagrams of steps in a method for forming a semiconductor structure according to an embodiment of the invention.

Detailed Description

As described in the background art, in the conventional memory structure, since the capacitor, the bit line and the conductive structure connected to the bit line are further provided between the word line and the transistor, in order to connect the capacitor and the word line and the transistor, the capacitor structure, the bit line and the conductive structure connected to the bit line need to be formed to be away from each other, which results in complicated circuit wiring and great difficulty in manufacturing process in the memory array region of the memory.

In order to solve the above technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, in which word lines and bit lines are formed on a first surface of a first substrate, and capacitors are formed on a second surface of the first substrate. Therefore, the manufacturing process difficulty of the memory is reduced, and the storage capacity of the memory is improved.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

It should be noted that "surface" in this specification is used to describe a relative positional relationship in space, and is not limited to whether or not it is in direct contact.

Referring to fig. 1 and fig. 2, fig. 1 is a schematic top view structure along a direction a in fig. 2, fig. 2 is a schematic cross-sectional structure along a direction B1-B2 in fig. 1, a first substrate 100 is provided, the first substrate 100 has a first side 101 and a second side 102 opposite to each other, the first substrate 100 further has a plurality of first doped regions 103 and second doped regions 104 arranged in an overlapping manner along a direction perpendicular to a surface of the first substrate 100 and separated from each other, and the first side 101 exposes the surface of the first doped regions 103.

In this embodiment, the first substrate 100 further has an isolation structure 105 therein, the isolation structure 105 extends from the first surface 101 toward the second surface 102, the isolation structure 105 is located between adjacent first doped regions 103, the isolation structure 105 is further located between adjacent second doped regions 104, and the first surface 101 exposes a top surface of the isolation structure 105.

In this embodiment, the method for forming the first doped region 103, the second doped region 104 and the isolation structure 105 includes: providing a substrate (not shown); forming an initial doping layer (not shown) on the substrate by using an epitaxial growth process, wherein the initial doping layer is internally provided with first ions; performing an ion implantation process on the top of the initial doped layer to form a second doped layer and a first doped layer located on the second doped layer, wherein the second doped layer is a part of the initial doped layer which is not subjected to the ion implantation process, the first doped layer is the initial doped layer (not shown) after the ion implantation process, second ions are contained in the second doped layer, and the conductivity types of the first ions and the second ions are opposite; etching the first doping layer and the second doping layer, and forming an isolation opening (not shown) in the first doping layer and the second doping layer, wherein the isolation opening penetrates through the first doping layer and extends into the second doping layer; an isolation structure 105 is formed in the isolation opening, and at the same time, a plurality of mutually separated first doping regions 103 and second doping regions 104 are formed.

In other embodiments, the isolation structure further extends into the first substrate between the second doped region and the second face.

The substrate is made of a semiconductor material. In this embodiment, the substrate is made of silicon. In other embodiments, the substrate material comprises silicon carbide, silicon germanium, a multi-component semiconductor material of group iii-v elements, silicon-on-insulator (SOI), or germanium-on-insulator. The multielement semiconductor material formed by III-V group elements comprises InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

In other embodiments, after the gate and the sidewall are formed in the subsequent step, an ion implantation process may be performed on the initial doping layer to form the first doping region and the second doping region.

In this embodiment, the first substrate 100 includes a storage region I, and the isolation structure 105, the first doped region 103, and the second doped region 104 are located in the storage region I.

In this embodiment, the first substrate 100 further has a first logic circuit (not shown), the first substrate 100 further includes a first logic area (not shown), and the first logic circuit is located in the first logic area.

In this embodiment, the first logic circuit includes 1 or more of a row address decoder, a data input buffer, a data output buffer, a sense amplifier, a column address decoder, and a driving circuit.

In another embodiment, the first logic circuit is electrically connected to a subsequently formed bit line.

In other embodiments, the first substrate does not include the first logic region and does not have the first logic circuit.

Next, a plurality of gates extending from the first surface 101 toward the second surface 102 are formed in the first substrate 100, each gate penetrates through 1 first doped region 103 and 1 second doped region 104, the gate includes an electrode layer and a dielectric layer located between the electrode layer and the first substrate 100, the first surface 101 exposes a top surface of the electrode layer, and a plurality of word lines are formed on the first surface 101, each word line is located on a top surface of at least 1 electrode layer. In particular, please refer to fig. 3 to 8 for the process of forming the gate and the word line.

Referring to fig. 3 and 4, fig. 3 is a schematic top view along a direction a in fig. 4, fig. 4 is a schematic cross-sectional view along a direction B1-B2 in fig. 3, a first opening patterning layer (not shown) is formed on the first surface 101, and the first opening patterning layer exposes a portion of the surface of the first doped region 103; and etching the first surface 101 by using the first opening patterning layer as a mask, and forming a plurality of first openings 106 in the first substrate 100, wherein each first opening 106 penetrates through 1 first doping region 103 and 1 second doping region 104.

In this embodiment, the process for etching the first surface 101 includes at least one of a dry etching process and a wet etching process.

In this embodiment, after the first opening 106 is formed, the first opening patterning layer is removed.

In this embodiment, the first openings 106 are arranged in an array along a first direction X and a second direction Y, and the first direction X and the second direction Y are perpendicular to each other.

It should be noted that, for convenience of illustration, fig. 4 only schematically illustrates 6 first openings 106 arranged in 3 columns along the first direction X and 2 rows along the second direction Y. The number and arrangement of the first openings 106 are designed according to actual requirements for storage capacity, wiring structure, and the like.

Referring to fig. 5 and fig. 6, fig. 4 is a schematic top view along direction a in fig. 5, fig. 5 is a schematic cross-sectional view along direction B1-B2 in fig. 4, and a dielectric material layer 110 is formed on the first opening 106 and the first side 101; forming an electrode material layer 120 on the surface of the dielectric material layer 110, wherein the first opening 106 is filled with the electrode material layer 120; a plurality of first mask structures 132 are formed on the surface of the electrode material layer 120, and each first mask structure 132 covers at least 1 first opening 106 and exposes at least a portion of the surface of the electrode material layer 120 on the first doped region 103.

In the present embodiment, the surface of the electrode material layer 120 is higher than the first surface 101.

For convenience of description, in the present embodiment, each first mask structure 132 is used to cover 1 column of the first openings 106 arranged along the first direction X.

The dielectric material layer 110 provides material for the subsequent formation of a dielectric layer.

The material of the dielectric material layer 110 includes silicon oxide or other dielectric materials. Correspondingly, the material of the dielectric layer comprises silicon oxide or other dielectric materials.

In this embodiment, the dielectric material layer 110 is made of silicon oxide. Correspondingly, the dielectric layer is made of silicon oxide.

In the present embodiment, the process of forming the dielectric material layer 110 includes an oxidation process, a deposition process, and the like, and the deposition process is, for example, a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, and the like.

The electrode material layer 120 provides material for the subsequent formation of an electrode layer.

The material of the electrode material layer 120 includes polysilicon or a metal material layer. Correspondingly, the material of the electrode layer comprises polysilicon or a metal material layer.

In this embodiment, the material of the electrode material layer 120 is polysilicon. Correspondingly, the material of the electrode layer is polysilicon.

In the present embodiment, the process of forming the electrode material layer 120 includes an epitaxial growth process, a metal plating process, a selective metal growth process, a deposition process, and the like, and the deposition process is, for example, a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, and the like.

In the present embodiment, before forming a plurality of the first mask structures 132, a word line material layer 130 is formed on the surface of the electrode material layer 120.

The word line material layer 130 provides material for the subsequent formation of word lines.

The process of forming the word line material layer 130 includes a metal plating process, a selective metal growth process, a deposition process, and the like, and the deposition process includes a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, and the like.

The material of the word line material layer 130 includes a metal material, such as tungsten, aluminum, copper, and the like. Accordingly, the material of the word line includes a metal material, such as tungsten, aluminum, copper, and the like.

In the present embodiment, the material of the word line material layer 130 is tungsten. Correspondingly, the material of the word line is tungsten.

In the present embodiment, the electrode material layer 120 is planarized before the word line material layer 130 is formed. Accordingly, the flatness of the surface of the electrode material layer 120 is improved, thereby facilitating the formation of the word line material layer 130 with better quality and the improvement of the pattern precision of the first mask structure 132.

In the present embodiment, the process of planarizing the electrode material layer 120 includes a chemical mechanical polishing process.

In this embodiment, the method for forming the first mask structure 132 includes: forming a first mask structure material layer (not shown) on the surface of the word line material layer 130; the first mask structure material layer is patterned to form the first mask structure 132.

Referring to fig. 7 and 8, fig. 7 is a schematic top view along a direction a in fig. 8, fig. 8 is a schematic cross-sectional view along a direction B1-B2 in fig. 7, the word line material layer 130 is etched using a plurality of first mask structures 132 as masks until the surface of the electrode material layer 120 is exposed, and a plurality of word lines 131 are formed on the first surface 101; after a plurality of word lines 131 are formed, the first mask structure 132 is continuously used as a mask to etch the electrode material layer 120 and the dielectric material layer 110 until the first surface 101 is exposed, so as to form a gate 122, wherein the gate 122 includes an electrode layer 121 and a dielectric layer 111, and each word line 131 is located on the top surface of at least 1 electrode layer 121.

The gate 122 is located within the first substrate 100 and extends from the first side 101 towards the second side 102. Each gate 122 penetrates 1 first doping region 103 and 1 second doping region 104.

The first surface 101 exposes a top surface of the electrode layer 121. In this embodiment, the top surface of the electrode layer 121 is higher than the first surface 101.

The dielectric layer 111 is located between the electrode layer 121 and the first substrate 100.

In this embodiment, the plurality of gates 122 are arranged in an array along the first direction X and the second direction Y, the plurality of word lines 131 extend along the first direction X, and each word line 131 is located on the top surface of the electrode layer 121 with 1 column of gates 122 arranged along the first direction X.

For convenience of description, fig. 7 only schematically illustrates 6 gates 122 arranged in 3 columns along the first direction X and 2 rows along the second direction Y, and 1 column of the gates 122 arranged along the first direction X are connected to each other at the first surface 101. The number, arrangement, and connection of the plurality of gates 122 on the first surface 101 are designed according to actual requirements for storage capacity, wiring structure, and the like.

In this embodiment, the process of etching the word line material layer 130, the electrode material layer 120 and the dielectric material layer 110 includes at least one of a dry etching process and a wet etching process.

In the present embodiment, the word line 131 and the gate 122 are located in the storage region I.

Referring to fig. 9, the view directions of fig. 9 and fig. 8 are the same, and a sidewall 123 is formed on the sidewall of the electrode layer 121 on the first surface 101; after the side walls 123 are formed, a contact layer 124 is formed on the surfaces of the first doped regions 103.

In this embodiment, the method for forming the sidewall spacers 123 includes: depositing a spacer material layer (not shown) on the surface of the electrode layer 121, the surface of the word line 131, and the first surface 101; and etching back the side wall material layer to form the side wall 123.

In this embodiment, the sidewall spacers 123 are also located on the sidewall surfaces of the word lines 131.

The insulating property between the gate 122 and the word line 131 and the bit line formed later can be further enhanced by the sidewall spacers 123.

In this embodiment, the material of the sidewall spacers 123 includes silicon oxide.

In this embodiment, the process of etching back the spacer material layer includes an anisotropic dry etching process.

In this embodiment, the material of the contact layer 124 is a metal silicide.

The process of forming the contact layer 124 includes a combination of one or more of a metal plating process, a selective metal growth process, a deposition process and an annealing process, for example, a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, and the like.

By forming the contact layer 124, a contact area with the first doped region 103 can be increased, thereby reducing a contact resistance between a subsequently formed bit line and the first doped region 103.

Referring to fig. 10, fig. 10 is a view in the same direction as fig. 9, after the word line 131 is formed, and before the bit line is formed subsequently, a first dielectric structure 140 is formed on the first surface 101, wherein the surface of the first dielectric structure 140 is higher than the surface of the word line 131.

In one aspect, the first dielectric structure 140 is used to insulate the word line 131 from a subsequently formed bit line; on the other hand, the first dielectric structure 140 is also used to provide support for the subsequent formation of bit lines.

In the present embodiment, the process of forming the first dielectric structure 140 includes a deposition process or a spin-on process, and the deposition process is at least one of a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

In this embodiment, the material of the first dielectric structure 140 includes silicon oxide.

Next, bit lines are formed on the first surface 101, each bit line is also at least located on the surface of 1 first doping region 103, and a plurality of word lines 131 are insulated from the bit lines. Please refer to fig. 11 to fig. 15 for a process of forming the bit lines.

Referring to fig. 11, in a view direction consistent with that of fig. 10, a plurality of second openings 141 are formed in the first dielectric structure 140, and each of the second openings 141 exposes at least a part or all of the surfaces of 1 first doping region 103.

The second opening 141 provides a space for a bit line to be formed later.

In this embodiment, since the contact layer 124 is formed on the surface of the first doped region 103, each second opening 141 exposes at least a part or all of the surface of 1 first doped region 103, which means that each second opening 141 exposes at least a part or all of the surface of the contact layer 124 on 1 first doped region 103.

The method of forming the second opening 141 includes: forming a second opening mask layer (not shown) on the surface of the first dielectric structure 140, wherein the second opening mask layer exposes a portion of the surface of the first dielectric structure 140; and etching the first dielectric structure 140 by using the second opening mask layer as a mask until the surface of the contact layer 124 is exposed.

The process for etching the first dielectric structure 140 includes at least one of a dry etching process or a wet etching process.

In the present embodiment, the first dielectric structure 140 is planarized before the second opening 141 is formed. Therefore, the flatness of the surface of the first dielectric structure 140 is improved, which is beneficial to improving the pattern precision of the second opening 141 and is beneficial to filling the material of the bit line material layer in the second opening 141 subsequently.

In the present embodiment, the process of planarizing the first dielectric structure 140 includes a chemical mechanical polishing process.

In this embodiment, after the second opening 141 is formed, the second opening mask layer is removed.

Referring to fig. 12 and 13, fig. 12 is a schematic top view along direction a in fig. 13, and fig. 13 is a schematic cross-sectional view along direction B1-B2 in fig. 12, wherein a bit line material layer 150 is formed in the second opening 141 and on the surface of the first dielectric structure 140; a plurality of second mask structures 152 are formed on the surface of the bit line material layer 150, and each second mask structure 152 covers at least 1 second opening 141.

In this embodiment, the second mask structure 152 extends along the second direction Y, and the second mask structure 152 further covers at least 1 first opening 106.

For convenience of description, in the present embodiment, each of the second mask structures 152 is used to cover 1 row of the first openings 106 arranged along the second direction Y.

The bit line material layer 150 provides material for the subsequent formation of bit lines.

The process of forming the bit line material layer 150 includes a metal plating process, a selective metal growth process, a deposition process, and the like, and the deposition process includes a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, and the like.

The material of the bit line material layer 150 includes a metal material, such as tungsten, aluminum, copper, and the like. Accordingly, the material of the bit line includes a metal material, such as tungsten, aluminum, copper, and the like.

In the present embodiment, the material of the bit line material layer 150 is tungsten. Correspondingly, the material of the bit line is tungsten.

In this embodiment, the method for forming the second mask structure 152 includes: forming a second masking structure material layer (not shown) on the surface of the bit line material layer 150; the second mask structure material layer is patterned to form the second mask structure 152.

Referring to fig. 14 and 15, fig. 14 is a schematic top view along a direction a in fig. 15, fig. 15 is a schematic cross-sectional view along a direction B1-B2 in fig. 14, the second mask structure 152 is used as a mask, the bit line material layer 150 is etched until the surface of the first dielectric structure 140 is exposed, a plurality of bit lines 151 are formed on the first surface 101, each bit line 151 is further located on at least 1 surface of the first doped region 103, and a plurality of word lines 131 are insulated from the bit lines 151.

In the present embodiment, the bit lines 151 extend in a second direction Y, the extending direction of the bit lines 151 and the extending direction of the word lines 131 are perpendicular to each other, and each bit line 151 crosses 1 row of the gates 122 in the second direction Y.

In other embodiments, the extending directions of the word lines and the bit lines are not perpendicular to each other.

In the present embodiment, the bit line 151 is located in the storage region I.

In this embodiment, the process of etching the bit line material layer 150 includes at least one of a dry etching process and a wet etching process.

In the present embodiment, after the bit lines 151 are formed, the second mask structure 152 is removed.

Referring to fig. 16, in the view direction of fig. 16 consistent with that of fig. 15, after the gate 122, the word line 131, and the bit line 151 are formed, and before the first substrate 100 and the second substrate are bonded subsequently, a second dielectric structure 160 is formed on the surface of the bit line 151 and the first surface 101, wherein the surface of the second dielectric structure 160 is higher than the surface of the bit line 151; a first conductive layer 161 is formed in the second dielectric structure 161, the first conductive layer 161 is connected to the bit line 151, and the first conductive layer 161 is exposed on the surface of the second dielectric structure 160.

The process of forming the second dielectric structure 160 includes a spin-on process or a deposition process.

In this embodiment, the material of the second dielectric structure 160 includes a dielectric material, such as silicon oxide.

The method of forming the first conductive layer 161 includes: forming a first conductive layer mask structure (not shown) on the surface of the second dielectric structure 160; the first conductive layer mask structure exposes a portion of the surface of the second dielectric structure 160 on the bit line 151; etching the second dielectric structure 160 with the first conductive layer mask structure as a mask until the top surface of the bit line 151 is exposed, thereby forming a first conductive opening (not shown); forming a first conductive material layer (not shown) in the first conductive opening and on the surface of the second dielectric structure 160; planarizing the first conductive material layer until the surface of the second dielectric structure 160 is exposed, forming the first conductive layer 161.

The process of forming the first conductive material layer includes a metal plating process, a selective metal growth process, a deposition process, and the like, and the deposition process includes a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, and the like.

The process for planarizing the first conductive material layer includes a chemical mechanical polishing process or a back etching process.

In this embodiment, after the first conductive layer 161 is formed and before a capacitor opening is formed subsequently, the second surface 102 is thinned.

The process for thinning the second surface 102 includes a physical mechanical polishing process, a chemical mechanical polishing process, a wet etching process, or the like.

Referring to fig. 17, fig. 17 is a view in accordance with fig. 16, and a second substrate 200 is provided, the second substrate 200 having a second logic circuit (not shown) therein, the second substrate 200 further having a functional side 201 and an inactive side 202 opposite to each other.

In this embodiment, the second logic circuit includes 1 or more of a row address decoder, a data input buffer, a data output buffer, a sense amplifier, a column address decoder, and a driving circuit.

With continued reference to fig. 17, a third dielectric structure 210 is formed on the functional surface 201; and forming a second conductive layer 211 in the third dielectric structure 210, wherein the second conductive layer 211 is electrically connected to the second logic circuit, and the second conductive layer 211 is exposed on the surface of the third dielectric structure 210.

The process of forming the third dielectric structure 210 includes a spin-on process or a deposition process.

In the present embodiment, the material of the third dielectric structure 210 includes a dielectric material, such as silicon oxide.

The method of forming the second conductive layer 211 includes: forming a second conductive layer mask structure (not shown) on the surface of the third dielectric structure 210; the second conductive layer mask structure exposes a part of the functional surface 201; taking the second conductive layer mask structure as a mask, etching the third dielectric structure 210 until the functional surface 201 is exposed, and forming a second conductive opening (not shown); forming a second conductive material layer (not shown) in the second conductive opening and on the surface of the third dielectric structure 210; and planarizing the second conductive material layer until the surface of the third dielectric structure 210 is exposed, thereby forming the second conductive layer 211.

The process of forming the second conductive material layer includes a metal plating process, a selective metal growth process, a deposition process, and the like, and the deposition process includes a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, and the like.

The process for planarizing the second conductive material layer includes a chemical mechanical polishing process or a back etching process.

Referring to fig. 18, in the same view direction as fig. 17 in fig. 18, after the gate 122, the word line 131, and the bit line 151 are formed and before the capacitor is formed subsequently, the first substrate 100 and the second substrate 200 are bonded, the first surface 101 faces the functional surface 201, and the second logic circuit is electrically connected to the bit line 151.

Specifically, after the first substrate 100 and the second substrate 200 are bonded, a projection of the first conductive layer 161 on the first surface 101 and a projection of the second conductive layer 211 on the first surface 101 at least partially overlap each other. Thereby, the electrical connection between the first conductive layer 161 and the second conductive layer 211 is achieved, and further, the electrical connection of the second logic circuit and the bit line 151 is achieved.

In another embodiment, the second logic circuit is electrically connected to the first logic circuit. Specifically, after the gate, the word line, and the bit line are formed and before the first substrate and the second substrate are bonded, a second dielectric structure is formed on the bit line surface and the first face, and the second dielectric structure surface is higher than the bit line surface; and forming a first conductive layer in the second dielectric structure, wherein the first conductive layer is connected with the first logic circuit, and the first conductive layer is exposed out of the surface of the second dielectric structure. After the first substrate and the second substrate are bonded, the first conductive layer is connected to the second logic circuit, thereby electrically connecting the second logic circuit to the first logic circuit.

Then, a plurality of capacitors are formed on the second surface 102, and the projection of each capacitor on the second surface 102 is at least partially overlapped with the projection of 1 second doped region 104 on the second surface 102, and each capacitor includes a first capacitor electrode layer, a capacitor dielectric layer located on the surface of the first capacitor electrode layer, and a second capacitor electrode layer located on the surface of the capacitor dielectric layer. Please refer to fig. 19 to fig. 20 for a specific process of forming the capacitor.

Referring to fig. 19, after the second surface 102 is thinned, the second surface 102 is etched, and a plurality of capacitor openings 170 are formed in the first substrate 100, wherein projections of the capacitor openings 170 on the second surface 102 are at least partially overlapped with projections of the 1 second doping region 104 on the second surface 102.

The capacitor opening 170 provides space for subsequent formation of a capacitor.

The method of forming the capacitor opening 170 includes: forming a capacitor opening mask layer (not shown) on the second surface 102, wherein the capacitor opening mask layer exposes a part of the second surface 102; and etching the second surface 102 by using the capacitor opening mask layer as a mask until a plurality of capacitor openings 170 are formed in the first substrate 100.

The process for etching the second surface 102 includes at least one of a dry etching process and a wet etching process.

In this embodiment, after the capacitor opening 170 is formed, the capacitor opening mask layer is removed.

Referring to fig. 20, a first capacitor electrode layer 171 is formed on an inner wall surface of each capacitor opening 170; forming a capacitor dielectric layer 172 on the surface of the first capacitor electrode layer 171; a second capacitance electrode layer 173 is formed on the surface of the capacitance dielectric layer 172 to form a plurality of capacitances on the second surface 102, and the projection of each capacitance on the second surface 102 is at least partially overlapped with the projection of 1 second doping region 104 on the second surface 102.

Specifically, the projection of each capacitor on the second surface 102 is at least partially overlapped with the projection of 1 second doping region 104 on the second surface 102, which means that the projection of the first capacitor electrode layer 171 on the second surface 102 is at least partially overlapped with the projection of 1 second doping region 104 on the second surface 102.

Because a plurality of gates 122 extending from the first surface 101 to the second surface 102 are formed in the first substrate 100, a word line 131 is formed on the top surface of the electrode layer 121 exposed on the first surface 101, a bit line 151 is formed on the surface of the first doped region 103 exposed on the first surface 101, a plurality of capacitors are formed on the second surface 102, and the projection of each capacitor on the second surface 102 is at least partially overlapped with the projection of 1 second doped region 104 on the second surface 102, on one hand, the structural association degree between the capacitor and the word line 131 and between the capacitor and the bit line 151 is small, thereby simplifying the wiring structure of the word line 131 and the bit line 151, and the capacitor can be connected with the second doped region 104 through a simple structure, thereby reducing the difficulty of the manufacturing process of the memory; on the other hand, since the capacitor is formed on the second surface 102, the occupied area of the wiring structure is reduced, and thus, the space for forming the capacitor can be increased, and further, the storage density of the memory and the storage capacity of the memory are improved.

Furthermore, since the capacitor is formed on the second surface 102, when another circuit, such as the first logic circuit, is provided in the first substrate 100, the structural relationship between the capacitor and the other circuit is reduced, so that the limitation of the other circuit on the overall height of the capacitor is reduced, the limitation on the height of the capacitor is smaller, and the storage capacity of the memory can be improved by increasing the height of the capacitor to increase the area of the capacitor. Specifically, the condition that the overall height of the capacitor is limited by the other circuit is, for example, when a conductive plug in the other circuit is formed, in order to reduce defects generated in an etching process for forming an opening of the conductive plug and a material filling process of the conductive plug, a conductive plug with good quality is formed, so that the aspect ratio of the conductive plug is limited, and thus, the height of the capacitor is limited.

In this embodiment, several capacitors are located in the storage region I.

In this embodiment, the method of forming the first capacitor electrode layer 171 includes: depositing a first capacitor electrode material layer (not shown) on the inner wall surface and the second surface 102 of the capacitor opening 170; the first capacitor electrode material layer is planarized until the second surface 102 is exposed.

In this embodiment, the material of the first capacitor electrode layer 171 includes tungsten.

In the present embodiment, the process for forming the capacitor dielectric layer 172 includes at least one of a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

In this embodiment, the material of the capacitor dielectric layer 172 includes a high-k dielectric constant material, aluminum oxide, etc.

In this embodiment, the process of forming the second capacitor electrode layer 173 includes at least one of a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

In this embodiment, the material of the second capacitor electrode layer 173 includes tungsten.

In the present embodiment, each of the gate 122, the first doped region 103 penetrated by the gate 122, the second doped region 104 penetrated by the gate 122, and the portion of the first substrate 100 located between the second doped region 104 and the capacitor constitute 1 trench transistor.

Specifically, the channel of the trench transistor is opened by applying a voltage to the word line 131, so that the first doped region 103, the second doped region 104 and the first substrate 100 between the capacitor and the bit line 151 are conducted, and the capacitor and the bit line 151 are conducted.

In other embodiments, after the second capacitance electrode layer is formed, the capacitance dielectric layer and the second capacitance electrode layer may be planarized until the second surface is exposed.

In other embodiments, the second substrate may not be provided, and the first substrate and the second substrate may not be bonded.

Accordingly, an embodiment of the present invention further provides a semiconductor structure formed by the above method, with reference to fig. 20, including: the first substrate 100, the first substrate 100 having a first surface 101 and a second surface 102 opposite to each other, the first substrate 100 further having a plurality of first doped regions 103 and second doped regions 104 arranged in an overlapping manner in a direction perpendicular to a surface of the first substrate 100 and separated from each other, and the first surface 101 exposing a surface of the first doped region 103; gate electrodes 122 located in the first substrate 100, the gate electrodes 122 extending from the first side 101 toward the second side 102, each gate electrode 122 penetrating through 1 first doped region 103 and 1 second doped region 104, the gate electrodes 122 including an electrode layer 121 and a dielectric layer 111 located between the electrode layer 121 and the first substrate 100, the first side 101 exposing a top surface of the electrode layer 121; a plurality of word lines 131 on the first side 101, each word line 131 being located on a top surface of at least 1 electrode layer 121; a plurality of bit lines 151 located on the first surface 101, wherein each bit line 151 is also located on at least 1 surface of the first doped region 103, and a plurality of word lines 131 and bit lines 151 are insulated from each other; and the projection of each capacitor on the second surface 102 is at least partially overlapped with the projection of 1 second doping region 104 on the second surface 102.

In the present embodiment, the first substrate 100 includes a storage region I in which the word line 131, the bit line 151, the gate 122, and the capacitor are located.

In this embodiment, the first substrate 100 further includes a first logic area (not shown), and the first substrate further includes a first logic circuit (not shown) therein, and the first logic circuit is located in the first logic area.

In another embodiment, the first logic circuit is electrically connected to a bit line.

In this embodiment, the capacitor includes a first capacitor electrode layer 171, a capacitor dielectric layer 172 on the surface of the first capacitor electrode layer 171, and a second capacitor electrode layer 173 on the surface of the capacitor dielectric layer 172.

In this embodiment, the first substrate 100 has a plurality of capacitor openings 170 (as shown in fig. 17), a projection of each capacitor opening 170 on the second surface 102 at least partially coincides with a projection of 1 second doped region 104 on the second surface 102, and the first capacitor electrode layer 171 is located on an inner wall surface of the capacitor opening 170.

In this embodiment, a plurality of the word lines 131 extend along a first direction X, and a plurality of the bit lines 151 extend along a second direction Y, where the first direction X and the second direction Y are perpendicular to each other.

In this embodiment, a plurality of the gates 122 are arranged in an array along the first direction X and the second direction Y, each word line 131 is located on the top surface of the electrode layer 121 of 1 column of the gates 122 arranged along the first direction X, and each bit line 151 crosses 1 row of the gates 122 in the second direction Y.

In this embodiment, the semiconductor structure further includes: an isolation structure 105 located within the first substrate 100, the isolation structure 105 extending from the first side 101 towards the second side 102, the isolation structure 105 being located between adjacent first doped regions 103, the isolation structure 105 being further located between adjacent second doped regions 104, the first side 101 exposing a top surface of the isolation structure 105.

In this embodiment, the semiconductor structure further includes: a first dielectric structure 140 on the first side 101, wherein the surface of the first dielectric structure 140 is higher than the surface of the word line 131.

The first dielectric structure 140 has a plurality of second openings 141 therein (as shown in fig. 11), each of the second openings 141 exposes at least a part or all of the surface of 1 first doped region 103, and the bit lines 151 are located in the second openings 141 and on the surface of the first dielectric structure 140.

In this embodiment, the semiconductor structure further includes: a second dielectric structure 160 on the surface of the bit line 151 and the first side 101, the second dielectric structure 160 being higher in surface than the bit line 151; a first conductive layer 161 located in the second dielectric structure 160, wherein the first conductive layer 161 is connected to the bit line 151, and the first conductive layer 161 is exposed on the surface of the second dielectric structure 160.

In this embodiment, the semiconductor structure further includes: and a second substrate 200 bonded to the first substrate 100, wherein the second substrate 200 has a functional surface 201 and a non-functional surface 202 opposite to each other, the first surface 101 faces the functional surface 201, and a second logic circuit (not shown) is provided in the second substrate 200 and electrically connected to the bit line 151.

In another embodiment, the second logic circuit is electrically connected to the first logic circuit. Specifically, the semiconductor structure further includes: a second dielectric structure on the bit line surface and the first side, the second dielectric structure surface being higher than the bit line surface; and the first conducting layer is positioned in the second dielectric structure, the first conducting layer is exposed out of the surface of the second dielectric structure, and the first conducting layer is respectively connected with the first logic circuit and the second logic circuit.

In this embodiment, the semiconductor structure further includes: a third media construction 210 on the functional side 201; a second conductive layer 211 located in the third dielectric structure 210, wherein the second conductive layer 211 is electrically connected to the second logic circuit, the second interconnect layer 211 is exposed on the surface of the third dielectric structure 210, and a projection of the first conductive layer 161 on the first surface 101 at least partially coincides with a projection of the second conductive layer 211 on the first surface 101.

In other embodiments, there is no second substrate bonded to the first substrate.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A semiconductor structure, comprising:

the first substrate is provided with a first surface and a second surface which are opposite, the first substrate is internally provided with a plurality of first doping regions and second doping regions which are overlapped and arranged along the direction vertical to the surface of the first substrate and are mutually separated, and the first surface is exposed out of the surface of the first doping region;

the grid electrode is positioned in the first substrate, the grid electrode extends from the first surface to the second surface, each grid electrode penetrates through 1 first doped region and 1 second doped region, the grid electrode comprises an electrode layer and a dielectric layer positioned between the electrode layer and the first substrate, and the first surface is exposed out of the top surface of the electrode layer;

a plurality of word lines on the first side, each word line on a top surface of at least 1 electrode layer;

the bit lines are positioned on the first surface, each bit line is also at least positioned on the surface of 1 first doping region, and the word lines and the bit lines are insulated;

and the projection of each capacitor on the second surface is at least partially coincided with the projections of the 1 second doping region on the second surface.

2. The semiconductor structure of claim 1, wherein the capacitor comprises a first capacitor electrode layer, a capacitor dielectric layer on a surface of the first capacitor electrode layer, and a second capacitor electrode layer on a surface of the capacitor dielectric layer.

3. The semiconductor structure of claim 2, wherein the first substrate has a plurality of capacitor openings therein, projections of the capacitor openings on the second surface at least partially coincide with projections of the 1 second doped region on the second surface, and the first capacitor electrode layer is located on an inner wall surface of the capacitor openings.

4. The semiconductor structure of claim 1, further comprising: and the isolation structure is positioned in the first substrate, extends from the first surface to the second surface, is positioned between the adjacent first doping regions, is also positioned between the adjacent second doping regions, and exposes the top surface of the isolation structure.

5. The semiconductor structure of claim 1, wherein a number of said word lines extend in a first direction and a number of said bit lines extend in a second direction, said first and second directions being perpendicular to each other.

6. The semiconductor structure of claim 5, wherein a plurality of the gates are arranged in an array along the first direction and the second direction, each word line is located on top of 1 column of the electrode layers of the open gates arranged along the first direction, and each bit line crosses 1 row of the gates in the second direction.

7. The semiconductor structure of claim 6, further comprising: a first dielectric structure on the first side, the first dielectric structure surface being higher than the word line surface.

8. The semiconductor structure of claim 7, wherein the first dielectric structure has a plurality of second openings therein, each second opening exposing at least a portion or all of the surface of 1 first doped region, the bit lines being located in the second openings and on the surface of the first dielectric structure.

9. The semiconductor structure of claim 1, wherein the first substrate comprises a storage region, and the word line, bit line, gate, and capacitance are located in the storage region.

10. The semiconductor structure of claim 9, wherein the first substrate further comprises a first logic region, the first substrate further having a first logic circuit therein, and the first logic circuit being located in the first logic region.

11. The semiconductor structure of claim 10, wherein the first logic circuit comprises 1 or more of a row address decoder, a data input buffer, a data output buffer, a sense amplifier, a column address decoder, and a driving circuit.

12. The semiconductor structure of claim 10, further comprising: and the second substrate is bonded with the first substrate, the second substrate is provided with a functional surface and a non-functional surface which are opposite, the first surface faces the functional surface, and the second substrate is internally provided with a second logic circuit which is electrically connected with the first logic circuit.

13. The semiconductor structure of claim 12, further comprising: a second dielectric structure on the bit line surface and the first side, the second dielectric structure surface being higher than the bit line surface; the first conducting layer is positioned in the second dielectric structure, the first conducting layer is exposed out of the surface of the second dielectric structure, and the first conducting layer is respectively connected with the first logic circuit and the second logic circuit.

14. The semiconductor structure of claim 1, further comprising: and the second substrate is bonded with the first substrate, the second substrate is provided with a functional surface and an nonfunctional surface which are opposite, the first surface faces the functional surface, and the second substrate is internally provided with a second logic circuit which is electrically connected with the bit line.

15. The semiconductor structure of claim 13, further comprising: a second dielectric structure on the bit line surface and the first side, the second dielectric structure surface being higher than the bit line surface; and the first conducting layer is positioned in the second dielectric structure, is connected with the bit line, and is exposed on the surface of the second dielectric structure.

16. The semiconductor structure of claim 14, further comprising: a third media construction on the functional side; and the second conducting layer is positioned in the third dielectric structure and is electrically connected with the second logic circuit, the second interconnection layer is exposed on the surface of the third dielectric structure, and the projection of the first conducting layer on the first surface is at least partially overlapped with the projection of the second conducting layer on the first surface.

17. The semiconductor structure according to claim 12 or 14, wherein the second logic circuit comprises 1 or more of a row address decoder, a data input buffer, a data output buffer, a sense amplifier, a column address decoder, and a driving circuit.

18. A method of forming a semiconductor structure, comprising:

providing a first substrate, wherein the first substrate is provided with a first surface and a second surface which are opposite, the first substrate is internally provided with a plurality of first doping regions and second doping regions which are overlapped and arranged along the direction vertical to the surface of the first substrate and are mutually separated, and the surface of the first doping region is exposed out of the first surface;

forming a plurality of grids extending from the first surface to the second surface in the first substrate, wherein each grid penetrates through 1 first doped region and 1 second doped region, each grid comprises an electrode layer and a dielectric layer positioned between the electrode layer and the first substrate, and the first surface is exposed out of the top surface of the electrode layer;

forming a plurality of word lines on the first surface, wherein each word line is positioned on the top surface of at least 1 electrode layer;

forming a plurality of bit lines on the first surface, wherein each bit line is at least positioned on the surface of 1 first doping region, and the word lines and the bit lines are insulated;

and forming a plurality of capacitors on the second surface, wherein the projection of each capacitor on the second surface is at least partially overlapped with the projection of the 1 second doping region on the second surface.

19. The method of claim 18, wherein the capacitor comprises a first capacitor electrode layer, a capacitor dielectric layer on a surface of the first capacitor electrode layer, and a second capacitor electrode layer on a surface of the capacitor dielectric layer.

20. The method of forming a semiconductor structure of claim 19, wherein forming the capacitor comprises: after forming a plurality of word lines and bit lines, etching the second surface, and forming a plurality of capacitor openings in the first substrate, wherein projections of the capacitor openings on the second surface are at least partially overlapped with projections of the 1 second doping area on the second surface; forming the first capacitance electrode layer on an inner wall surface of each capacitance opening; forming a capacitance dielectric layer on the surface of the first capacitance electrode layer; and forming a second capacitance electrode layer on the surface of the capacitance dielectric layer.

21. The method of forming a semiconductor structure of claim 20, further comprising: the second face is thinned after forming the word lines and bit lines and before forming the capacitance openings.

22. The method of forming a semiconductor structure of claim 18, further comprising an isolation structure in the first substrate, the isolation structure extending from the first side toward the second side, the isolation structure being located between adjacent first doped regions, the isolation structure being further located between adjacent second doped regions, the first side exposing a top surface of the isolation structure.

23. The method of forming a semiconductor structure of claim 18, wherein forming the gate comprises: etching the first surface, and forming a plurality of first openings in the first substrate, wherein each first opening penetrates through 1 first doping region and 1 second doping region; forming a dielectric material layer on the first opening and the first surface; forming an electrode material layer on the surface of the dielectric material layer, wherein the surface of the electrode material layer is higher than the first surface; forming a plurality of first mask structures on the surface of the electrode material layer, wherein each first mask structure covers at least 1 first opening and exposes at least part of the surface of the electrode material layer on the first doping region; and etching the electrode material layer and the dielectric material layer by taking the first mask structures as masks until the first surface is exposed.

24. The method of forming a semiconductor structure of claim 23, wherein forming a plurality of the word lines comprises: forming a word line material layer on the surface of the electrode material layer before forming a plurality of first mask structures; before etching the electrode material layer, etching the word line material layer by taking the first mask structures as masks until the surface of the electrode material layer is exposed.

25. The method of forming a semiconductor structure of claim 24, further comprising: after the word line is formed, a first dielectric structure is formed on the first surface before the bit line is formed, and the surface of the first dielectric structure is higher than the surface of the word line.

26. The method of forming a semiconductor structure of claim 25, wherein the method of forming the bit line comprises: forming a plurality of second openings in the first dielectric structure, wherein each second opening at least exposes partial or all surfaces of 1 first doping region; forming a bit line material layer in the second opening and on the surface of the first dielectric structure; forming a plurality of second mask structures on the surface of the bit line material layer, wherein each second mask structure covers at least 1 second opening; and etching the bit line material layer by taking the second mask structure as a mask until the surface of the first dielectric structure is exposed.

27. The method of forming a semiconductor structure of claim 18, further comprising: after forming the gates and word lines, and before forming bit lines, contact layers are formed on the surfaces of the first doped regions.

28. The method of forming a semiconductor structure of claim 27, wherein the electrode layer has a top surface higher than the first surface; the method for forming the semiconductor structure further comprises the following steps: and before the contact layer is formed, forming a side wall on the side wall surface of the electrode layer on the first surface.

29. The method of forming a semiconductor structure of claim 18, wherein an extending direction of the bit line and an extending direction of the word line are perpendicular to each other.

30. The method of forming a semiconductor structure of claim 18, wherein the first substrate includes a storage region, and wherein the word line, bit line, gate, and capacitor are located in the storage region.

31. The method of forming a semiconductor structure according to claim 30, wherein the first substrate further comprises a first logic region, the first substrate further comprises a first logic circuit therein, and the first logic circuit is located in the first logic region.

32. The method of forming a semiconductor structure of claim 31, further comprising: providing a second substrate having a second logic circuit therein, the second substrate further having opposing functional and non-functional sides; bonding the first substrate and a second substrate after forming the gate, the word line, and the bit line and before forming the capacitor, the first surface facing the functional surface, and the second logic circuit being electrically connected to the first logic circuit.

33. The method of forming a semiconductor structure of claim 32, further comprising: further comprising: forming a second dielectric structure on the bit line surface and the first face after forming the gate, the word line, and the bit line and before bonding the first substrate and the second substrate, the second dielectric structure surface being higher than the bit line surface; and forming a first conductive layer in the second dielectric structure, wherein the first conductive layer is connected with the first logic circuit, and the first conductive layer is exposed out of the surface of the second dielectric structure.

34. The method of forming a semiconductor structure of claim 18, further comprising: providing a second substrate having a second logic circuit therein, the second substrate further having opposing functional and non-functional sides; bonding the first substrate and a second substrate after forming the gate, the word line, and the bit line and before forming the capacitor, the first surface facing the functional surface, and the second logic circuit being electrically connected to the bit line.

35. The method of forming a semiconductor structure of claim 34, further comprising: forming a second dielectric structure on the bit line surface and the first face after forming the gate, the word line, and the bit line and before bonding the first substrate and the second substrate, the second dielectric structure surface being higher than the bit line surface; and forming a first conductive layer in the second dielectric structure, wherein the first conductive layer is connected with the bit line, and the first conductive layer is exposed out of the surface of the second dielectric structure.

36. The method of forming a semiconductor structure of claim 35, further comprising: forming a third dielectric structure on the functional side prior to bonding the first substrate to the second substrate; and forming a second conducting layer in the third dielectric structure, wherein the second conducting layer is electrically connected with the second logic circuit, the second conducting layer is exposed from the surface of the third dielectric structure, and after the first substrate is bonded with the second substrate, the projection of the first conducting layer on the first surface is at least partially overlapped with the projection of the second conducting layer on the first surface.