TWI826307B - Memory structure and manufacturing methid thereof - Google Patents

Abstract

A memory structure including a substrate, a first conductive line, a first contact, a gate, a second conductive line, a first dielectric layer, a second dielectric layer, a second contact, and a capacitor is provided. The substrate includes a substrate layer, an insulating layer, and a semiconductor layer. The insulating layer is located on the substrate layer. The semiconductor layer is located on the insulating layer. The first conductive line is located in the insulating layer. The first contact is located in the semiconductor layer and on the first conductive line. The gate is located in the semiconductor layer and on the first contact. The second conductive line is located in the semiconductor layer and on the gate. The first dielectric layer is located between the gate and the first contact, between the gate and the semiconductor layer, and between the second conductive line and the semiconductor layer. The second dielectric layer is located on the second conductive line. The second contact is located on the semiconductor layer and the second dielectric layer. The capacitor is located on the second contact.

Description

Memory structure and manufacturing method

The present invention relates to a memory structure, and in particular to a memory structure that can effectively reduce the memory cell area.

Dynamic random access memory includes transistors and capacitors coupled to each other, where the capacitors can serve as storage nodes. However, how to effectively reduce the memory cell area of dynamic random access memory is a goal that the industry continues to strive for.

The present invention provides a memory structure and a manufacturing method thereof, which can effectively reduce the memory cell area.

The invention proposes a memory structure, which includes a substrate, a first conductor, a first contact window, a gate, a second conductor, a first dielectric layer, a second dielectric layer, a second contact window and a capacitor. The base includes a base layer, an insulating layer and a semiconductor layer. The insulation layer is on the base layer. The semiconductor layer is on the insulating layer. The first conductor is located in the insulation layer. The first contact window is located in the semiconductor layer and on the first conductive line. The gate is located in the semiconductor layer and on the first contact window. The second conductor is located in the semiconductor layer and on the gate. The first dielectric layer is between the gate and the first contact window, between the gate and the semiconductor layer, and between the second conductor and the semiconductor layer. The second dielectric layer is located on the second conductive line. The second contact window is located on the semiconductor layer and the second dielectric layer. The capacitor is located on the second contact window.

According to an embodiment of the present invention, in the above memory structure, the first contact window can directly contact the semiconductor layer.

According to an embodiment of the present invention, in the above memory structure, the gate and the second conductor may be integrally formed.

According to an embodiment of the present invention, in the above memory structure, the top surface of the second conductive line may be lower than the top surface of the semiconductor layer.

According to an embodiment of the present invention, in the above memory structure, the second contact window can directly contact the semiconductor layer.

According to an embodiment of the present invention, the above memory structure may further include an isolation structure. The isolation structure is located in the semiconductor layer. Isolation structures define active regions in the semiconductor layer.

According to an embodiment of the present invention, the above memory structure may further include a filling layer and a capping layer. The filling layer is located in the semiconductor layer. The gate may be surrounded by semiconductor layers and filling layers. The capping layer is located between the first conductive line and the filling layer.

The present invention proposes a method for manufacturing a memory structure, which includes the following steps. Provide a base. The base includes a base layer, an insulating layer and a semiconductor layer. The insulation layer is on the base layer. The semiconductor layer is on the insulating layer. A first conductive line is formed in the insulating layer. A first contact window is formed in the semiconductor layer and on the first conductive line. A gate is formed in the semiconductor layer and on the first contact window. A second conductive line is formed in the semiconductor layer and on the gate electrode. A first dielectric layer is formed between the gate electrode and the first contact window, between the gate electrode and the semiconductor layer, and between the second conductive line and the semiconductor layer. A second dielectric layer is formed over the second conductive line. A second contact window is formed on the semiconductor layer and the second dielectric layer. A capacitor is formed on the second contact window.

According to an embodiment of the present invention, in the above method of manufacturing a memory structure, the method of forming the first conductor, the first contact window, the gate, the second conductor and the first dielectric layer may include the following steps. A first trench is formed in the semiconductor layer and the insulating layer. A first conductive line is formed in the first trench. A capping layer is formed in the first trench and on the first wire. A filling layer is formed in the first trench and on the capping layer. A second trench is formed in the semiconductor layer and the filling layer. Openings are formed in the filling layer and the capping layer. The opening may expose part of the first conductor. A first contact window is formed on the first conductor exposed by the opening. A first dielectric layer is formed in the second trench and opening and on the first conductive line. A gate electrode and a second conductive line are formed on the first dielectric layer. The gate can be located in the opening and the second conductor can be located in the second trench.

According to an embodiment of the present invention, the method for manufacturing the memory structure may further include the following steps. An isolation structure is formed in the semiconductor layer. Isolation structures define active regions in the semiconductor layer.

Based on the above, in the memory structure and the manufacturing method thereof proposed by the present invention, the substrate includes a base layer, an insulating layer and a semiconductor layer. The first conductor is located in the insulation layer. The first contact window is located in the semiconductor layer and on the first conductive line. The gate is located in the semiconductor layer and on the first contact window. The second conductor is located in the semiconductor layer and on the gate. The first dielectric layer is between the gate and the first contact window, between the gate and the semiconductor layer, and between the second conductor and the semiconductor layer. The second dielectric layer is located on the second conductive line. The second contact window is located on the semiconductor layer and the second dielectric layer. The capacitor is located on the second contact window. Therefore, the memory structure and its manufacturing method proposed by the present invention can effectively reduce the memory cell area and increase the memory cell density.

In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, embodiments are given below and described in detail with reference to the accompanying drawings.

Examples are listed below and described in detail with reference to the drawings. However, the provided examples are not intended to limit the scope of the present invention. To facilitate understanding, the same components will be identified with the same symbols in the following description. In addition, the drawings are for illustrative purposes only and are not drawn to original size. Additionally, features in the perspective view are not drawn to the same scale as features in the upper view. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

1A to 1L are perspective views of the manufacturing process of a memory structure according to some embodiments of the present invention. Figure 2 is a perspective view of a memory structure according to some embodiments of the present invention. FIG. 3 is a top view of the memory structure in FIG. 1L. FIG. 1L is a perspective view of part of the memory structure in FIG. 3 . In FIGS. 2 and 3 , some components in FIG. 1L are omitted to clearly illustrate the positional relationship between the components in FIGS. 2 and 3 .

Referring to Figure 1A, a substrate 100 is provided. The substrate 100 includes a base layer 102, an insulating layer 104 and a semiconductor layer 106. In some embodiments, the substrate 100 may be a semiconductor-on-insulator (SOI) substrate. In some embodiments, the material of the base layer 102 is, for example, a semiconductor material, such as silicon. The insulating layer 104 is located on the base layer 102 . In some embodiments, the material of the insulating layer 104 is, for example, silicon oxide. The semiconductor layer 106 is located on the insulating layer 104 . In some embodiments, the material of the semiconductor layer 106 is, for example, silicon.

Referring to FIG. 1B , a trench T1 may be formed in the semiconductor layer 106 and the insulating layer 104 . In some embodiments, the trench T1 can be formed by patterning the semiconductor layer 106 and the insulating layer 104 through a photolithography process and an etching process (eg, a dry etching process).

Referring to FIG. 1C , wires 108 may be formed in trench T1. Thereby, the conductive wire 108 can be formed in the insulating layer 104 . In some embodiments, the material of the wire 108 is, for example, tungsten, titanium, titanium nitride, or combinations thereof. In some embodiments, a method of forming wires 108 may include the following steps. First, a conductive material layer (not shown) filling the trench T1 may be formed on the semiconductor layer 106 . Then, an etching back process (such as a dry etching process) can be performed on the wire material layer to form the wire 108 .

Next, a capping layer 110 may be formed in the trench T1 and on the conductive line 108 . In some embodiments, capping layer 110 may serve as an etch stop layer. In some embodiments, the material of the capping layer 110 is, for example, silicon nitride. In some embodiments, a method of forming the capping layer 110 may include the following steps. First, a cap material layer (not shown) filling the trench T1 may be formed on the semiconductor layer 106 . Then, an etching back process (eg, a dry etching process) can be performed on the capping material layer to form the capping layer 110 .

Then, a filling layer 112 may be formed in the trench T1 and on the capping layer 110 . In some embodiments, the material of the filling layer 112 is, for example, silicon oxide. In some embodiments, a method of forming the filling layer 112 may include the following steps. First, a filling material layer (not shown) filling the trench T1 may be formed on the semiconductor layer 106 . Then, an etch-back process (eg, a dry etching process) can be performed on the filling material layer to form the filling layer 112 .

Referring to FIG. 1D , an isolation structure 114 may be formed in the semiconductor layer 106 . Isolation structure 114 may define active area AA in semiconductor layer 106 . In some embodiments, the material of the isolation structure 114 is, for example, silicon oxide. In some embodiments, a method of forming the isolation structure 114 may include the following steps. First, the semiconductor layer 106 and the filling layer 112 may be patterned through a photolithography process and an etching process to form trenches (not shown) in the semiconductor layer 106 and the filling layer 112 . Next, an isolation material layer (not shown) filling the trench may be formed on the semiconductor layer 106 and the filling layer 112 . Then, a portion of the isolation material layer outside the trench may be removed to form isolation structure 114 . In some embodiments, the partial isolation material layer located outside the trench is removed by, for example, chemical mechanical polishing.

Referring to FIG. 1E , a trench T2 may be formed in the semiconductor layer 106 and the filling layer 112 . In some embodiments, the trench T2 may be formed by patterning the semiconductor layer 106, the filling layer 112, and the isolation structure 114 through a photolithography process and an etching process (eg, a dry etching process).

Referring to FIG. 1F , a patterned photoresist layer 116 may be formed. The patterned photoresist layer 116 may have an opening OP1. The opening OP1 may expose a portion of the filling layer 112 located at an intersection region of the top-view pattern of the trench T2 and the top-view pattern of the conductive line 108 . In some embodiments, the patterned photoresist layer 116 may be formed by a photolithography process.

Referring to FIG. 1G , the patterned photoresist layer 116 can be used as a mask to remove part of the filling layer 112 and part of the capping layer 110 to form the opening OP2. Thereby, the opening OP2 can be formed in the filling layer 112 and the capping layer 110 . The opening OP2 may expose part of the wire 108 . In some embodiments, a method for removing part of the filling layer 112 and part of the capping layer 110 is, for example, dry etching. In some embodiments, in the etching process for removing part of the filling layer 112 and part of the capping layer 110 , the removal rate of the filling layer 112 and the removal rate of the capping layer 110 is greater than the removal rate of the semiconductor layer 106 . Therefore, in the etching process for removing part of the filling layer 112 and part of the capping layer 110 , even if the opening OP2 exposes part of the semiconductor layer 106 , part of the filling layer 112 and part of the capping layer 110 can be removed in a self-aligned manner. Cover 110.

Referring to FIG. 1H , the patterned photoresist layer 116 can be removed. Furthermore, as shown in FIG. 1H , the opening OP2 may be connected to the trench T2. In some embodiments, the patterned photoresist layer 116 is removed by, for example, dry stripping or wet stripping.

Referring to FIG. 1I, a contact window 118 may be formed on the wire 108 exposed by the opening OP2. Thereby, contact windows 118 can be formed in the semiconductor layer 106 and on the wires 108 . In some embodiments, contact window 118 may directly contact semiconductor layer 106 . In some embodiments, the contact window 118 is made of, for example, doped polysilicon. In some embodiments, a method of forming the contact window 118 may include the following steps. First, a contact window material layer (not shown) filling the opening OP2 and the trench T2 may be formed on the semiconductor layer 106, the wire 108, the filling layer 112 and the isolation structure 114. Then, an etching back process (eg, a dry etching process) can be performed on the contact window material layer to form the contact window 118 .

Referring to FIG. 1J , a dielectric layer 120 may be formed in the trench T2 and the opening OP2 and on the contact window 118 . Next, the gate 122 and the conductor 124 can be formed on the dielectric layer 120 . Gate 122 may be located in opening OP2, and conductor 124 may be located in trench T2. Through the above method, the gate 122 can be formed in the semiconductor layer 106 and on the contact window 118, the conductor 124 can be formed in the semiconductor layer 106 and on the gate 122, and between the gate 122 and the contact window 118, the gate electrode 122 can be formed. A dielectric layer 120 is formed between the pole 122 and the semiconductor layer 106 and between the conductive wire 124 and the semiconductor layer 106 . Gate 122 and contact 118 may be electrically isolated from each other by dielectric layer 120 . The gate 122 and the semiconductor layer 106 may be electrically insulated from each other by the dielectric layer 120 . The conductive lines 124 and the semiconductor layer 108 may be electrically insulated from each other by the dielectric layer 120 . In some embodiments, the material of the dielectric layer 120 is, for example, silicon oxide. In some embodiments, the gate 122 and the conductor 124 may be integrally formed. In some embodiments, the top surface S1 of the conductive lines 124 may be lower than the top surface S2 of the semiconductor layer 106 . In some embodiments, the material of the gate 122 and the conductor 124 is, for example, tungsten, copper, aluminum, titanium, titanium nitride, tantalum, tantalum nitride or a combination thereof.

In some embodiments, the method of forming the dielectric layer 120, the gate 122 and the conductive wire 124 may include the following steps. First, a dielectric material layer (not shown) may be formed on the semiconductor layer 106 and the contact window 118 . In some embodiments, the dielectric material layer is formed by a thermal oxidation method, such as an in situ steam generation (ISSG) method. Next, a conductive material layer (not shown) filling the opening OP2 and the trench T2 may be formed on the dielectric material layer. Then, a portion of the conductive material layer located outside the trench T2 is removed to form the wires 124 and the gate 122 , and a portion of the dielectric material layer located outside the trench T2 is removed to form the dielectric layer 120 . In some embodiments, part of the conductive material layer located in the trench T2 may be removed, so that the top surface S1 of the conductive line 124 is lower than the top surface S2 of the semiconductor layer 106 . In some embodiments, a portion of the dielectric material layer located in the trench T2 may be removed such that the top surface S3 of the dielectric layer 120 is lower than the top surface S2 of the semiconductor layer 106 . In some embodiments, a method for removing part of the conductive material layer and part of the dielectric material layer is, for example, chemical mechanical polishing, etching back, or a combination thereof.

Next, a dielectric layer 126 is formed on the conductive lines 124 . In some embodiments, top surface S4 of dielectric layer 126 may be flush with top surface S2 of semiconductor layer 106 . In some embodiments, the material of the dielectric layer 126 is, for example, silicon oxide. In some embodiments, a method of forming dielectric layer 126 may include the following steps. First, a dielectric material layer (not shown) filling the trench T2 may be formed on the semiconductor layer 106 , the filling layer 112 , the isolation structure 114 , the conductive lines 124 and the dielectric layer 120 . The dielectric material layer located outside the trench T2 can then be removed to form the dielectric layer 126 . In some embodiments, the method for removing the dielectric material layer located outside the trench T2 is, for example, chemical mechanical polishing or etching back.

Referring to FIG. 1K , contact windows 128 are formed on the semiconductor layer 106 and the dielectric layer 126 . In some embodiments, contacts 128 and wires 124 may be electrically isolated from each other by dielectric layer 126 . In some embodiments, contact window 128 may directly contact semiconductor layer 106 . In some embodiments, the material of the contact window 128 is, for example, doped polycrystalline silicon, tungsten, titanium, titanium nitride, or combinations thereof. In some embodiments, contact 128 may be located in a dielectric layer (not shown). However, in order to clearly illustrate the positional relationship between the components in the figure, the above-mentioned dielectric layer is omitted from the figure. In addition, the contact window 128 can be formed by conventional methods, and the description thereof is omitted here.

Referring to FIG. 1L , a capacitor 130 is formed on the contact window 128 . Capacitor 130 may be electrically connected to contact window 128 . In some embodiments, the capacitor 130 may be a cylinder capacitor, but the invention is not limited thereto. Capacitor 130 can be any capacitor that can be used as a storage node (SN). In some embodiments, capacitor 130 may be located in a dielectric layer (not shown). However, in order to clearly illustrate the positional relationship between the components in the figure, the above-mentioned dielectric layer is omitted from the figure. In addition, the capacitor 130 can be formed by conventional methods, and the description thereof is omitted here.

Hereinafter, the memory structure 10 of the above embodiment will be described with reference to FIG. 1L, FIG. 2 and FIG. 3. In addition, although the method for forming the memory structure 10 is described by taking the above method as an example, the present invention is not limited thereto.

Referring to FIGS. 1L , 2 and 3 , the memory structure 10 includes a substrate 100 , wires 108 , contacts 118 , gates 122 , wires 124 , dielectric layers 120 , dielectric layers 126 , contacts 128 and capacitors 130 . In some embodiments, the memory structure 10 is, for example, a dynamic random access memory (DRAM) structure.

The substrate 100 includes a base layer 102, an insulating layer 104 and a semiconductor layer 106. The insulating layer 104 is located on the base layer 102 . The semiconductor layer 106 is located on the insulating layer 104 . In some embodiments, semiconductor layer 106 may function as a channel layer. Conductors 108 are located in insulation layer 104 . In some embodiments, conductors 108 may function as bit lines. Wire 108 may extend in direction Dl. Contact windows 118 are located in the semiconductor layer 106 and on the conductive lines 108 . The contact window 118 can be electrically connected to the wire 108 . In some embodiments, contact 118 may be used as a bit contact. The gate 122 is located in the semiconductor layer 106 and on the contact window 118 . Wires 124 are located in the semiconductor layer 106 and on the gate 122 . In some embodiments, conductors 124 may function as word lines. Wire 124 may extend in direction D2. Direction D1 may intersect direction D2. In some embodiments, direction D1 may be perpendicular to direction D2. The dielectric layer 120 is located between the gate 122 and the contact window 118 , between the gate 122 and the semiconductor layer 106 , and between the conductor 124 and the semiconductor layer 106 . Dielectric layer 126 is located over conductive lines 124 . Contact windows 128 are located on the semiconductor layer 106 and the dielectric layer 126 . Capacitor 130 is located on contact 128. In some embodiments, capacitor 130 may be used as a storage node.

As shown in FIG. 1D and FIG. 1L , the memory structure 10 may further include an isolation structure 114 . Isolation structure 114 is located in semiconductor layer 106 . Isolation structure 114 may define active area AA in semiconductor layer 106 (FIG. 1D).

As shown in FIGS. 1H to 1J , the memory structure 10 may further include a filling layer 112 and a capping layer 110 . A filling layer 112 is located in the semiconductor layer 106 . The gate 122 may be surrounded by the semiconductor layer 106 and the filling layer 112 . The capping layer 110 is located between the conductive lines 108 and the filling layer 112 .

As shown in FIG. 3 , the memory structure 10 may further include a contact window 132 and a contact window 134 . The contact window 132 is electrically connected to the wire 108 . In some embodiments, contact 132 may be used as a bit line contact. The contact window 134 is electrically connected to the wire 124 . In some embodiments, contacts 134 may be used as word line contacts.

The memory structure 10 may include memory cells MC. The memory cell MC may be located at the intersection of the top-view pattern of the conductor 108 and the top-view pattern of the conductor 124 . In some embodiments, the memory cell MC may include a semiconductor layer 106, a conductor 108, a contact 118, a gate 122, a conductor 124, a dielectric layer 120, a dielectric layer 126, a contact 128 and a capacitor 130.

Based on the above embodiments, it can be known that in the memory structure 10 and the manufacturing method thereof, the substrate 100 includes a base layer 102, an insulating layer 104 and a semiconductor layer 106. Conductors 108 are located in insulation layer 104 . Contact windows 118 are located in the semiconductor layer 106 and on the conductive lines 108 . The gate 122 is located in the semiconductor layer 106 and on the contact window 118 . Wires 124 are located in the semiconductor layer 106 and on the gate 122 . The dielectric layer 120 is located between the gate 122 and the contact window 118 , between the gate 122 and the semiconductor layer 106 , and between the conductor 124 and the semiconductor layer 106 . Dielectric layer 126 is located over conductive lines 124 . Contact windows 128 are located on the semiconductor layer 106 and the dielectric layer 126 . Capacitor 130 is located on contact 128. Therefore, the memory structure 10 and its manufacturing method can effectively reduce the memory cell area and increase the memory cell density.

In summary, in the memory structure and the manufacturing method of the above embodiments, the memory cell area can be effectively reduced and the memory cell density can be increased through the arrangement of each component in the memory structure.

Although the present invention has been disclosed above through embodiments, they are not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some modifications and modifications without departing from the spirit and scope of the present invention. Therefore, The protection scope of the present invention shall be determined by the appended patent application scope.

100:Base 102: Basal layer 104:Insulation layer 106: Semiconductor layer 108:Wire 110:Top layer 112:Filling layer 114:Isolation structure 116:Patterned photoresist layer 118,128,132,134:Contact window 120,126: Dielectric layer 122: Gate 124:Wire 130:Capacitor AA: active area D1, D2: direction MC: memory cell OP1, OP2: Open S1, S2, S3, S4: top surface T1, T2: ditch

1A to 1L are perspective views of the manufacturing process of a memory structure according to some embodiments of the present invention. Figure 2 is a perspective view of a memory structure according to some embodiments of the present invention. FIG. 3 is a top view of the memory structure in FIG. 1L.

100:Base

102: Basal layer

104:Insulation layer

106: Semiconductor layer

108:Wire

114:Isolation structure

118,128:Contact window

120,126: Dielectric layer

122: Gate

124:Wire

130:Capacitor

D1, D2: direction

MC: memory cell

Claims (10)

A memory structure including: Base, including: basal layer; an insulating layer located on the base layer; and A semiconductor layer located on the insulating layer; The first conductor is located in the insulating layer; A first contact window is located in the semiconductor layer and on the first conductor; A gate located in the semiconductor layer and on the first contact window; a second conductor located in the semiconductor layer and on the gate; a first dielectric layer located between the gate and the first contact window, between the gate and the semiconductor layer, and between the second conductor and the semiconductor layer; a second dielectric layer located on the second conductor; A second contact window is located on the semiconductor layer and the second dielectric layer; and The capacitor is located on the second contact window. The memory structure of claim 1, wherein the first contact window directly contacts the semiconductor layer. The memory structure of claim 1, wherein the gate and the second conductor are integrally formed. The memory structure of claim 1, wherein a top surface of the second conductive line is lower than a top surface of the semiconductor layer. The memory structure of claim 1, wherein the second contact window directly contacts the semiconductor layer. The memory structure as described in request item 1 further includes: An isolation structure is located in the semiconductor layer and defines an active region in the semiconductor layer. The memory structure as described in request item 1 further includes: a filling layer located in the semiconductor layer, wherein the gate is surrounded by the semiconductor layer and the filling layer; and A top cover layer is located between the first conductive line and the filling layer. A method of manufacturing a memory structure, including: A substrate is provided, wherein the substrate includes: basal layer; an insulating layer located on the base layer; and A semiconductor layer located on the insulating layer; forming a first conductive line in the insulating layer, forming a first contact window in the semiconductor layer and on the first conductor; forming a gate in the semiconductor layer and on the first contact window; forming a second conductive line in the semiconductor layer and on the gate electrode; A first dielectric layer is formed between the gate and the first contact window, between the gate and the semiconductor layer, and between the second conductor and the semiconductor layer; forming a second dielectric layer on the second conductor; forming a second contact window on the semiconductor layer and the second dielectric layer; and A capacitor is formed on the second contact window. The method of manufacturing a memory structure according to claim 8, wherein the method of forming the first conductor, the first contact window, the gate, the second conductor and the first dielectric layer includes: : forming a first trench in the semiconductor layer and the insulating layer; forming the first conductive line in the first trench; forming a capping layer in the first trench and on the first conductor; forming a filling layer in the first trench and on the top cover layer; forming a second trench in the semiconductor layer and the filling layer; forming an opening in the filling layer and the capping layer, wherein the opening exposes a portion of the first conductor; forming the first contact window on the first conductor exposed by the opening; forming the first dielectric layer in the second trench and the opening and on the first contact window; and The gate electrode and the second conductive line are formed on the first dielectric layer, wherein the gate electrode is located in the opening, and the second conductive line is located in the second trench. The manufacturing method of the memory structure as described in claim 8 further includes: An isolation structure is formed in the semiconductor layer, wherein the isolation structure defines an active region in the semiconductor layer.

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