TW200428567A - Method for isolating the active area of a memory cell with partial vertical channel - Google Patents

Abstract

A method for isolating the active area of a memory cell with partial vertical channel is provided. First, provide a semiconductor substrate that contains two deep trenches. In each deep trench, a deep trench capacitor is formed and the capacitor is below the substrate surface. Second, form a protruding column type active area between the deep trenches, and conduct ion implantation process on the bottom corner of the exposed active area to form ion doped areas that are as source/drain areas. Third, sequentially form a gate dielectric layer and a conduction layer on the active area surface. The conduction layer is used to be a vertical gate. Form a dielectric layer on the substrate to isolate the other active area. The height of the said dielectric layer is equal to the top of the vertical gate.

Description

200428567 V. Description of the invention (l) [Technical field to which the invention belongs] The present invention relates to a method for manufacturing an isolation element, and more particularly, to an isolation device having a vertical transistor and a deep trench capacitor. Active zone method. [Previous Technology] When fabricating high-density implanted semiconductor components on integrated circuit wafers, it is necessary to consider how to reduce the size and power consumption of each memory cell in order to speed up its operation speed. In the traditional planar transistor design, in order to obtain a memory cell of the smallest size, the gate length of the transistor must be as short as possible to reduce the lateral area of 7C. However, this will make the leisure electrode unable to tolerate a large leakage current and must correspondingly reduce the voltage on the bit line, thereby reducing the charge stored in the capacitor. Therefore, while reducing the lateral length of the gate, it is also necessary to consider how to make Capacitors with large capacitance, such as: increasing the area of the capacitor, reducing the effective dielectric thickness between the capacitor plates, and so on. Since the conditions for reducing the memory cell area and increasing the capacitor area cannot be met in actual production, and the thickness of the effective medium cannot be further reduced, a vertical transistor (vert 丨 ⑶ 目前 transistor) structure is currently developed, which can reduce the gate length. Maintaining an appropriate value for obtaining low leakage current will not only reduce the bit line voltage, nor increase the lateral area of the memory cell. In addition, a deep trench capacitor (Deep Trench Capacitor) has also been developed, which is placed directly below the vertical transistor without occupying an additional area of the memory cell.

200428567

Self-aligned diffused source vertical transistor. Please refer to the la-le diagram. The la_le diagram is a schematic cross-sectional view of the transistor in the vertical channel.有, there is a knife (U-known manufacturing method is to form a plurality of deep grooves 04 and a corresponding protruding columnar region 102 on a P-type silicon substrate 101): Each chip :: columnar region m. As shown in Figure la, the surface of the cylindrical region 10 is two females and one female.

Open Π2Λ domain. Firstly, 2 heteroemulsions 105 (such as arsenic glass ASG) are formed on the side wall of the region below the deep trench 104 as a source diffusion material, and a short-time annealing process is performed at a low temperature to diffuse the fragments into the columnar region ^, the side wall An n-type heavily doped (η +) diffusion region 106 is formed for use as an n + source region 106 and a storage electrode of a deep trench capacitor to be manufactured later. Subsequently, as shown in FIG. 1 b, the heavily doped oxide 5 is removed.

Then, as shown in FIG. 1c, a 0N0 film 107 is grown on the inner sidewall of the deep trench 104 as a medium of the deep trench capacitor. Then, a polysilicon layer 108 is deposited in the deep trench ^ to serve as a capacitor plate 108 of the trench capacitor, and the 0N0 thin film 107 and the n + polycrystalline silicon layer 108 are etched to a predetermined depth. Following ^, as shown in FIG. Id, a barrier oxide layer 109 is covered with a polycrystalline silicon layer in the deep trench 104, so as to isolate the gates made later. Subsequently, a gate oxide 11 () is grown on the sidewall in the deep trench 104, and a #polycrystalline silicon layer m is filled in the deep trench 104 as a control gate lu. Then, as shown in FIG. 1e, the gate electrodes are etched to isolate the word lines, and the thin pad oxide layer 103a and the oxynitride layer 103b are removed, and then die / (^ A 102 is implanted with an n + polar region 112. Finally, an AND word line is formed.

200428567 V. Description of the invention (3) Where the vertical metal lines 1 1 3 are formed, the memory cell array is completed. It can be known from the above that in each memory cell, the control gate 1 1 1, the source region 106 and the n + drain region 112 constitute a vertical transistor, and the #diffusion regions 1 06 and 0 N located below the vertical transistor The thin film 107 and the n + polycrystalline silicon layer 108 constitute a deep trench capacitor. In an open bit line (bit llne) architecture, all memory cells share a deep trench capacitor # evening sun silicon valley board 108, the charge is stored in the y diffusion region in each columnar region 102 106. Although the top of the columnar region 102 can be used as a channel between the n + source regions ι〇6 and η; and the polar region 112, it is to avoid two adjacent ones on the inner side wall of the columnar region 02. The source region 106 may be too close and overlapped, and the lateral width of the columnar region 102 may be limited to a certain extent and cannot be shortened. In addition, the columnar region 1 may be shortened. 〇2 The width of the effective isolation area will reduce the density of memory cells that can be formed per unit area. [Summary of the Invention] The objective of the present invention is to provide a method for isolating active areas with partial vertical traffic § == early 70, which is used for dynamic random access memory early cells and effectively isolate each active area. According to the above object, the present invention and M ^ + ^ provide a method for isolating an active region having a partially vertical communication memory h, including the following steps: providing a semiconductor substrate, a + conductor substrate including two deep trenches, and a deep trench A deep trench capacitor is formed inside, and the deep trench capacitance is lower than the surface of the semiconductor substrate, so that the deep trenches become-protruding pillar-shaped active regions;

200428567 V. Description of the invention (4) The ion implantation step is performed at the bottom corner of the region to form > as a source drain region; on the surface of the active region, a * heteroregion, * layer and a conductive layer, the conductive layer is used for As a -vertical-formed-electrode dielectric substrate, a dielectric layer is formed, and the dielectric layer is isolated from a vertical semiconductor to isolate another active region. "You have the same height at the top, and according to the above purpose, the method of the present invention again mentions the active area of the channel memory unit = includes? Divided into a vertical conductor substrate, the bottom part of the semiconductor is right. Provide a half-deep groove: ΐ: the shape of the groove; on each-deep trench capacitor surface, the semiconductor ^ surface is filled with-mask layer; ☆ deep trench The bottom of the semiconductor ▲ :: Cheng: j: The first patterned mask layer in layer 2 covers a part of the surface of the mask layer. ^ -The patterned mask layer and the mask layer are masks. The height of the isolation layer is to form-highlight the columnar active-to remove the first patterned mask layer and the mask layer; the ion implantation step is performed on the active area on the side of the isolation layer to form an ion doped region, and As a source drain region; a gate dielectric layer, a conductive layer, and a second patterned mask layer are sequentially formed on a semiconductor substrate, and the position of the second patterned mask layer corresponds to the active region and the mask; A part of the curtain layer; using the second patterned mask curtain layer as an etching mask to etch a conductive layer to form a vertical gate; removing the second patterned mask curtain layer; and forming a dielectric layer on the semiconductor substrate, and The dielectric layer is at the same height as the top of the vertical gate to isolate another active area. According to the above-mentioned object, the present invention further provides a method for isolating an active area with a partially vertical memory unit, including the following steps: providing half 0548-9650twF (nl); 91299; Claiie.ptd page 8 200428567

A conductive substrate to form a deep trench capacitor cover curtain layer for each deep trench; in the curtain layer, the first pattern is lower than the isolation deep trench; a layer is formed on the active area layer to expose the top cover mainly in the active area幕 # Engraving the main dielectric layer; a conforming mask curtain layer on the substrate on an ion-doped conductor substrate, the conductive layer is etched with a conductive layer at the semiconductor substrate to complete the active semiconductor substrate trench capacitor, deep trench The height of the first patterned cover curtain layer and the cover layer between the deep trenches is formed on the top side surface; the surface of the semiconductor between the capacitor and the first dielectric region is the surface of the first movable region to make the insulation layer side The edge region is used for performing oxidation stepwise to form a second patterned sub-region; to form a vertical bottom to form a vertical gate region. An insulating layer is formed on the low wall containing the two deep trench capacitors; the semiconductor substrate cover curtain layer is covered with a curtain layer to remove the first half of the columnar & compliant layer on the bottom; it is flat in order and the first intermediate Distance; the active area on top of the active area is used as a source step to form an electrical layer; the second patterned gate is covered on the conductive screen curtain layer; the second dielectric layer electrode is removed to form a trench; A ring-shaped insulation is formed on each of the deep trenches by a ring-shaped insulation on the semiconductor substrate, and the conductor substrate of the masked cover layer immediately forms a sacrificial first dielectric layer and a sacrificial substrate. The corners of the electrical layer are rounded into the ion implantation area; the corresponding active area mask layer is formed on the electrical layer of the sacrificial gate dielectric layer to remove the second dielectric isolation area, and the bottom surface of the deep trench Each layer is filled with a patterned masking knife surface; the + conductor substrate and the masking layer are the active layer bucket layer; the height of the sacrificial layer and the sacrificial layer is low and the sacrificial layer is ; Removing the first step to form the animal layer; half; / Di - engraved pattern and the mask layer covers the screen, the mask layer I; and a dielectric layer regions to be separated from the level of

200428567

In order to make the present invention easier to understand, detailed descriptions are as follows: The fans and other objects, features, and advantages can be made clearer. The preferred embodiments are described in detail with the accompanying drawings. [Embodiment]

Figure 21, Figures 2a-21 are schematic cross-sectional views showing the method of isolating the active area of the memory cell of the present invention. Please refer to Figure 2a. First, a semiconductor substrate 201 is provided. A semiconductor layer 201 is formed on the substrate 201, and the semiconductor substrate 201 includes two deep trenches 201a. The two deep trenches 20a There is a predetermined distance between each other, and the semiconductor substrate between the predetermined distances is the active area defined later, so 'this predetermined distance can be determined according to needs, for example, 丨 200 ～ 丨 400A. The pad layer 202 is, for example, a pad oxide layer or a pad nitride layer.

A conductive layer is filled in the deep trench 201a to serve as a deep trench capacitor 203. The height of the deep trench capacitor 203 is lower than the surface of the semiconductor substrate 201, and the height of the deep trench capacitor 203 is It can be determined according to needs. The distance between the deep trench capacitor 203 and the surface of the semiconductor substrate 001 can determine the vertical channel length of the subsequently formed gate. Among them, a collar-shaped ring-shaped insulating layer 204 is formed on the top side wall of each deep trench 20a to isolate it from the gates that can be formed later. The conductive layer is, for example, a polycrystalline silicon layer; the ring-shaped insulating layer 204 is, for example, an oxide layer. Please refer to FIG. 2b. Next, an isolation layer is formed on the semiconductor substrate 201, the deep trench 20a, and the deep trench capacitor 203 in conformity, and the isolation is performed.

200428567 V. Description of the invention (7) The layer is subjected to an isotropic etching step to remove the isolation layer on the side wall of the deep trench 2 0 1 a until the isolation layer 2 0 5 on the deep trench capacitor 2003 is left. Because the isolation layer is formed on the deep trench 2 0 1 a side wall and the thickness ratio of the deep trench capacitor 2 0 3 surface is less than 1: 8, when removing the isolation layer on the deep trench 2 Ola side wall, the deep trench capacitor 2 0 3 The insulation layer 2 0 5 will not have a considerable impact. Wherein, the insulating layer 2 0 5 is, for example, a top trench oxide (t 〇ptrench oxide) ° Please refer to FIG. 2c, a mask layer 206 is formed on the cushion layer 202, and the mask layer 2 06 will fill the deep trench 201a. . Among them, the cover layer 206 is, for example, an organic anti-reflection layer such as an oxynitride (SiON) layer. Next, the masking layer 206 is planarized until the surface of the cushion layer 202 is exposed, and the masking layer 206a in the deep trench 20a is left, as shown in FIG. 2d. The planarization step is, for example, a chemical mechanical polish step or an etch back step. Referring to FIG. 2e, a photoresist layer 207 is formed on the semiconductor substrate 201 between the two deep trenches 201a. In order to completely cover the semiconductor substrate 201, the photoresist layer 207 will cover a part of the mask layer 2 0 6a. First, please refer to FIG. 2f, the photoresist layer 207 and the mask layer 206 are used as the etching mask to perform anisotropic etching on the semiconductor substrate 201. The height of the semiconductor substrate ... is lower than the isolation conductor substrate 201 The depth is approximately 2600 to 3300 A. Among them, the anisotropic #etch is, for example, plasma #etch (? 1 ^ 11 ^ etching) or reactive ion etching (reactive ion etching); the reaction gas is a hydrogen bromide (HBr) -containing gas

0548-9650twF (nl); 91299; Clairc.ptd

Page 11 200428567

Gas and oxygen-containing (02) gas mixture ^ The silicon layer and the nitride layer have a good choice ## The effect of other structures. ’Hydrogen bromide (HBr) gas-pair poly-etching’

Please refer to Figure 2g, and sequentially remove the R ▽ village nine resistance layer 207 and the mask, so that even the second deep trench 2 (η ρ π, the soap layer Mba to deduct the semiconductor substrate 2Glb between mw-丨It has a large columnar shape, such as b, the protruding columnar body 2 0 1 b between the deep grooves 20a, which is the active area for the subsequent formation of the sun-solar body. Please refer to Figure 2h. N-type γ-για I ions are used to perform an ion implantation step on the bottom corner of the exposed portion of the active region 201b.

Figure 2m of Qing Cang, after the ion implantation step, an ion implantation region 21 () will be formed in the active region 2Gib on the side wall of the isolation layer 205, which will be used as the source drain region and the sacrificial layer 2 0 a 20 lb of the active area can be protected from damage during ion implantation; then, the sacrificial layer 208a is removed. Referring to FIG. 2j, a thermal oxidation step is performed on the semiconductor substrate 200m to form an oxide layer on the exposed surface of the semiconductor substrate 20la & 20lb, which is used as a gate dielectric layer. 2 丨 1. Since the material of the insulating layer 2 05 is also an oxide layer, the insulating layer 2 will not be oxidized again.

Next, a conductive layer 2 1 2 a and a hard mask layer 212 b are formed conformably on the semiconductor substrate 201. The conductive layer 212 is composed of, for example, a polycrystalline silicon layer and a metal silicide layer. The composite layer is used as a gate electrode in the subsequent steps. The metal silicide layer is, for example, tungsten silicide (WSi), and the hard mask layer 2 1 2 b is, for example, a nitride layer. Then, a pattern is formed on the conductive layer 212a and the hard mask layer 21 2b.

0548-9650twF (nl); 91299; Glaire.ptd Page 12 200428567 V. Description of the invention (9) Mask layer 213, the patterned mask layer 213 is, for example, a photoresist layer formed on the conductive layer 212a corresponding to the active region 201b And hard cover curtain layer 212b; and in order to fully cover the conductive layer 21 2a and hard cover curtain layer 2 1 2 b corresponding to the active area 20 lb, the 'patterned cover curtain layer 2 1 3 will also cover part of the corresponding The conductive layer 212a and the hard cover curtain layer 212b of the isolated area 2 05. Please refer to FIG. 2k ', using the patterned mask layer 2 0 3 as a money mask mask, the conductive layer 21 2a and the hard mask layer 21 2 b are sequentially etched to expose the unpatterned mask layer 2 0 3 The gate dielectric layer 21 and the insulating layer 205 are covered so as to form a conductive layer 212c and a hard mask layer 212d surrounding the active region 201b. Next, after the patterned mask layer 203 is removed, a dielectric layer 2 1 4 is formed on the semiconductor θ substrate 201, and a planarization step is performed on the dielectric layer 2 1 4 to make the dielectric layer 21 4 and conductive. The tops of the layer 212c and the hard cover curtain layer 21 2d are substantially the same height, as shown in FIG. 2p. The dielectric layer 2 4 is, for example, a high density plasma (HDP) oxide layer, and is used as an isolation region between the active R 2 0 1 b. °° According to the present invention, in the active region process of a dynamic random access memory cell with a partially vertical channel transistor, an anti-reflection layer can be formed as a self-aligned mask in a deep trench. Reducing the number of masks can effectively reduce production time and costs. At the same time, because the anti-reflection layer is an etching mask, it can avoid etching to the collar-shaped ring of the deep trench: Layer: Therefore, it is possible to use a polysilicon layer and a nitrided layer with good selective etching: Emulsion, such as bromination Hydrogen gas is used as an etching reaction gas. Although the present invention has been disclosed and limited by the preferred embodiments, anyone skilled in the art is as above but it is not intended to depart from the spirit of the present invention.

200428567 V. Description (10) and scope of the invention shall be modified and retouched. Therefore, the scope of protection of the present invention shall be determined by the scope of the attached patent application.

0548-9650twF (nl); 91299; Claire.ptd Page 14 200428567 Brief description of the drawings Figure 1 a-Ί e is a schematic cross-sectional view showing a conventional transistor with a partial vertical channel. Figures 2a to 21 are schematic sectional views showing the method for isolating the active area of a memory unit with a partial vertical channel according to the present invention. Explanation of symbols: 1 (Π ~ p-type silicon substrate; 102 ~ column area, «103a ~ thin pad oxide layer; 103b ~ oxynitride layer; 104 ~ deep trench; 105 ~ heavily doped Oxide; 106 ~ n + diffusion region; 107 ~ top oxide layer-nitride layer-bottom oxide layer 108 ~ capacitor plate; 109 ~ shielding oxide layer; 110 ~ gate oxide; 111 ~ control Gate electrode; 11 2 ~ n + > and pole region, 11 3 ~ bit line metal layer; 201, 201b ~ semiconductor substrate; 201a ~ deep trench; 202 ~ 塾 layer; 230 ~ deep trench capacitor;

0548-9650twF (nl); 91299; Claire.ptd page 15 200428567 The diagram briefly explains 2 0 4 ~ ring insulation layer; 2 5 5 ~ insulation layer; 2 0 6 ~ cover layer; 2 0 7 ~ photoresist 2 1 0 ~ ion implanted area; 2 1 1 ~ gate dielectric layer; 212a, 212c ~ conductive layer; 212b, 212d ~ hard cover curtain layer; 2 1 3 ~ patterned cover curtain layer; 2 1 4 ~ Dielectric layer.

0548-9650twF (nl); 91299; Claire.ptd page 16

Claims (1)

200428567 VI. Scope of patent application 1. A method for isolating an active area of a memory cell with a partial vertical channel, including the following steps: providing a semiconductor substrate 'the semiconductor substrate includes a two-bead trench', and a deep trench is formed in each of the deep trenches Trench capacitors, and the deep trench capacitors are lower than the surface of the semiconductor substrate, so that the deep trenches become a protruding pillar-shaped active area; an ion implantation step is performed on the bottom corner of the active area exposed on the surface to form an ion A doped region for use as a source drain region; a gate dielectric layer and a conductive layer are sequentially formed on the surface of the active region; the conductive layer is used as a vertical gate; and on the semiconductor substrate A dielectric layer is formed, and the dielectric layer is at the same height as the top of the vertical gate to isolate another active region. 2. The method of isolating an active region with a partially vertical channel memory cell as described in item 1 of the scope of the patent application, wherein the gate dielectric layer is a gate oxide layer. 3. The method of isolating an active region of a memory cell having a partially vertical channel as described in item 2 of the scope of the patent application, wherein the method of forming the gate oxide layer is a thermal oxidation method. 4. The method for isolating an active area of a memory cell having a partially vertical channel as described in item 1 of the scope of the patent application, wherein the conductive layer is a polycrystalline silicon layer. 5. The method for isolating an active region having a partially vertical channel memory cell as described in item 1 of the scope of the patent application, wherein the dielectric layer is an oxide layer. 6. —A method for isolating the active area of a memory cell with a partial vertical channel, including the following steps: 0548-9650twF (nl); 91299; Clairc.ptd Page 17 200428567 6. The scope of the patent application is 1 for a semiconductor substrate, which contains two deep trenches. A deep trench capacitor is formed in each of these deep trenches, and The deep trench capacitors are lower than the surface of the semiconductor substrate; an isolation layer is formed on the surface of the mother bead trench capacitor; a cover layer is filled in each deep trench; on the semiconductor substrate between the deep trenches such as 5 Hai Forming a first patterned mask layer, wherein the first patterned mask layer covers a part of the surfaces of the mask layers; The first patterned mask layer and the mask layers are used as etching masks, and the semiconductor substrate is etched to a height lower than the isolation layer to form a protruding columnar active area; removing the first patterned mask A curtain layer and the cover curtain layers; performing an ion implantation step on the active region on the side of the isolation layer to form an ion doped region for use as a source drain region; and sequentially forming a semiconductor substrate on the semiconductor substrate A gate dielectric layer, a conductive layer, and a second patterned mask layer; the position of the second patterned mask layer corresponds to the active area and a part of the mask layer; The second patterned mask is used as an etching mask, and the conductive layer is etched to form a vertical gate. The second patterned mask is removed to form a dielectric layer on the semiconductor substrate, and the dielectric layer and The top of the straight gate is of the same height to isolate another ^ θ θ + η /, + [Isolation has a partial vertical ij 7 · The% -like insulating layer in the glycoside as described in item 6 of the patent application is a collar-shaped channel圯 fe early method of active zone, its r master 200428567 ~, patent application scope Electric layer. 8. Such as applying for a patent layer. Method, in which the ring-shaped insulating layer is oxidized, f 2 !: The isolation described in item 6 of the scope of patent application has a partial vertical connection, the main description of the predecessor, aa, earth, and 10. If applying for a patent ° ° τ Λ method, wherein the insulating layer is an oxide layer. Heritage _ _ The isolation described in item 6 of Qianwei has a partial vertical channel memory unit ΛΛΙΓΛ16. The isolation Γ has a partial vertical reaction gas that is the inverse of a hydrogen bromide-containing semiconductor substrate ^ κ a etiquette and oxygen-containing gas The mixed gas. The method of isolating a partially vertical pass region as described in item 6 of the Dow claims patent scope, which "etches the semiconductor substrate",% 13. The method of isolating the active region with a partially vertical pass: layer as described in item 6 of the scope of patent application, wherein the gate dielectric layer is gate oxygen ...: U. As described in ^ 3 of the scope of patent application The method of isolating the active region with a part of the vertical i? I: cell is described, and the gate oxide layer is formed by a thermal oxidation method. I5. The method for isolating an active region having a partially vertical pass-through memory cell as described in item 6 of the scope of the patent application, wherein the conductive layer is a polycrystalline silicon layer. 6. The method of isolating an active region having a partial vertical driving force of a C-membrane as described in item 6 of the patent application park, wherein the dielectric layer is an oxide layer. 〇548-9650twF (nl); 91299: Claire.ptd Page 19 200428567 VI. Patent Application Range 1 7. A method for isolating the active area of a memory cell with partial vertical channels, including the following steps: providing a semiconductor substrate, the The semiconductor substrate includes two deep trenches; a deep trench capacitor is formed in each deep trench, the deep trench capacitors are lower than the surface of the semiconductor substrate, and a ring-shaped insulating layer is formed on the top sidewall of each deep trench; An isolation layer is formed on the surface of a deep trench capacitor; a mask layer is filled in each deep trench; a first patterned mask layer is formed on the semiconductor substrate between the deep trenches, wherein the first pattern The masking layer covers a part of the surfaces of the masking layers; using the first patterned masking layer and the masking layers as an etching mask, the semiconductor substrate is etched to a height lower than the insulating layer; removing the first A patterned mask layer and the mask layers, wherein the semiconductor substrate with protruding columns between the deep trench capacitors is an active area; the semiconductor substrate outside the active area A sacrificial layer is formed conformably on the bottom; a first dielectric layer is formed on the sacrificial layer; the first dielectric layer and the sacrificial layer are sequentially planarized to the surface exposing the active region, and the first dielectric The height of the electrical layer and the sacrificial layer is lower than a predetermined distance from the top surface of the active region; etching the active region with the first dielectric layer and the sacrificial layer as a mask to round the top corner of the active region; remove The first dielectric layer; 0548-9650twF (nl); 91299; Claire.ptd Page 20 200428567 6. Application scope of patent The ion implantation step is performed on the active region on the side of the isolation layer to form an ion doped region for use as a source sink. Polar region; removing the sacrificial layer; performing an oxidation step on the semiconductor substrate to form a gate dielectric layer; compliantly forming a conductive layer on the semiconductor substrate; forming a second patterned mask on the conductive layer Layer, the second patterned mask layer covers a portion of the conductive layer corresponding to the active area and the mask layers; the second patterned mask layer is #etched mask, and the conductive layer is engraved with Forming a vertical gate; removing the second patterned mask layer; and forming a second dielectric layer on the semiconductor substrate to perform a planarization step on the second dielectric layer to expose the vertical gate to form a Isolation area, which is used to isolate another active area. 1 8 · The method for isolating an active area of a memory cell having a partial vertical channel as described in item 17 of the scope of the patent application, wherein the blanket insulation layer is a collar-type dielectric device r 〇1 9 · The method of separating the active area of a memory cell with a partial vertical channel as described in item 7, wherein the clothing-like, lamellae layer is oxidized, and the isolation is partially vertical, wherein the insulation layer is an oxide layer. The isolation has a partially vertical layer. 2 0. If the scope of the patent application item 17 The method of the active area of the channel memory unit 2 1 · If the scope of the patent application item 17 200428567 VI. Patent Application Method of the active area of the channel memory unit, wherein the mask layer is an anti-reflection layer. 2 2. The method for isolating an active region with a partially vertical channel memory cell as described in item 17 of the scope of the patent application, wherein the reaction gas of the semiconductor substrate is a mixed gas of hydrogen bromide-containing gas and oxygen-containing gas. 2 3 · The method for isolating an active area of a memory cell having a partial vertical channel as described in item 17 of the scope of the patent application, wherein the method of engraving the semiconductor substrate is anisotropic etching. 24. The method of isolating an active area of a memory cell having a partially vertical channel as described in item 17 of the scope of the patent application, wherein the sacrificial layer is a nitrided layer. 25. The method of isolating an active area of a memory cell having a partial vertical channel as achieved in item 17 of the scope of the patent application, wherein the first dielectric layer is an oxide layer. 2 6. The method for isolating an active area of a memory cell having a partial vertical channel as described in item 17 of the scope of the patent application, wherein the idler dielectric layer is a gate oxide layer. 2 7. The method for isolating an active area of a memory cell having a partially vertical channel as described in item 17 of the scope of the patent application, wherein the conductive layer is a polycrystalline silicon layer. 2 8. The method for isolating an active region with a partially vertical channel memory cell as described in item 17 of the scope of patent application, wherein the second dielectric layer is an oxide layer. 0548-9650twF (nl); 91299; Claire.ptd page 22