TWI223377B - Method for isolating the active area of a memory cell with partial vertical channel - Google Patents

Abstract

A method for isolating the active area of a memory cell with partial vertical channel is provided. First, provide a semiconductor substrate that contains two deep trenches. In each deep trench, a deep trench capacitor is formed and the capacitor is below the substrate surface. Second, form a protruding column type active area between the deep trenches, and conduct ion implantation process on the bottom corner of the exposed active area to form ion doped areas that are as source/drain areas. Third, sequentially form a gate dielectric layer and a conduction layer on the active area surface. The conduction layer is used to be a vertical gate. Form a dielectric layer on the substrate to isolate the other active area. The height of the said dielectric layer is equal to the top of the vertical gate.

Description

1223377

[Technical field to which the invention belongs] The present invention relates to a method for manufacturing an isolation element, and more particularly, to a method for isolating an active region having a vertical transistor and a deep trench capacitor. [Previous Technology] When fabricating high-density implanted semiconductor components on integrated circuit wafers, it is necessary to consider how to reduce the size and power consumption of each memory cell in order to speed up its operation speed. In the traditional planar transistor design, in order to obtain a memory cell of the smallest size, the gate length of the transistor must be made as short as possible 'to reduce the lateral area of the delta element. However, this will make the gate unable to tolerate a large leakage current and must correspondingly reduce the voltage on the bit line, thereby reducing the charge stored in the capacitor. Therefore, while reducing the lateral length of the gate, it is also necessary to consider how to make a Capacitors with large capacitance, such as: increasing the area of the capacitor, reducing the effective dielectric thickness between the capacitor plates, and so on. Since the conditions for reducing the memory cell area and increasing the capacitor area cannot be met in actual production, and the thickness of the effective medium cannot be further reduced, a vertical transistor structure has been developed to maintain the gate length. At an appropriate value for obtaining a low leakage current, not only the bit line voltage is not reduced, nor the lateral area of the memory cell is increased. In addition, a deep trench capacitor has also been developed, which is placed directly below the vertical transistor without occupying an additional area of the memory cell. A deep trench capacitor is disclosed in U.S. Patent No. 6,034,389

1223377

Self-aligned diffused source vertical transistor. Please refer to the la-le diagram. The la-le diagram is a schematic cross-sectional view of a conventional transistor with a vertical channel. A conventional manufacturing method is to form a plurality of deep trenches 104 and corresponding protruding columnar regions 102 on a P-type silicon substrate 101, so that the deep trenches 104 isolate every two columnar regions 102. As shown in FIG. 1a, a thin pad oxide layer 103a and an oxynitride layer 103b are provided on the surface of the columnar region 102 to define the region of the columnar region 102. First, a heavy layer is formed on the sidewall of the area below the deep trench, and a dopant oxide 105 (such as arsenic glass ASG) is used as a source diffusion material, and then a short-time annealing process is performed at high temperature to diffuse arsenic An n-type heavily doped (n +) diffusion region 106 is formed on the sidewall of the columnar region 102, and is used as a #source region 106 and a storage electrode of a deep trench capacitor to be manufactured later. Subsequently, as shown in FIG. 1 b, the heavily doped oxide 105 is removed. Then, as shown in FIG. 1c, a 100N thin film 107 is grown on the inner sidewall of the deep trench 104 as a medium for the deep trench capacitor. Next, an η + polycrystalline silicon layer 108 is deposited in the deep trench 104 as the capacitor plate 108 of the trench capacitor, and the ONO film 107 and the η + polycrystalline silicon layer 108 are etched to a predetermined depth. Then, as shown in FIG. Id, the n + polycrystalline silicon layer 10 in the deep trench 104 is covered with a barrier oxide layer 10 9 so as to isolate the gates made later. Subsequently, a gate oxide is grown on the sidewall in the deep trench 104, and an n + polycrystalline silicon layer 111 is filled in the deep trench 104 as a control gate 111. Then, as shown in FIG. 1e, the gate electrode 111 is etched to isolate the word lines, and the thin pad oxide layer 103a and the oxynitride layer 103b are removed, and then planted at the top of each pillar region 102. Into an n + drain region 11 2. Finally form an AND word line

1223377 V. Description of the invention (3) The vertical bit line metal layer 11 3 will complete the memory cell array. It can be known from the above that in each memory cell, the control gate n, the n + source region 106, and the #drain region 112 constitute a vertical transistor, and the n + diffusion regions 106 and 0N0 films located below the vertical transistor. 107 and the n + polycrystalline silicon layer 108 constitute a deep trench capacitor. In an open bitline architecture, all memory cells share a polycrystalline silicon capacitor plate 108, and charges are stored in each columnar region 22 diffusion region 1G6. The top of the columnar region 1 () 2 can be used as a channel between the n + source region and the n + drain region 112, but in order to avoid two adjacent source regions 1 on the inner sidewall of the columnar region 102. 6 produces empty regions (regions) are too close and overlapping, the F π of the septum cone of the cylindrical region 102 is reduced, plus the isolation & visibility that effectively isolates the cylindrical region 102 Will reduce the unit density. "Jibu" along the ridge of the remembrance 7L [Content of the invention] In view of this, the purpose of the present invention is a Μ +, animal, storage θ ®-month is for the purpose of isolation for some Φ acre channels Lu Ji Shi Si 70 The method of the main service is to apply the knife to the king, which is suitable for kinetic energy with the unit, and effectively isolates each active area. 2. Use memory to access the memory. According to the above purpose, Tailu, 々Ρ 4 4 1 Benmemin & For a kind of taxi i A, Θ with active area of 8000 and 7000, The method of external division and vertical work / (he) includes the following steps. The semiconductor chip can be used for half the soil. The deep groove has a deep groove, and the deep groove has a deep groove. 1 ^ φ h wooden grooves are formed in the wooden grooves so that the deep grooves become a protrusion # ^, the surface of the base of the body is large, and the columnar active area is large;

1223377 V. Description of the invention (4) The bottom corner of the area is used as a source layer and a conductive layer for the drain region layer and ion implantation; a dielectric layer is formed on the active substrate to dielectrically isolate the other ground. The channel memory single conductor substrate is formed with a deep trench; a patterned mask surface is filled within each depth; the conductor substrate to the area; the movable area is removed to remove the source drain region; the electrical layer and a first active Area and engraved masks, the remaining mask layers; and the top gate of the straight gate according to the main channel memory single active area described in the main semiconductor trench capacitor trench electrical curtain layer; a layer whose pattern is lower than the spaced apart pattern The semiconductor layer is engraved on the semiconductor layer with a patterned mask layer, which is electrically conductive on the semiconductor layer and other high-order elements to form an ion-doped region. The surface is sequentially formed with gate dielectric as vertical gate. The semiconductor layer is at the same height as the top of the vertical gate, and the square substrate of the moving region of the present invention includes a step of increasing the height of the mask layer of the first patterned mask layer in the deep trench on the surface of the deep trench. The part of the mask layer on the substrate The partition layer is formed on the body substrate for isolation, and the movable region of the present invention further provides an isolation method, which includes the following: a deep trench having a trench capacitance lower than that of the semiconductor-based masking layer covering and covering forming an isolation layer; The curtain layer is left to form a mask layer; a gate and a second domain are sequentially formed by doping an ion dopant; a method of forming a series of gates is provided in a vertical direction, and a second pattern gate is provided, including patterning the second gate. The active region of the dielectric layer has a partial vertical step: providing a semi-deep trench in the shape of the semiconductor substrate surface; forming a part of the mask on the bottom of each deep trench. The main area on the side of the active insulation layer is used as a polar dielectric layer and a conductive mask layer. The second pattern is removed from the mask layer and the dielectric layer is separated from the vertical layer. Partially verticalize the following steps: provide half

1223377 V. Description of the invention (5) A conductive substrate, a semiconductor substrate including two deep trenches; a deep trench capacitor is formed in each deep trench, and the deep trench capacitance is lower than the surface of the semiconductor substrate, wherein the top sidewall of each deep trench is formed A ring-shaped insulating layer; forming an isolation layer on the surface of each deep trench capacitor; filling a cover layer in each deep trench; forming a first patterned cover layer on a semiconductor substrate between the deep trenches, The first patterned mask layer covers a part of the surface of the mask layer; using the first patterned mask layer and the mask layer as an etching mask, the semiconductor substrate is etched to a height lower than the isolation layer; the first patterned mask is removed Curtain layer and cover curtain layer, in which the protruding columnar semiconductor substrate between deep trench capacitors is an active area; a sacrificial layer is conformably formed on the semiconductor substrate outside the active area; a first dielectric is formed on the sacrificial layer Layer; sequentially planarize the first dielectric layer and the sacrificial layer to the surface exposing the active region, and the height of the first dielectric layer and the sacrificial layer is lower than a predetermined distance from the top surface of the active region; The sacrificial layer and the sacrificial layer etch the active region to round the top corner of the active region; remove the first dielectric layer; perform an ion implantation step on the active region on the side of the isolation layer to form an ion-doped region for As a source drain region; removing the sacrificial layer; performing an oxidation step on the semiconductor substrate to form a gate dielectric layer; compliantly forming a conductive layer on the semiconductor substrate; forming a second patterned mask on the conductive layer Layer, the second patterned mask layer covers a portion of the conductive layer corresponding to the active area and the mask layer; using the second patterned mask layer as an etching mask, the conductive layer is etched to form a vertical gate; removing the second Patterning the mask layer; and forming a second dielectric layer on the semiconductor substrate, performing a planarization step on the second dielectric layer until the vertical gate is exposed to form an isolation region, which is used to isolate another active region.

0548-9650twF (nl); 91299; Claire.ptd page 9 1223377

In order to make the above and other objects of the present invention easier, the following is enumerated—preferably described as follows: The features, characteristics, and advantages can be made clearer, and will be described in detail with the accompanying drawings.

[Embodiment] Please refer to Figs. 2a-21, Chu 9 〇1 a part of a vertical channel memory unit a = diagram showing the isolator of the present invention Please refer to Fig. 2a, first, a schematic cross-sectional view. A body substrate 201 is formed with —sounds 2, — = conductor substrate 201 'semiconducting' and the semiconductor substrate 201 includes an ice trench 201a. The two deep trenches 201 are separated from each other by a predetermined distance. The semiconductor substrate is the active area defined later, so 'this predetermined distance can be determined as needed, such as 12,000 to 1400A. Wherein, the hafnium layer 202 is, for example, a pad oxide layer or a pad nitride > f. In the deep trench 2 01a, a-$ electric layer is used as a $ trench capacitor 203, a deep trench. The height of the capacitor 203 is lower than the surface of the semiconductor substrate 201. The height of the deep trench capacitor 203 can be determined as needed. The distance between the deep trench 203 and the surface of the semiconductor substrate 201 can determine the length of the vertical channel of the subsequently formed gate. . Among them, a collar-shaped ring-shaped insulating layer 204 is formed on the top side wall of each deep trench 20a, which can be used to continue with subsequent ones.

Continued gates are used for isolation. Among them, the conductive layer is, for example, a polycrystalline stone layer; the ring-shaped insulating layer 204 is, for example, an oxide layer. M Please refer to FIG. 2b. Next, an isolation layer is formed on the semiconductor substrate 201, the deep trench 201a and the deep trench capacitor 203 in conformity, and the insulation layer

1223377 V. Description of the invention (7) The layer is subjected to an isotropic engraving step to remove the insulating layer on the side wall of the deep trench 20a, until the insulating layer 205 on the deep trench capacitor 203 is left. Because the insulation layer 7 is formed on the sidewall of the deep trench 20 la and the thickness ratio 2 on the surface of the deep trench capacitor 20 is less than 1: 8, when removing the insulation layer on the sidewall of the deep trench 20 la, the deep trench capacitor 2 is removed. The isolation layer 205 on 〇3 will not have a considerable impact. The 'isolation layer 20 5 is, for example, a top trench oxide. Please refer to FIG. 2C. A mask layer 206 is formed on the cushion layer 202. The mask layer 206 will fill the deep trenches 20 la. The mask layer 206 is, for example, an organic anti-reflection layer such as a silicon oxynitride (Si ON) layer. Next, a planarization step is performed on the mask layer 206 until the surface of the cushion layer 200 is exposed, and the mask layer 206a in the deep trench 20a is left, as shown in FIG. 2d. The planarization step is, for example, a chemical mechanical polish step or an etch b a c k step.凊 Referring to FIG. 2e, a photoresist layer 207 is formed on the semiconductor substrate 201 between the two deep trenches 201a. In order to completely cover the semiconductor substrate 201, the photoresist layer 207 will cover a part of the mask layer 2. 6a. Please refer to FIG. 2f, and use the photoresist layer 207 and the mask layer 206a as the last name to engrav the mask. Up to 205, the depth of the etched semiconductor substrate 201 is about 2600 to 3300A. Among them, the anisotropic #etch is, for example, plasma etching or reactive ion etching; the reaction gas is a hydrogen-containing hydrogen (HBr) gas.

0548-9650twF (nl); 91299; Claire.ptd Page 11 1223377 V. Description of the invention (8) ~ " Mixed gas of gas and oxygen-containing (〇2) gas, hydrogen bromide (HBr) -containing polycrystalline The Shi Xi layer and the nitride layer have good selective etching, which can reduce the influence on other structures when etching the substrate. 〃 Please refer to Figure 2g, 'Sequentially remove the photoresist layer 207 and the mask layer 206a. In this way, even if the semiconductor substrate 2 〇 丨 b between the two deep trenches 2 〇a is a protruding column, so As a result, the protruding columnar semiconductor substrate 20 lb between the two deep trenches 20 a is the active area for the subsequent formation of the transistor position. Referring to FIG. 2h, the ion implantation step is performed by using the N-type ion to the bottom corner of the exposed portion of the active region 20b. Please refer to FIG. 21 of McCaw. After the ion implantation step, an ion implantation region 21 will be formed in the active region 201b of the side wall of the isolation layer 205, which is used as a source drain region. The sacrificial layer 208a can The protective active region 201b is destroyed during the implantation; then, the sacrificial layer 208a is removed. Referring to FIG. 2j, a thermal oxidation step is performed on the semiconductor substrate 201 to form an oxide layer on the surface of the semiconductor substrate 201a & 20lb, which is used as a gate dielectric layer. 2 丨 i. Because the material of the insulating layer 205 is also an oxide layer, the insulating layer 205 will not be oxidized again.

Next, a conductive layer 212a and a hard mask layer 212b are formed conformably on the semiconductor substrate 201. The conductive layer 212 is, for example, a composite layer composed of a polycrystalline silicon (poly) layer and a metal silicide layer for subsequent use. Used as a gate electrode; where the metal silicide layer is, for example, tungsten silicide (WSi hard mask layer 21 2b is, for example, a nitride layer. Then, a pattern is formed on the conductive layer 212a and the hard mask layer 21 2b.

〇548-9650twF (nl); 91299; Clairc.ptd Page 12 1223377 V. Description of the invention (9) Mask layer 2 1 3 'The patterned mask layer 2 1 3 is, for example, a photoresist layer' formed in the corresponding active region The conductive layer 212a of 201b and the hard cover curtain layer 212b; and in order to completely cover the conductive layer 212a and the hard cover curtain layer 2 1 2b corresponding to the active area 201b, the patterned cover curtain layer 2 1 3 will also be covered. Partly corresponds to the conductive layer 212a and the hard mask layer 212b of the isolation region 205. Please refer to FIG. 2k ', using the patterned mask layer 203 as the money mask mask, sequentially perform #etching on the conductive layer 212a and the hard mask layer 212b to expose the gate electrode that is not covered by the patterned mask layer 2 0 3 The dielectric layer 2 11 and the insulating layer 2 05 are formed to form a conductive layer 212 c and a hard mask layer 212 d that surround the active region 201 b. Next, after the patterned mask layer 203 is removed, a dielectric layer 2 1 4 is formed on the semiconductor substrate 201, and a planarization step is performed on the dielectric layer 2 1 4 to make the dielectric layer 214 and the conductive layer 212c. And the top of the hard cover curtain layer 212d is substantially the same height, as shown in FIG. 2p. The dielectric layer 214 is, for example, a high density plasma (HDP) oxide layer, and is used as an isolation region between the active regions 2 0 1 b. According to the present invention, in the active-area process of eight-blade vertical channel transistors suitable for dynamic random access memory cells, an anti-reflection layer can be formed in a deep trench as a self-aligned mask. Reducing the number of photomasks effectively reduces production time and costs. At the same time, because the anti-reflection layer is used as the etching mask, the collar-shaped ring-shaped insulating layer 1 that can be etched to the deep trenches can be avoided. As the etching reaction gas, for example, hydrogen bromide gas is used. The invention has been disclosed as above with preferred embodiments, but it is not intended to limit the present invention. Anyone skilled in the art will not depart from the spirit of the present invention.

II,

0548-9650twF (nl); 91299; Claire.ptd 1223377 V. Within the scope of the invention description (ίο) and modifications can be made and retouched, so the scope of protection of the present invention shall be determined by the scope of the attached patent application . IBii 0548-9650twF (nl); 91299; Clairc.ptd Page 14 1223377 Brief description of the diagrams Figures 1 a-1 e are schematic cross-sectional views of conventional transistors with partial vertical channels. Figures 2a-21 are schematic cross-sectional views showing the method for isolating the active area of a memory cell with a partial vertical channel according to the present invention. Explanation of symbols: 1 0 1 ~ p-type silicon substrate; 10 2 ~ columnar area, 1 0 3 a ~ thin hafnium oxide layer; 103b ~ oxynitride layer; 104 ~ deep trench; 105 ~ heavy Doped oxide; 106 ~ n + diffusion region; 107 ~ top oxide layer-nitriding layer-bottom oxide layer; 108 ~ capacitor plate; 109 ~ barrier oxide layer; 110 ~ gate oxidation Object; 111 ~ control gate; 11 2 ~ n + non-electrode region; 11 3 ~ bit line metal layer; 201, 201b ~ semiconductor substrate; 2 0 1 a ~ deep trench; 2 0 2 ~ 0 layer; 203 ~ deep trench Slot capacitance

0548-9650twF (nl); 91299; Clairc.ptd Page 15 1223377 The diagram briefly explains 2 0 4 ~ ring insulation layer; 2 5 5 ~ insulation layer; 20 6 ~ cover layer; 2 0 7 ~ photoresist layer 2 1 0 ~ ion implantation area; 2 11 ~ gate dielectric layer; 212a, 212c ~ conductive layer; 212b, 212d ~ hard cover curtain layer; 213 ~ patterned cover curtain layer; 2 1 4 ~ dielectric layer .

0548-9650twF (nl); 91299; Clairc.ptd page 16

Claims (1)

Ί 12 愼 (if, ΓΡ # 晚 92114881_July 5th, 2007 revised beam_ VI. Patent application scope 1. A method for isolating an active area with a partially vertical channel memory cell, including the following steps: Provide a semiconductor substrate The semiconductor substrate includes two deep trenches. A deep trench capacitor is formed in each of the deep trenches, and the deep trench capacitances are lower than the surface of the semiconductor substrate, so that the deep trenches become a protruding columnar active area; An ion implantation step is performed at the bottom corner of the active region on the surface to form an ion doped region for use as a source-inverted region; a gate dielectric layer and a conductive layer are sequentially formed on the surface of the active region, The conductive layer is used as a vertical gate; and a dielectric layer is formed on the semiconductor substrate, and the dielectric layer is at the same height as the top of the vertical gate to isolate another active region. The method for isolating an active area of a memory cell having a partial vertical channel as described in the first item of the scope, wherein the gate dielectric layer is a gate oxide layer. 3. As described in the second item of the patent application scope A method for isolating an active region with a partially vertical channel memory cell, wherein the method for forming the gate oxide layer is a thermal oxidation method. 4. Isolating an active region with a partially vertical channel memory cell as described in item 1 of the scope of patent application Method, wherein the conductive layer is a polycrystalline silicon layer. 5. The method for isolating an active area of a memory cell with a partial vertical channel as described in item 1 of the patent application scope, wherein the dielectric layer is an oxide layer. The method for the active area of a certain vertical channel memory unit includes the following steps: 0548-9650TWFl (4.5); 91299; jamngwo.ptc page 17 1223377 _ case number 92114881 _ month and month amends_ Sixth, the scope of the patent application provides a semiconductor substrate, the semiconductor substrate includes two deep trenches, A deep trench capacitor is formed respectively, and the deep trench capacitors are lower than the surface of the semiconductor substrate; an isolation layer is formed on the surface of each deep trench capacitor; a cover layer is filled in each deep trench; A first patterned mask layer is formed on the semiconductor substrate between the trenches, wherein the first patterned mask layer covers a part of the surfaces of the mask layers; the first patterned mask layer and the masks are formed The layer is an etching mask, and the semiconductor substrate is etched to a height lower than the insulating layer to form a protruding columnar active area; the first patterned mask layer and the mask layers are removed; and the insulating layer side An ion implantation step is performed on the active region on the edge to form an ion doping region as a source / anion region; a gate dielectric layer, a conductive layer, and a second pattern are sequentially formed on the semiconductor substrate. Turn into The curtain layer, the position of the second patterned mask layer corresponding to the active area and a part of the mask layers; using the second patterned mask layer as an etching mask, the conductive layer is etched to form a vertical gate Electrode; removing the second patterned mask layer; and forming a dielectric layer on the semiconductor substrate, and the dielectric layer is at the same height as the top of the vertical gate to isolate another active region. 7. The method of isolating an active region having a partially vertical channel memory cell as described in item 6 of the scope of the patent application, wherein the isolation layer is an oxide layer. 0548-9650TWFl (4.5); 91299; jamngwo.ptc page 18 1223377 _ case number 92114881 _ month and day _ _ _ 6, the scope of the patent application 8. The isolation as described in the 6th scope of the patent application has a partial vertical channel memory The active area method of the unit, wherein the mask layer is an anti-reflection layer. 9. The method of isolating an active region having a partially vertical channel memory cell as described in item 6 of the scope of the patent application, wherein the reaction gas for etching the semiconductor substrate is a mixed gas of a hydrogen bromide-containing gas and an oxygen-containing gas. 10. The method for isolating an active area of a memory cell having a partially vertical channel as described in item 6 of the scope of the patent application, wherein the method of etching the semiconductor substrate is anisotropic etching. 11. The method of isolating an active region having a partially vertical channel memory cell as described in item 6 of the scope of the patent application, wherein the gate dielectric layer is a gate oxide layer. 1 2. The method for isolating an active area of a memory cell having a partially vertical channel as described in item 11 of the scope of the patent application, wherein the gate oxide layer is formed by a thermal oxidation method. 1 3. The method for isolating an active area of a memory cell having a partially vertical channel as described in item 6 of the scope of the patent application, wherein the conductive layer is a polycrystalline silicon layer. 1 4. The method for isolating an active area of a memory cell having a partial vertical channel as described in item 6 of the scope of the patent application, wherein the dielectric layer is an oxide layer. 1 5. A method for isolating an active area of a memory cell having a partial vertical channel, including the following steps: providing a semiconductor substrate including two deep trenches; forming a deep trench capacitor in each deep trench, etc. The deep trench capacitance is lower than the surface of the semiconductor substrate, and a ring-shaped insulating layer is formed on the top sidewall of each deep trench; 0548-9650TWFl (4.5); 91299; jamngwo.ptc Page 19 1223377 _Case No. 92114881_ Month and Revise_ Sixth, the scope of the patent application forms an insulation layer on the surface of each deep trench capacitor; within each deep trench Filling a mask layer; forming a first patterned mask layer on the semiconductor substrate between the deep trenches, wherein the first patterned mask layer covers a part of the surface of the mask layer; using the first A patterned mask layer and the mask layers are etching masks, and the semiconductor substrate is etched to a height lower than the isolation layer; the first patterned mask layer and the mask layers are removed, wherein the deep grooves The protruding semiconductor column substrate between the trench capacitors is an active region; a sacrificial layer is conformably formed on the semiconductor substrate outside the active region; a first dielectric layer is formed on the sacrificial layer; sequentially flat Changing the first dielectric layer and the sacrificial layer to the surface exposing the active region, and the height of the first dielectric layer and the sacrificial layer being lower than a predetermined distance from the top surface of the active region; using the first dielectric Layer and the sacrificial layer Engraving the active region to round the top corner of the active region; removing the first dielectric layer; performing an ion implantation step on the active region on the side of the isolation layer to form an ion doped region for use as A source drain region; removing the sacrificial layer; performing an oxidation step on the semiconductor substrate to form a gate dielectric layer; compliantly forming a conductive layer on the semiconductor substrate; 0548-9650TWF1 (4.5); 91299; jamngwo.ptc page 20 1223377 _ case number 92114881 _ month and month amend _ 6. The scope of the patent application forms a second patterned cover layer on the conductive layer, the second pattern The masking layer covers a part of the conductive layer corresponding to the active area and the masking layer. The second patterned masking layer is used as an etching mask, and the conductive layer is etched to form a vertical gate. A second patterned mask layer; and forming a second dielectric layer on the semiconductor substrate, performing a planarization step on the second dielectric layer to expose the vertical gate electrode to form an isolation region, the isolation region being used for Isolate another active area. 16. The method for isolating an active area of a memory cell having a partially vertical channel as described in item 15 of the scope of the patent application, wherein the ring-shaped insulating layer is a collar-type dielectric layer. 1 7. The method for isolating an active area of a memory cell having a partially vertical channel as described in item 15 of the scope of the patent application, wherein the ring-shaped insulating layer is an oxide layer. 1 8. The method for isolating an active region of a memory cell having a partial vertical channel as described in item 15 of the scope of the patent application, wherein the insulating layer is an oxide layer. 19. The method for isolating an active area of a memory cell having a partial vertical channel as described in item 15 of the scope of the patent application, wherein the cover layer is an anti-reflection layer. 20. The method for isolating an active region having a partially vertical channel memory cell as described in item 15 of the scope of the patent application, wherein the reaction gas for etching the semiconductor substrate is a mixed gas of a hydrogen bromide-containing gas and an oxygen-containing gas. 2 1. The isolation described in item 15 of the scope of patent application has partial verticality 0548-9650TWFl (4.5); 91299; jamngwo.ptc page 21 1223377 _ case number 92114881 _ year month day__ VI. Patent application method for the active area of the channel memory cell, wherein the method of etching the semiconductor substrate is non-equal Anisotropic etching. 2 2. The method for isolating an active area of a memory cell having a partially vertical channel as described in item 15 of the scope of the patent application, wherein the sacrificial layer is a nitrided layer. 2 3. The method for isolating an active area of a memory cell having a partial vertical channel as described in item 15 of the scope of the patent application, wherein the first dielectric layer is an oxide layer. 24. The method for isolating an active area of a memory cell having a partial vertical channel as described in item 15 of the scope of the patent application, wherein the gate dielectric layer is a gate oxide layer. 25. The method for isolating an active area of a memory cell having a partially vertical channel as described in item 15 of the scope of the patent application, wherein the conductive layer is a polycrystalline silicon layer. 2 6. The method for isolating an active area of a memory cell having a partial vertical channel as described in item 15 of the scope of the patent application, wherein the second dielectric layer is an oxide layer. 0548-9650TWFl (4.5) »91299« jamngwo.ptc Page 22