CN113707660A - Dynamic random access memory and forming method thereof - Google Patents

Dynamic random access memory and forming method thereof Download PDF

Info

Publication number
CN113707660A
CN113707660A CN202111028397.1A CN202111028397A CN113707660A CN 113707660 A CN113707660 A CN 113707660A CN 202111028397 A CN202111028397 A CN 202111028397A CN 113707660 A CN113707660 A CN 113707660A
Authority
CN
China
Prior art keywords
word line
layer
forming
line gate
isolation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202111028397.1A
Other languages
Chinese (zh)
Other versions
CN113707660B (en
Inventor
华文宇
刘藩东
丁潇
朱宏斌
华子群
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ICLeague Technology Co Ltd
Original Assignee
ICLeague Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ICLeague Technology Co Ltd filed Critical ICLeague Technology Co Ltd
Priority to CN202111028397.1A priority Critical patent/CN113707660B/en
Publication of CN113707660A publication Critical patent/CN113707660A/en
Application granted granted Critical
Publication of CN113707660B publication Critical patent/CN113707660B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)

Abstract

A dynamic random access memory and a forming method thereof are disclosed, which comprises the following steps: the semiconductor device comprises a substrate, a first substrate, a second substrate and a plurality of active regions, wherein the substrate is provided with a first surface and a second surface and comprises a plurality of active regions, and each active region comprises a channel region and a word line region; a word line gate structure located in the word line region; a first isolation structure located within each of the word line regions; a second isolation structure located within each of the channel regions; the first source-drain doped region is positioned in the first surface of the channel region; a capacitive structure on the first side; the second source-drain doped region is positioned in the second surface of the channel region; a bit line layer on the second side. Through arranging the capacitor structure and the bit line layer on the first surface and the second surface of the substrate, the difficulty of circuit wiring and a manufacturing process can be effectively reduced, the area occupied by a single storage structure can be effectively reduced, and the storage density of the memory can be improved.

Description

Dynamic random access memory and forming method thereof
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a dynamic random access memory and a forming method thereof.
Background
With the rapid development of technology, semiconductor memories are widely used in electronic devices. Dynamic Random Access Memory (DRAM), which is a volatile memory, is the most commonly utilized solution for applications that store large amounts of data.
Generally, a dram is composed of a plurality of memory cells, each of which is mainly composed of a transistor and a capacitor operated by the transistor, and each of the memory cells is electrically connected to each other through a word line and a bit line.
However, the conventional dynamic random access memory still has many problems.
Disclosure of Invention
The invention provides a dynamic random access memory and a forming method thereof, which can effectively reduce the process difficulty and improve the storage density of the memory.
To solve the above problems, the present invention provides a dynamic random access memory, comprising: the substrate is provided with a first surface and a second surface which are opposite, the substrate comprises a plurality of active regions which are mutually separated and parallel to a first direction, the active regions are arranged along a second direction, the first direction is vertical to the second direction, each active region comprises a plurality of word line regions and a plurality of channel regions, and the word line regions and the channel regions in each active region are arranged at intervals along the first direction; a word line gate trench located in each of the word line regions, the word line gate trench extending from the first face to the second face and the word line gate trench penetrating the active region along the second direction; two mutually-separated word line gate structures are positioned in each word line gate groove, and a first isolation opening is formed between the two word line gate structures; a first isolation structure located in each word line region, the first isolation structure also located in a first isolation opening between two word line gate structures; a second isolation structure located within each of the channel regions; the first source-drain doped region is positioned in the first surface of each channel region; the plurality of capacitor structures are positioned on the first surface, and each capacitor structure is electrically connected with one first source drain doped region; the second source-drain doped region is positioned in the second surface of each channel region; and a plurality of bit line layers which are parallel to the first direction and positioned on the second surface, wherein each bit line layer is electrically connected with a plurality of second source-drain doped regions in one active region.
Optionally, the method further includes: and the isolation layer penetrates through the substrate from the first surface to the second surface.
Optionally, the method further includes: and the word line gate structure is positioned on the flat layer.
Optionally, the material of the planarization layer includes an insulating dielectric material; the insulating dielectric material comprises: silicon oxide.
Optionally, the depth of the second source-drain doped region is greater than or equal to the distance between the word line grid structure and the second surface of the substrate.
Optionally, the word line gate structure includes: the word line gate dielectric layer is positioned on the side wall and the bottom surface of the word line gate groove, and the word line gate layer is positioned on the word line gate dielectric layer.
Optionally, the word line gate layer includes: a single layer structure or a composite structure.
Optionally, when the word line gate layer is of a single-layer structure, the material of the word line gate layer includes: metal or polysilicon.
Optionally, when the word line gate layer is of a composite structure, the word line gate layer includes a first gate layer and a second gate layer located on the first gate layer, and the first gate layer and the second gate layer are made of different materials.
Optionally, the material of the first gate layer includes: metal or polysilicon; the material of the second gate layer comprises: polysilicon or metal.
Optionally, a spacing between the first isolation structure and the second face is smaller than or equal to a spacing between the word line gate structure and the second face.
Optionally, the method further includes: and each capacitor structure is electrically connected with one first conductive plug.
Optionally, the method further includes: and the second conductive plugs are used for electrically connecting each bit line layer with the second source-drain doped regions in the corresponding active region respectively.
Optionally, the capacitor structure includes: an upper electrode layer, a lower electrode layer, and a dielectric layer between the upper electrode layer and the lower electrode layer.
Correspondingly, the invention also provides a method for forming the dynamic random access memory, which comprises the following steps: providing a substrate, wherein the substrate is provided with a first face and a second face which are opposite, the substrate comprises a plurality of active regions which are separated from each other and are parallel to a first direction, the plurality of active regions are arranged along a second direction, the first direction is vertical to the second direction, each active region comprises a plurality of word line regions and a plurality of channel regions, and the plurality of word line regions and the plurality of channel regions in each active region are arranged at intervals along the first direction; forming a word line gate trench in each word line region, wherein the word line gate trench extends from the first surface to the second surface and penetrates through the active region along the second direction; forming an initial word line gate structure in each word line gate groove; etching part of the initial word line gate structure from the first face to the second face, forming a plurality of first isolation openings parallel to the second direction in the substrate, wherein the first isolation openings penetrate through the initial word line gate structure from the first face to the second face, and enabling the initial word line gate structure to form two mutually-separated word line gate structures; etching part of the channel region from the first surface to the second surface, and forming a plurality of second isolation openings parallel to the second direction in the substrate; forming a first isolation structure in the first isolation opening; forming a second isolation structure in the second isolation opening; forming a first source drain doped region in the first surface of each channel region; forming a plurality of capacitor structures on the first surface, wherein each capacitor structure is electrically connected with one first source drain doped region; thinning the substrate from the second surface to the first surface; forming a second source-drain doped region in the second surface of each channel region; and forming a plurality of bit line layers parallel to the first direction on the second surface, wherein each bit line layer is electrically connected with a plurality of second source-drain doped regions in one active region.
Optionally, before forming the word line gate trench, the method further includes: and forming an isolation layer between adjacent active regions.
Optionally, the forming method of the isolation layer includes: forming a layer of isolation material between adjacent ones of the active regions and on the first face; and carrying out planarization treatment on the isolation material layer until the first surface is exposed to form the isolation layer.
Optionally, after forming the word line gate trench and before forming the initial word line gate structure, the method further includes: forming a flat layer at the bottom of the word line gate groove; the word line gate structure is located on the flat layer.
Optionally, the method for forming the planarization layer at the bottom of the word line gate trench includes: forming a flat material layer at the bottom of the word line gate groove by adopting a spin coating process, wherein the flat material layer is fluid; and carrying out curing treatment on the flat material layer to form the flat layer.
Optionally, the material of the planarization layer includes an insulating dielectric material; the insulating dielectric material comprises: silicon oxide.
Optionally, the depth of the second source-drain doped region is greater than or equal to the distance between the word line grid structure and the second surface of the substrate.
Optionally, the word line gate structure includes: the word line gate dielectric layer is positioned on the side wall and the bottom surface of the word line gate groove, and the word line gate layer is positioned on the word line gate dielectric layer.
Optionally, the word line gate layer includes: a single layer structure or a composite structure.
Optionally, when the word line gate layer is of a single-layer structure, the material of the word line gate layer includes: metal or polysilicon.
Optionally, when the word line gate layer is of a composite structure, the word line gate layer includes a first gate layer and a second gate layer located on the first gate layer, and the first gate layer and the second gate layer are made of different materials.
Optionally, the material of the first gate layer includes: metal or polysilicon; the material of the second gate layer comprises: polysilicon or metal.
Optionally, a spacing between the first isolation structure and the second face is smaller than or equal to a spacing between the word line gate structure and the second face.
Optionally, before forming the plurality of capacitor structures, the method further includes: and forming a first conductive plug on each first source-drain doped region, wherein each capacitor structure is electrically connected with one first conductive plug.
Optionally, before forming a plurality of bit line layers, the method further includes: and forming a plurality of second conductive plugs, wherein the second conductive plugs are used for electrically connecting each bit line layer with the second source-drain doped regions in the corresponding active region respectively.
Optionally, the capacitor structure includes: an upper electrode layer, a lower electrode layer, and a dielectric layer between the upper electrode layer and the lower electrode layer.
Optionally, the first isolation opening and the second isolation opening are formed at the same time or at different times.
Optionally, the method for forming the first isolation structure and the second isolation structure includes: forming a layer of barrier material within said first spaced-apart openings, within said second spaced-apart openings and on said first face; and carrying out planarization treatment on the isolation material layer until the first surface is exposed, and forming the first isolation structure and the second isolation structure.
Compared with the prior art, the technical scheme of the invention has the following advantages:
in the structure of the technical scheme, the capacitor structure and the bit line layer are respectively arranged on the first surface and the second surface of the substrate, so that the space of the capacitor structure and the bit line layer during arrangement can be increased, the difficulty of circuit wiring and manufacturing process can be further effectively reduced, the area occupied by a single storage structure can be effectively reduced, and the storage density of a memory can be improved.
In addition, from the perspective of the exposure process, since the capacitor structure is a hole structure and the bit line layer is a line structure, the hole structure is more difficult to expose, the line structure is easier to expose, and the exposure requirement is higher when the process is performed from the second surface. Therefore, the capacitor structure with higher exposure difficulty is arranged on the first surface of the substrate, and the bit line layer with lower exposure difficulty is arranged on the second surface, so that the difficulty of an exposure process can be effectively reduced.
From the signal extraction point of view, the upper electrode plate of the capacitor structure and the bit line layer need to be extracted. In the same dynamic random access memory, the upper electrode plates of the capacitor structures are connected with each other, so that a conductive area with a large area is formed, and the capacitor structures are easy to lead out. The linewidth of the bit line layer is small, and the corresponding extraction is difficult. In the process of forming the dynamic random access memory, the leading-out of signals is finished from the second surface of the substrate, so that the capacitor structure with lower lead difficulty is arranged on the first surface, and the bit line layer with higher lead difficulty is arranged on the second surface, thereby effectively reducing the process difficulty in leading-out of signals.
Further, still include: and the word line gate structure is positioned on the flat layer. The flat layer positioned at the bottom of the word line gate groove can effectively improve the controllability of the subsequent process technology and the stability and reliability of the finally formed device structure.
In the forming method of the technical scheme, the capacitor structure and the bit line layer are respectively arranged on the first surface and the second surface of the substrate, so that the space of the capacitor structure and the bit line layer during arrangement can be increased, the difficulty of circuit wiring and manufacturing process can be further effectively reduced, the area occupied by a single storage structure can be effectively reduced, and the storage density of a memory can be improved. In addition, in the process of forming the capacitor structure and the bit line layer, the process can be respectively carried out from the first surface and the second surface of the substrate, and the process efficiency can be effectively improved.
In addition, from the perspective of the exposure process, since the capacitor structure is a hole structure and the bit line layer is a line structure, the hole structure is more difficult to expose, the line structure is easier to expose, and the exposure requirement is higher when the process is performed from the second surface. Therefore, the capacitor structure with higher exposure difficulty is arranged on the first surface of the substrate, and the bit line layer with lower exposure difficulty is arranged on the second surface, so that the difficulty of an exposure process can be effectively reduced.
From the signal extraction point of view, the upper electrode plate of the capacitor structure and the bit line layer need to be extracted. In the same dynamic random access memory, the upper electrode plates of the capacitor structures are connected with each other, so that a conductive area with a large area is formed, and the capacitor structures are easy to lead out. The linewidth of the bit line layer is small, and the corresponding extraction is difficult. In the process of forming the dynamic random access memory, the leading-out of signals is finished from the second surface of the substrate, so that the capacitor structure with lower lead difficulty is arranged on the first surface, and the bit line layer with higher lead difficulty is arranged on the second surface, thereby effectively reducing the process difficulty in leading-out of signals.
In addition, the forming method of the word line grid structure is that an initial word line grid structure is formed first, and then the initial word line grid structure is divided into two mutually-separated word line grid structures by forming the first isolation opening. Because the pattern size of the single word line grid structure is small, the space between the adjacent word line grid structures is also small, and the corresponding exposure process difficulty is large. By forming the initial word line gate structure with larger pattern size and larger adjacent distance, the difficulty of the exposure process can be effectively reduced.
Further, after forming the word line gate trench and before forming the initial word line gate structure, the method further includes: forming a flat layer at the bottom of the word line gate groove; the word line gate structure is located on the flat layer. By forming the flat layer at the bottom of the word line gate groove, the controllability of a subsequent process technology can be effectively improved, and the stability and reliability of a finally formed device structure can be effectively improved.
Drawings
Fig. 1 to 14 are schematic structural diagrams of steps of a method for forming a dynamic random access memory according to an embodiment of the invention.
Detailed Description
As described in the background, problems still exist with existing dynamic random access memories. As will be specifically described below.
In the conventional dynamic random access memory, a bit line and a conductive structure connected to the bit line are provided between the capacitor and the word line and the transistor. Therefore, in order to connect the capacitor to the word line and the transistor, the capacitor structure and the bit line and the conductive structure connected to the bit line need to be avoided from each other, which results in complicated circuit layout and difficult manufacturing process in the memory array region of the memory.
On the basis, the capacitor structure and the bit line layer are respectively arranged on the first surface and the second surface of the substrate, so that the space of the capacitor structure and the bit line layer during arrangement can be enlarged, the difficulty of circuit wiring and manufacturing process can be further effectively reduced, the area occupied by a single storage structure can be effectively reduced, and the storage density of the memory can be improved. In addition, in the process of forming the capacitor structure and the bit line layer, the process can be respectively carried out from the first surface and the second surface of the substrate, and the process efficiency can be effectively improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 1 to 14 are schematic structural diagrams of steps of a method for forming a dynamic random access memory according to an embodiment of the invention.
Referring to fig. 1 to 3, fig. 2 is a schematic cross-sectional view taken along line a-a in fig. 1, fig. 3 is a schematic cross-sectional view taken along line B-B in fig. 1, a substrate 100 is provided, the substrate 100 has a first side 101 and a second side 102 opposite to each other, the substrate 100 includes a plurality of active regions 103 that are separated from each other and parallel to a first direction X, and a plurality of the active regions 103 are arranged along a second direction Y, the first direction X is perpendicular to the second direction Y, each of the active regions 103 includes a plurality of word line regions 104 and a plurality of channel regions 105, and the plurality of the word line regions 104 and the plurality of the channel regions 105 in each of the active regions 103 are arranged at intervals along the first direction X.
In this embodiment, the material of the substrate 100 is silicon; in other embodiments, the substrate may also be germanium, silicon carbide, gallium arsenide, or indium gallium.
In this embodiment, the channel region 105 and the word line region 104 are used to subsequently form a transistor device.
Referring to fig. 4, the views of fig. 4 and fig. 2 are in the same direction, and an isolation layer 106 is formed between adjacent active regions 103.
In this embodiment, the method for forming the isolation layer 106 includes: forming an initial isolation layer (not shown) between adjacent active regions 103 and on the first face 101; the initial isolation layer is planarized until the first side 101 is exposed, so as to form the isolation layer 106.
In this embodiment, the material of the isolation layer 106 is silicon oxide.
Referring to fig. 5, the view directions of fig. 5 and fig. 3 are the same, a word line gate trench 107 is formed in each of the word line regions 104, the word line gate trench 107 extends from the first surface 101 to the second surface 102, and the word line gate trench 107 penetrates through the active region 103 along the second direction Y.
In this embodiment, the word line gate trench 107 provides a space for a word line gate structure to be formed in the word line gate trench 107.
In this embodiment, the method for forming the word line gate trench 107 includes: forming a first patterned layer (not shown) on the first side 101 of the substrate 100, the first patterned layer exposing the word line region 104; and etching from the first surface 101 to the second surface 102 by using the first patterning layer as a mask through an etching process to form the word line gate trench 107.
In this embodiment, the depth of the word line gate trench 107 is smaller than the depth of the isolation layer 106. In other embodiments, the depth of the word line gate trench may also be equal to the depth of the isolation layer.
In this embodiment, during the process of forming the word line gate trench 107, the isolation layer 106 and the word line region 104 need to be etched simultaneously. Since the isolation layer 106 and the word line region 104 are made of different materials, in the etching process, the etching rates of the isolation layer 106 and the word line region 104 are different, which easily causes the bottom of the finally formed word line gate trench 107 to have an uneven problem, thereby easily affecting the controllability of the subsequent process and the stability and reliability of the finally formed device structure.
In the present embodiment, with continued reference to fig. 5, a planarization layer 121 is formed at the bottom of the word line gate trench 107.
In this embodiment, the method for forming the planarization layer 121 at the bottom of the word line gate trench 107 includes: forming a flat material layer (not shown) at the bottom of the word line gate trench 107 by using a spin coating process, wherein the flat material layer is a fluid; and curing the flat material layer to form the flat layer 121.
In this embodiment, the material of the planarization layer 121 includes an insulating dielectric material; the insulating medium material adopts silicon oxide.
By forming the planarization layer 121 on the bottom of the word line gate trench 107, the controllability of the subsequent process can be effectively improved, and the stability and reliability of the finally formed device structure can be effectively improved.
In other embodiments, when the flatness of the bottom of the word line gate trench is high, the planarization layer may not be formed.
Referring to fig. 6 and 7, fig. 7 is a schematic cross-sectional view taken along line C-C in fig. 6, and an initial word line gate structure 108 is formed in each of the word line gate trenches 107.
In this embodiment, the initial word line gate structure 108 includes: an initial wordline gate dielectric layer located on the sidewalls and bottom surface of the wordline gate trench 107, and an initial wordline gate layer (not labeled) located on the initial wordline gate dielectric layer.
With continuing reference to fig. 7, in the present embodiment, the initial word line gate structure 108 does not fill the word line gate trench 107, and after forming the initial word line gate structure 108, the method further includes: a dielectric layer 109 is formed on the first surface 101 of the substrate 100, the word line gate trench 107 is filled with the dielectric layer 109, and the surface of the channel region 105 is exposed by the dielectric layer 109.
Referring to fig. 8, fig. 8 and fig. 7 are the same in view direction, a portion of the initial word line gate structure 108 is etched from the first surface 101 to the second surface 102, a plurality of first isolation openings 110 parallel to the second direction Y are formed in the substrate 100, the first isolation openings 110 penetrate through the initial word line gate structure 108 from the first surface 101 to the second surface 102, and the initial word line gate structure 108 forms two word line gate structures 111 separated from each other; a portion of the channel region 105 is etched in a direction from the first side 101 to the second side 102, forming a plurality of second isolation openings 112 in the substrate 100 parallel to the second direction Y.
In the present embodiment, the first isolation opening 110 and the second isolation opening 112 are formed simultaneously. The first isolation opening 110 and the second isolation opening 112 are formed simultaneously by a single exposure process, which can effectively improve the process efficiency.
In this embodiment, the method for forming the first isolation opening 110 and the second isolation opening 112 includes: forming a second patterned layer (not shown) on the first side 101 of the substrate 100, the second patterned layer exposing a portion of the top surface of the dielectric layer 109 and a portion of the top surface of the channel region 105; and etching from the first surface 101 to the second surface 102 by using the first patterning layer as a mask through an etching process to form the first isolation opening 110 and the second isolation opening 112.
In other embodiments, the first isolation opening and the second isolation opening may also not be formed simultaneously. The first isolation opening and the second isolation opening are formed by adopting a double-exposure process, so that the pattern density in a single-exposure process can be reduced, and the difficulty of the single-exposure process is further reduced.
In this embodiment, the depth of the second isolation opening 112 is greater than or equal to the distance between a subsequently formed second source/drain doped region and the first surface 101 of the substrate 100.
In this embodiment, the word line gate structure 111 is formed by first forming an initial word line gate structure 108, and then dividing the initial word line gate structure 108 into two word line gate structures 111 separated from each other by forming the first isolation opening 110. Since the pattern size of a single word line gate structure 111 is small, the space between adjacent word line gate structures 111 is also small, and the difficulty of the corresponding exposure process is large. By forming the initial word line grid structure 108 with a larger pattern size and a larger adjacent distance, the difficulty of the exposure process can be effectively reduced.
In this embodiment, the word line gate structure 111 includes: a word line gate dielectric layer on the sidewall and bottom surfaces of the word line gate trench 107, and a word line gate layer (not labeled) on the word line gate dielectric layer.
In this embodiment, the word line gate layer has a composite structure, and includes a first gate layer and a second gate layer (not shown) on the first gate layer, where the first gate layer and the second gate layer are made of different materials.
In this embodiment, the first gate layer is made of polysilicon, and the second gate layer is made of metal; in other embodiments, the material of the first gate layer may also be a metal, and the material of the corresponding second gate layer may also be polysilicon.
In other embodiments, the word line gate layer may also adopt a single-layer structure, and when the word line gate layer adopts a single-layer structure, the material of the word line gate layer may adopt polysilicon or metal.
In the present embodiment, the word line gate structure 111 is located on the planarization layer 121.
Referring to fig. 9, a first isolation structure 113 is formed in the first isolation opening 110; a second isolation structure 114 is formed within the second isolation opening 112.
In the present embodiment, the first isolation structure 113 and the second isolation structure 114 are formed simultaneously; in other embodiments, the first isolation structure and the second isolation structure may also not be formed simultaneously.
In this embodiment, the method for forming the first isolation structure 113 and the second isolation structure 114 includes: forming a layer of isolation material (not shown) within the first isolation opening 110, within the second isolation opening 112, and on the first side 101; and planarizing the isolation material layer until the first surface 101 is exposed, thereby forming the first isolation structure 113 and the second isolation structure 114.
In this embodiment, the first isolation structure 113 is used to connect only one side of the word line gate structure 111 with the channel region 105, so that the transistor is a single-side channel structure. The dynamic random access memory with the unilateral channel structure is not easy to generate the leakage current problem during working.
In this embodiment, the material of the first isolation structure 113 and the second isolation structure 114 is silicon oxide.
In the present embodiment, the distance between the first isolation structure 113 and the second surface 102 is smaller than the distance between the word line grid structure 111 and the second surface 102. The two word line gate structures 111 in the word line gate trench 107 can be completely separated by the first isolation structure 113, and therefore, the two word line gate structures 111 are effectively prevented from being shorted.
In other embodiments, the spacing between the first isolation structure 113 and the second side 102 may also be equal to the spacing between the word line gate structure 111 and the second side 102.
Referring to fig. 10, a first source/drain doped region 115 is formed in the first surface 101 of each channel region 105.
In this embodiment, the method for forming the first source/drain doped region 115 in the first surface 101 of each channel region 105 includes: by adopting an ion implantation process, a first ion implantation treatment is performed from the first surface 101 to the second surface 102, and a first source-drain doped region 115 is formed in the first surface 101 of each channel region 105.
In the embodiment, the first ions are N-type ions; in other embodiments, the first ions may also be P-type ions.
Referring to fig. 11, a plurality of capacitor structures 116 are formed on the first surface 101, and each capacitor structure 116 is electrically connected to one first source-drain doped region 115.
In this embodiment, before forming the plurality of capacitor structures 116, the method further includes: forming a first conductive plug 117 on each first source-drain doped region 115, wherein each capacitor structure 116 is electrically connected to one first conductive plug 117; in other embodiments, the first conductive plug may not be formed.
In this embodiment, the capacitor structure 116 includes: an upper electrode layer, a lower electrode layer, and a dielectric layer (not labeled) between the upper electrode layer and the lower electrode layer.
Referring to fig. 12, the substrate 100 is thinned from the second side 102 toward the first side 101.
The process of thinning the substrate 100 from the second surface 102 to the first surface 101 includes a physical mechanical polishing process, a chemical mechanical polishing process, or a wet etching process. In this embodiment, the process of thinning the substrate 100 from the second surface 102 to the first surface 101 is a chemical mechanical polishing process.
The thinning process is performed until the surface of the isolation layer 106 is exposed.
In the present embodiment, the depth of the first isolation structure 113 and the second isolation structure 114 is equal to the depth of the isolation layer 106. Thus, after the thinning process, the second side of the substrate 100 also exposes the surfaces of the first isolation structure 113 and the second isolation structure 114.
In other embodiments, the first and second isolation structures may also have a depth less than the depth of the isolation layer, and the second side of the substrate does not expose the surfaces of the first and second isolation structures after the thinning process.
Referring to fig. 13, a second source/drain doped region 118 is formed in the second side 102 of each channel region 105.
In this embodiment, the method for forming the second source/drain doped region 118 in the second surface 102 of each channel region 105 includes: and performing second ion implantation treatment from the second surface 102 to the first surface 101 by using an ion implantation process, and forming a second source-drain doped region 118 in the second surface 102 of each channel region 105.
The second ions are of the same electrical type as the first ions.
In this embodiment, the second ions are N-type ions; in other embodiments, when the first ions are P-type ions, the second ions may also be P-type ions.
In this embodiment, the depth of the second source-drain doped region 118 is greater than the distance between the word line gate structure 111 and the second surface 102 of the substrate 101; in other embodiments, the depth of the second source/drain doped region 118 may also be equal to the distance between the word line gate structure and the second surface of the substrate.
From there, transistors are formed within the substrate 100.
Referring to fig. 14, a plurality of bit line layers 119 parallel to the first direction X are formed on the second surface 102, and each of the bit line layers 119 is electrically connected to a plurality of second source/drain doped regions 118 in one of the active regions 103.
In this embodiment, the capacitor structure 116 and the bit line layer 119 are respectively arranged on the first surface 101 and the second surface 102 of the substrate 100, so that the space of the capacitor structure 116 and the bit line layer 119 during arrangement can be increased, the difficulty of circuit wiring and a manufacturing process can be further effectively reduced, the area occupied by a single memory structure can be further effectively reduced, and the memory density of the memory can be improved. In addition, in the process of forming the capacitor structure 116 and the bit line layer 119, the process can be performed from the first side 101 and the second side 102 of the substrate 100, respectively, which can effectively improve the process efficiency.
In addition, from the perspective of the exposure process, since the capacitor structure 116 is a hole structure and the bit line layer 119 is a line structure, the hole structure is more difficult to expose, the line structure is easier to expose, and the exposure requirement is higher when the process is performed from the second surface 102. Therefore, the capacitor structures 116 with higher exposure difficulty are arranged on the first side 101 of the substrate 100, and the bit line layer 119 with lower exposure difficulty is arranged on the second side 102 of the substrate 100, so that the difficulty of the exposure process can be effectively reduced.
From a signal extraction point of view, the upper electrode plate of the capacitor structure 116 and the bit line layer 119 need to be extracted. Because the upper electrode plates of the capacitor structures 116 are connected to each other in the same dram, a conductive region with a large area is formed, and thus, the capacitor structures 116 can be easily led out. The linewidth of the bit line layer 119 is small and the corresponding extraction is difficult. Since the signal is led out from the second surface 102 of the substrate 100 in the process of forming the dynamic random access memory, the capacitor structure 116 with less lead difficulty is arranged on the first surface 101 of the substrate 100, and the bit line layer 119 with greater lead difficulty is arranged on the second surface 102 of the substrate 100, which can effectively reduce the process difficulty in signal leading out.
In this embodiment, one capacitor structure 116 and one transistor are arranged in a two-dimensional matrix as a unit. The basic operation mechanism is divided into Read (Read) and Write (Write), in which the bit line layer 119 is first charged to half of the operation voltage and then the transistor is turned on to cause charge sharing between the bit line layer 119 and the capacitor structure 116. If the internally stored value is 1, the voltage of the bit line layer 119 is raised by charge sharing to more than half of the operating voltage; on the other hand, if the internally stored value is 0, the voltage of the bit line layer 119 is pulled down to be lower than half of the operating voltage, and after the voltage of the bit line layer 119 is obtained, the internally stored value is determined to be 0 or 1 through the amplifier. The transistor is turned on when writing, and if 1 is to be written, the voltage of the bit line layer 119 is raised to an operating voltage so that the operating voltage is stored on the capacitor structure 116; if a 0 is to be written, then lowering the bit line layer 119 to 0 volts leaves no charge inside the capacitive structure 116.
In the embodiment, before forming several bit line layers 119, the method further includes: forming a plurality of second conductive plugs 120, wherein each of the bit line layers 119 is electrically connected to a plurality of second source/drain doped regions 118 in a corresponding one of the active regions 103 by the plurality of second conductive plugs 120; in other embodiments, the second conductive plug may not be formed.
The bit line layer 119 material includes metals including tungsten, aluminum, copper, and the like. In this embodiment, the bit line layer 119 is made of tungsten.
In the present embodiment, the method of forming the bit line layer 119 includes: forming a bit line material layer (not shown) on the second side 102; forming a third patterned layer (not shown) on the bit line material layer, the third patterned layer exposing a portion of the bit line material layer; and etching the bit line material layer from the second surface 102 to the first surface 101 by using the third patterned layer as a mask to form a plurality of bit line layers 119.
The process for forming the bit line material layer comprises the following steps: a metal plating process, a selective metal growth process or a deposition process; the deposition process comprises a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process. In this embodiment, the bit line material layer is formed by an atomic layer deposition process.
Accordingly, the embodiment of the present invention further provides a dynamic random access memory, please continue to refer to fig. 14, including: a substrate 100, the substrate 100 having a first side 101 and a second side 102 opposite to each other, the substrate 100 including a plurality of active regions 103 separated from each other and parallel to a first direction X, and a plurality of active regions 103 arranged along a second direction Y, the first direction X being perpendicular to the second direction Y, each of the active regions 103 including a plurality of word line regions 104 and a plurality of channel regions 105, and the plurality of word line regions 104 and the plurality of channel regions 105 in each of the active regions 103 being arranged at intervals along the first direction X; a word line gate trench 107 located in each of the word line regions 104, the word line gate trench 107 extending from the first face 101 to the second face 102, and the word line gate trench 107 penetrating the active region 103 along the second direction Y; two mutually-separated word line gate structures 111 are positioned in each word line gate groove 107, and a first isolation opening 110 is arranged between the two word line gate structures 111; a first isolation structure 113 located in each of the word line regions 104, wherein the first isolation structure 113 is further located in the first isolation opening 110 between the two word line gate structures 111; a second isolation structure 114 located within each of the channel regions 105; a first source-drain doped region 115 located in the first side 101 of each channel region 105; a plurality of capacitor structures 116 located on the first surface 101, wherein each capacitor structure 116 is electrically connected to one of the first source drain doped regions 115; a second source-drain doped region 118 located in the second side 102 of each of the channel regions 105; a plurality of bit line layers 119 located on the second side 102 and parallel to the first direction X, wherein each of the bit line layers 119 is electrically connected to a plurality of second source/drain doped regions 118 in one of the active regions 103.
In this embodiment, the capacitor structure 116 and the bit line layer 119 are respectively arranged on the first surface 101 and the second surface 102 of the substrate 100, so that the space of the capacitor structure 116 and the bit line layer 119 during arrangement can be increased, the difficulty of circuit wiring and a manufacturing process can be further effectively reduced, the area occupied by a single storage structure can be further effectively reduced, and the storage density of the memory can be further improved.
In addition, from the perspective of the exposure process, since the capacitor structure 116 is a hole structure and the bit line layer 119 is a line structure, the hole structure is more difficult to expose, the line structure is easier to expose, and the exposure requirement is higher when the process is performed from the second surface 102. Therefore, the capacitor structures 116 with higher exposure difficulty are arranged on the first side 101 of the substrate 100, and the bit line layer 119 with lower exposure difficulty is arranged on the second side 102 of the substrate 100, so that the difficulty of the exposure process can be effectively reduced.
From a signal extraction point of view, the upper electrode plate of the capacitor structure 116 and the bit line layer 119 need to be extracted. Because the upper electrode plates of the capacitor structures 116 are connected to each other in the same dram, a conductive region with a large area is formed, and thus, the capacitor structures 116 can be easily led out. The linewidth of the bit line layer 119 is small and the corresponding extraction is difficult. Since the signal is led out from the second surface 102 of the substrate 100 in the process of forming the dynamic random access memory, the capacitor structure 116 with less lead difficulty is arranged on the first surface 101 of the substrate 100, and the bit line layer 119 with greater lead difficulty is arranged on the second surface 102 of the substrate 100, which can effectively reduce the process difficulty in signal leading out.
In this embodiment, the method further includes: an isolation layer 106 located between adjacent active regions 103, wherein the isolation layer 106 penetrates the substrate 100 in a direction from the first side 101 to the second side 102.
In this embodiment, the method further includes: a flat layer 121 located at the bottom of the word line gate trench 107, and the word line gate structure 111 is located on the flat layer 121.
The flat layer 121 located at the bottom of the word line gate trench 107 can effectively improve the controllability of the subsequent process, and the stability and reliability of the finally formed device structure.
In other embodiments, the planarization layer may not be formed.
In this embodiment, the material of the planarization layer 121 includes an insulating dielectric material; the insulating medium material adopts silicon oxide.
In this embodiment, the depth of the second source-drain doped region 118 is greater than the distance between the word line gate structure 111 and the second surface 102 of the substrate 100; in other embodiments, the depth of the second source-drain doped region may also be equal to the distance between the word line gate structure and the second surface of the substrate.
In this embodiment, the word line gate structure 111 includes: a word line gate dielectric layer on the side wall and bottom surface of the word line gate trench, and a word line gate layer (not labeled) on the word line gate dielectric layer.
In this embodiment, the word line gate layer has a composite structure, and includes a first gate layer and a second gate layer (not shown) on the first gate layer, where the first gate layer and the second gate layer are made of different materials.
In this embodiment, the first gate layer is made of polysilicon, and the second gate layer is made of metal; in other embodiments, the material of the first gate layer may also be a metal, and the material of the corresponding second gate layer may also be polysilicon.
In other embodiments, the word line gate layer may also adopt a single-layer structure, and when the word line gate layer adopts a single-layer structure, the material of the word line gate layer may adopt polysilicon or metal.
In the present embodiment, the distance between the first isolation structure 113 and the second surface 102 is smaller than the distance between the word line grid structure 111 and the second surface 102. The two word line gate structures 111 in the word line gate trench 107 can be completely separated by the first isolation structure 113, and therefore, the two word line gate structures 111 are effectively prevented from being shorted.
In other embodiments, a spacing between the first isolation structure and the second side may also be equal to a spacing between the word line gate structure and the second side.
In this embodiment, the method further includes: a first conductive plug 117 located on each first source-drain doped region 115, wherein each capacitor structure 116 is electrically connected to one first conductive plug 117; in other embodiments, the first conductive plug may not be formed.
In this embodiment, the method further includes: a plurality of second conductive plugs 120, wherein each of the bit line layers 119 is electrically connected to a plurality of second source/drain doped regions 118 in a corresponding one of the active regions 103 by the plurality of second conductive plugs 120; in other embodiments, the second conductive plug may not be formed.
In this embodiment, the capacitor structure 116 includes: an upper electrode layer, a lower electrode layer, and a dielectric layer (not labeled) between the upper electrode layer and the lower electrode layer.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (32)

1. A dynamic random access memory, comprising:
the substrate is provided with a first surface and a second surface which are opposite, the substrate comprises a plurality of active regions which are mutually separated and parallel to a first direction, the active regions are arranged along a second direction, the first direction is vertical to the second direction, each active region comprises a plurality of word line regions and a plurality of channel regions, and the word line regions and the channel regions in each active region are arranged at intervals along the first direction;
a word line gate trench located in each of the word line regions, the word line gate trench extending from the first face to the second face and the word line gate trench penetrating the active region along the second direction;
the two word line gate structures are positioned in each word line gate groove and are separated from each other, and a first isolation opening is formed between the two word line gate structures;
a first isolation structure located in each word line region, the first isolation structure also located in a first isolation opening between two word line gate structures;
a second isolation structure located within each of the channel regions;
the first source-drain doped region is positioned in the first surface of each channel region;
the plurality of capacitor structures are positioned on the first surface, and each capacitor structure is electrically connected with one first source drain doped region;
the second source-drain doped region is positioned in the second surface of each channel region;
and a plurality of bit line layers which are parallel to the first direction and positioned on the second surface, wherein each bit line layer is electrically connected with a plurality of second source-drain doped regions in one active region.
2. The dynamic random access memory of claim 1, further comprising: and the isolation layer penetrates through the substrate from the first surface to the second surface.
3. The dynamic random access memory of claim 1, further comprising: and the word line gate structure is positioned on the flat layer.
4. The dynamic random access memory of claim 3 wherein the material of the planar layer comprises an insulating dielectric material; the insulating dielectric material comprises: silicon oxide.
5. The dynamic random access memory of claim 1, wherein a depth of the second source drain doped region is greater than or equal to a spacing between the word line gate structure and the second side of the substrate.
6. The dynamic random access memory of claim 1, wherein the word line gate structure comprises: the word line gate dielectric layer is positioned on the side wall and the bottom surface of the word line gate groove, and the word line gate layer is positioned on the word line gate dielectric layer.
7. The dynamic random access memory of claim 6, wherein the word line gate layer comprises: a single layer structure or a composite structure.
8. The dynamic random access memory according to claim 7, wherein when the word line gate layer has a single-layer structure, the material of the word line gate layer includes: metal or polysilicon.
9. The dynamic random access memory according to claim 7, wherein when the wordline gate layer is a composite structure, the wordline gate layer comprises a first gate layer and a second gate layer located on the first gate layer, and the first gate layer and the second gate layer are made of different materials.
10. The dynamic random access memory of claim 9, wherein the material of the first gate layer comprises: metal or polysilicon; the material of the second gate layer comprises: polysilicon or metal.
11. The dynamic random access memory of claim 1, wherein a pitch between the first isolation structure and the second face is less than or equal to a pitch between the word line gate structure and the second face.
12. The dynamic random access memory of claim 1, further comprising: and each capacitor structure is electrically connected with one first conductive plug.
13. The dynamic random access memory of claim 1, further comprising: and the second conductive plugs are used for electrically connecting each bit line layer with the second source-drain doped regions in the corresponding active region respectively.
14. The dynamic random access memory of claim 1, wherein the capacitive structure comprises: an upper electrode layer, a lower electrode layer, and a dielectric layer between the upper electrode layer and the lower electrode layer.
15. A method for forming a dynamic random access memory, comprising:
providing a substrate, wherein the substrate is provided with a first face and a second face which are opposite, the substrate comprises a plurality of active regions which are separated from each other and are parallel to a first direction, the plurality of active regions are arranged along a second direction, the first direction is vertical to the second direction, each active region comprises a plurality of word line regions and a plurality of channel regions, and the plurality of word line regions and the plurality of channel regions in each active region are arranged at intervals along the first direction;
forming a word line gate trench in each word line region, wherein the word line gate trench extends from the first surface to the second surface and penetrates through the active region along the second direction;
forming an initial word line gate structure in each word line gate groove;
etching part of the initial word line gate structure from the first face to the second face, forming a plurality of first isolation openings parallel to the second direction in the substrate, wherein the first isolation openings penetrate through the initial word line gate structure from the first face to the second face, and enabling the initial word line gate structure to form two mutually-separated word line gate structures;
etching part of the channel region from the first surface to the second surface, and forming a plurality of second isolation openings parallel to the second direction in the substrate;
forming a first isolation structure in the first isolation opening;
forming a second isolation structure in the second isolation opening;
forming a first source drain doped region in the first surface of each channel region;
forming a plurality of capacitor structures on the first surface, wherein each capacitor structure is electrically connected with one first source drain doped region;
thinning the substrate from the second surface to the first surface;
forming a second source-drain doped region in the second surface of each channel region;
and forming a plurality of bit line layers parallel to the first direction on the second surface, wherein each bit line layer is electrically connected with a plurality of second source-drain doped regions in one active region.
16. The method of forming a dynamic random access memory of claim 15, further comprising, prior to forming the word line gate trench: and forming an isolation layer between adjacent active regions.
17. The method of forming a dynamic random access memory according to claim 16, wherein the spacer layer comprises: forming a layer of isolation material between adjacent ones of the active regions and on the first face; and carrying out planarization treatment on the isolation material layer until the first surface is exposed to form the isolation layer.
18. The method of forming a dynamic random access memory of claim 15, further comprising, after forming the word line gate trench and before forming the initial word line gate structure: forming a flat layer at the bottom of the word line gate groove; the word line gate structure is located on the flat layer.
19. The method of claim 18, wherein the step of forming a planarization layer on the bottom of the word line gate trench comprises: forming a flat material layer at the bottom of the word line gate groove by adopting a spin coating process, wherein the flat material layer is fluid; and carrying out curing treatment on the flat material layer to form the flat layer.
20. The method of claim 18, wherein the material of the planarization layer comprises an insulating dielectric material; the insulating dielectric material comprises: silicon oxide.
21. The method of claim 15, wherein a depth of the second source-drain doped region is greater than or equal to a distance between the word line gate structure and the second side of the substrate.
22. The method of claim 15, wherein the word line gate structure comprises: the word line gate dielectric layer is positioned on the side wall and the bottom surface of the word line gate groove, and the word line gate layer is positioned on the word line gate dielectric layer.
23. The method of forming a dynamic random access memory of claim 22 wherein the word line gate layer comprises: a single layer structure or a composite structure.
24. The method of claim 23, wherein when the word line gate layer is a single layer structure, the material of the word line gate layer comprises: metal or polysilicon.
25. The method of claim 23, wherein the wordline gate layer comprises a first gate layer and a second gate layer over the first gate layer when the wordline gate layer is a composite structure, and wherein the first gate layer and the second gate layer are made of different materials.
26. The method of claim 24, wherein the material of the first gate layer comprises: metal or polysilicon; the material of the second gate layer comprises: polysilicon or metal.
27. The method of claim 15, wherein a pitch between the first isolation structure and the second side is less than or equal to a pitch between the word line gate structure and the second side.
28. The method of forming a dynamic random access memory of claim 15, further comprising, prior to forming the plurality of capacitor structures: and forming a first conductive plug on each first source-drain doped region, wherein each capacitor structure is electrically connected with one first conductive plug.
29. The method of forming a dynamic random access memory of claim 15 further comprising, prior to forming a plurality of said bit line layers: and forming a plurality of second conductive plugs, wherein the second conductive plugs are used for electrically connecting each bit line layer with the second source-drain doped regions in the corresponding active region respectively.
30. The method of claim 15, wherein the capacitor structure comprises: an upper electrode layer, a lower electrode layer, and a dielectric layer between the upper electrode layer and the lower electrode layer.
31. The method of claim 15, wherein the first isolation opening and the second isolation opening are formed at the same time or at different times.
32. The method of forming a dynamic random access memory of claim 15, wherein the method of forming the first isolation structure and the second isolation structure comprises: forming a layer of barrier material within said first spaced-apart openings, within said second spaced-apart openings and on said first face; and carrying out planarization treatment on the isolation material layer until the first surface is exposed, and forming the first isolation structure and the second isolation structure.
CN202111028397.1A 2021-09-02 2021-09-02 Dynamic random access memory and forming method thereof Active CN113707660B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202111028397.1A CN113707660B (en) 2021-09-02 2021-09-02 Dynamic random access memory and forming method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202111028397.1A CN113707660B (en) 2021-09-02 2021-09-02 Dynamic random access memory and forming method thereof

Publications (2)

Publication Number Publication Date
CN113707660A true CN113707660A (en) 2021-11-26
CN113707660B CN113707660B (en) 2024-04-05

Family

ID=78657741

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202111028397.1A Active CN113707660B (en) 2021-09-02 2021-09-02 Dynamic random access memory and forming method thereof

Country Status (1)

Country Link
CN (1) CN113707660B (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114121961A (en) * 2021-11-29 2022-03-01 芯盟科技有限公司 Dynamic random access memory and forming method thereof
CN114220765A (en) * 2022-02-22 2022-03-22 芯盟科技有限公司 Memory and manufacturing method thereof
WO2023130655A1 (en) * 2022-01-05 2023-07-13 芯盟科技有限公司 Semiconductor structure, and method for forming semiconductor structure

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6184080B1 (en) * 1998-09-04 2001-02-06 Texas Instruments Incorporated Method of the simultaneous formation for the storage node contacts, bit line contacts, and the contacts for periphery circuits
KR20010091733A (en) * 2000-03-17 2001-10-23 후 훙-치우 Structure of dram with vertical transistor and method of fabricating the same
US20040029342A1 (en) * 2002-08-06 2004-02-12 Intelligent Sources Development Corp. Self-aligned trench-type dram strucutre and its manufacturing methods
US20190103407A1 (en) * 2017-09-29 2019-04-04 Samsung Electronics Co., Ltd. Semiconductor memory devices
CN110265398A (en) * 2019-06-28 2019-09-20 芯盟科技有限公司 Memory and forming method thereof
CN112071841A (en) * 2020-09-17 2020-12-11 芯盟科技有限公司 Semiconductor structure and forming method thereof
CN112864158A (en) * 2021-04-07 2021-05-28 芯盟科技有限公司 Dynamic random access memory and forming method thereof
CN112909001A (en) * 2021-04-07 2021-06-04 芯盟科技有限公司 Dynamic random access memory and forming method thereof
CN112951828A (en) * 2021-04-07 2021-06-11 芯盟科技有限公司 Semiconductor structure and forming method thereof
CN113192956A (en) * 2021-06-29 2021-07-30 芯盟科技有限公司 Dynamic random access memory and forming method thereof

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6184080B1 (en) * 1998-09-04 2001-02-06 Texas Instruments Incorporated Method of the simultaneous formation for the storage node contacts, bit line contacts, and the contacts for periphery circuits
KR20010091733A (en) * 2000-03-17 2001-10-23 후 훙-치우 Structure of dram with vertical transistor and method of fabricating the same
US20040029342A1 (en) * 2002-08-06 2004-02-12 Intelligent Sources Development Corp. Self-aligned trench-type dram strucutre and its manufacturing methods
US20190103407A1 (en) * 2017-09-29 2019-04-04 Samsung Electronics Co., Ltd. Semiconductor memory devices
CN110265398A (en) * 2019-06-28 2019-09-20 芯盟科技有限公司 Memory and forming method thereof
CN112071841A (en) * 2020-09-17 2020-12-11 芯盟科技有限公司 Semiconductor structure and forming method thereof
CN112864158A (en) * 2021-04-07 2021-05-28 芯盟科技有限公司 Dynamic random access memory and forming method thereof
CN112909001A (en) * 2021-04-07 2021-06-04 芯盟科技有限公司 Dynamic random access memory and forming method thereof
CN112951828A (en) * 2021-04-07 2021-06-11 芯盟科技有限公司 Semiconductor structure and forming method thereof
CN113192956A (en) * 2021-06-29 2021-07-30 芯盟科技有限公司 Dynamic random access memory and forming method thereof

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114121961A (en) * 2021-11-29 2022-03-01 芯盟科技有限公司 Dynamic random access memory and forming method thereof
CN114121961B (en) * 2021-11-29 2024-04-05 芯盟科技有限公司 Dynamic random access memory and forming method thereof
WO2023130655A1 (en) * 2022-01-05 2023-07-13 芯盟科技有限公司 Semiconductor structure, and method for forming semiconductor structure
CN114220765A (en) * 2022-02-22 2022-03-22 芯盟科技有限公司 Memory and manufacturing method thereof

Also Published As

Publication number Publication date
CN113707660B (en) 2024-04-05

Similar Documents

Publication Publication Date Title
CN112864158B (en) Dynamic random access memory and forming method thereof
KR960005251B1 (en) Manufacture of memory device
CN113707660B (en) Dynamic random access memory and forming method thereof
CN112909001B (en) Dynamic random access memory and forming method thereof
CN112071841A (en) Semiconductor structure and forming method thereof
US9048293B2 (en) Semiconductor device and method for manufacturing the same
CN114121961B (en) Dynamic random access memory and forming method thereof
CN113192956B (en) Dynamic random access memory and forming method thereof
CN112951769B (en) Semiconductor memory and forming method thereof
CN114121821A (en) Method for forming dynamic random access memory
CN115701210A (en) Semiconductor structure and manufacturing method thereof
CN113437068B (en) Dynamic random access memory and forming method thereof
CN110137138B (en) Memory structure, forming method thereof and circuit of memory structure
CN115295496A (en) Semiconductor device, manufacturing method thereof, memory and storage system
CN115346986B (en) Dynamic random access memory and forming method thereof
CN115377108B (en) Dynamic random access memory and forming method thereof
CN113540094A (en) Semiconductor structure and forming method thereof
CN210272359U (en) Semiconductor memory device with a memory cell having a plurality of memory cells
US20230005919A1 (en) Semiconductor structure and method for forming semiconductor structure
CN113437069B (en) Dynamic random access memory and forming method thereof
CN116137781A (en) Memory and forming method thereof
CN111816671A (en) Magnetic random access memory and forming method thereof
CN115312519B (en) Dynamic random access memory and forming method thereof
WO2024060676A9 (en) Semiconductor structure, and manufacturing method for semiconductor structure
WO2023245716A1 (en) Semiconductor structure and forming method therefor

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant