CN116137781A - Memory and forming method thereof - Google Patents

Abstract

A memory and a forming method thereof, wherein the forming method comprises: providing a substrate, wherein the substrate is provided with a first surface and a second surface which are opposite, and the substrate comprises a plurality of active areas; forming a first isolation layer on the first surface; thinning the substrate from the second surface to the first surface; etching back the first isolation layer from the second surface to the first surface; forming a protective layer on the exposed side wall surface of the active region; forming a second isolation layer on the second surface, wherein the second isolation layer covers the side wall of the protection layer; etching back the active region from the second face to the first face to form a bit line opening in the second isolation layer; forming a bit line layer in the bit line opening; removing the second isolation layer; a third spacer is formed on the second side. The side wall of the bit line layer is protected through the protection layer, so that transverse etching caused by the bit line layer is effectively reduced, and the problem that the bit line layer collapses is prevented. In addition, the protective layer can also effectively prevent the side wall of the bit line layer from being oxidized, so that the performance of the device structure is improved.

Description

Memory and forming method thereof

Technical Field

The present disclosure relates to semiconductor manufacturing technology, and more particularly, to a memory and a method for forming the same.

Background

With rapid development of technology nowadays, semiconductor memories are widely used in electronic devices. The vertical channel memory architecture (VCAT) has a higher memory density than the conventional architecture (BCAT), and a capacitive contact of the vertical channel memory architecture (VCAT) is connected to an active region of the vertical channel device, and a word line is formed within and surface-level with the active region.

However, vertical channel memories still have problems in the formation process.

Disclosure of Invention

The invention solves the technical problem of providing a memory and a forming method thereof, which increase the protection of a bit line layer and further improve the performance of a device.

In order to solve the above-mentioned problems, the present invention provides a method for forming a memory, comprising: providing a substrate, wherein the substrate is provided with a first surface and a second surface which are opposite, the substrate comprises a plurality of active areas which are mutually separated and parallel to a first direction, and the plurality of active areas are arranged along a second direction, and the first direction is perpendicular to the second direction; forming a first isolation layer on the first surface, wherein the first isolation layer is positioned between adjacent active areas; thinning the substrate from the second surface to the first surface until the first isolation layer is exposed; etching back the first isolation layer from the second surface to the first surface to expose part of the side wall surface of the active region; forming a protective layer on the exposed side wall surface of the active region; forming a second isolation layer on the second face after forming the protection layer, wherein the second isolation layer covers the side wall of the protection layer; etching back the active region from the second face to the first face after forming the second isolation layer, and forming a bit line opening in the second isolation layer; forming a bit line layer within the bit line opening; removing the second isolation layer after forming the bit line layer; after the second isolation layer is removed, a third isolation layer is formed on the second face, the third isolation layer covers the bit line layer and the protection layer, and a cavity is formed in the third isolation layer.

Optionally, after exposing a portion of the sidewall surface of the active region and before forming the protective layer, the method further includes: and etching the exposed active region to reduce the width dimension of the exposed active region.

Optionally, the forming method of the protective layer and the second isolation layer includes: forming a protective material layer on the exposed side wall and top surface of the active region and the surface of the first isolation layer; forming a spacer material layer on the second face, the spacer material layer covering the protective material layer; and flattening the isolation material layer and the protection material layer from the second surface to the first surface until the surface of the active region is exposed, so as to form the protection layer and the second isolation layer.

Optionally, the material of the protective layer includes: silicon nitride, titanium nitride or aluminum oxide.

Optionally, the bit line layer includes: a polysilicon layer, a metal silicide layer on the polysilicon layer, and a metal layer on the metal silicide layer.

Optionally, each of the active regions includes a plurality of word line regions and a plurality of channel regions, and the plurality of word line regions and the plurality of channel regions in each of the active regions are arranged at intervals along the first direction; before thinning the substrate, the method further comprises: forming a word line gate trench within each of the word line regions, the word line gate trench extending from the first face to the second face, and the word line gate trench extending through the active region in the second direction; two electrically isolated word line gate structures are formed within each of the word line gate trenches.

Optionally, after forming the word line gate structure, the method further includes: etching part of the channel region from the first surface to the second surface, and forming a plurality of isolation openings parallel to the second direction in the substrate; forming an isolation structure in the isolation opening; forming a first source-drain doped region in a first surface of each channel region; forming a plurality of capacitor structures on the first surface, wherein each capacitor structure is electrically connected with one first source-drain doped region; and forming a second source-drain doped region in the second surface of each channel region.

Optionally, each bit line layer is electrically connected with a plurality of second source-drain doped regions in one active region.

Correspondingly, the technical scheme of the invention also provides a memory, which comprises the following components: a substrate having opposite first and second sides, the substrate comprising a plurality of active regions separated from each other and parallel to a first direction, the plurality of active regions being arranged along a second direction, the first direction being perpendicular to the second direction; a first isolation layer located between adjacent ones of the active regions; a plurality of bit line layers on the second side, each bit line layer electrically connected to one of the active regions; a protective layer located on the sidewall of the bit line layer; and a third isolation layer on the second surface, wherein the third isolation layer covers the bit line layer and the protection layer, and a cavity is formed in the third isolation layer.

Optionally, the width dimension of the bit line layer is smaller than the width dimension of the active region.

Optionally, the material of the protective layer includes: silicon nitride, titanium nitride or aluminum oxide.

Optionally, the bit line layer includes: a polysilicon layer, a metal silicide layer on the polysilicon layer, and a metal layer on the metal silicide layer.

Optionally, each of the active regions includes a plurality of word line regions and a plurality of channel regions, and the plurality of word line regions and the plurality of channel regions in each of the active regions are spaced apart along the first direction.

Optionally, the method further comprises: a word line gate trench within each of the word line regions, the word line gate trench extending from the first face to the second face, and the word line gate trench extending through the active region in the second direction; two electrically isolated word line gate structures located within each of the word line gate trenches.

Optionally, the method further comprises: an isolation opening in each of the channel regions; an isolation structure located within the isolation opening; a first source-drain doped region located in a first face of each channel region; a plurality of capacitor structures located on the first surface, each capacitor structure being electrically connected to one of the first source-drain doped regions; and a second source-drain doped region located in a second face of each channel region.

Optionally, each bit line layer is electrically connected with a plurality of second source-drain doped regions in one active region.

Compared with the prior art, the technical scheme of the invention has the following advantages:

according to the method for forming the memory, the protective layer is formed on the exposed side wall surface of the active region, and the side wall of the bit line layer is protected through the protective layer in the process of removing the second isolation layer, so that the transverse etching on the bit line layer is effectively reduced, and the problem of collapse of the bit line layer is prevented. In addition, the protective layer can also effectively prevent the side wall of the bit line layer from being oxidized, so that the performance of the device structure is improved.

Further, after exposing a portion of the sidewall surface of the active region and before forming the protective layer, further comprising: and etching the exposed active region to reduce the width dimension of the exposed active region. The width dimension of the exposed active region is reduced, so that the width dimension of the bit line layer is reduced, the space dimension between adjacent bit line layers is increased, and the parasitic capacitance between the adjacent bit line layers is reduced.

In the memory of the technical scheme of the invention, the side wall of the bit line layer is protected by the protective layer, so that the transverse etching on the bit line layer is effectively reduced, and the problem of collapse of the bit line layer is prevented. In addition, the protective layer can also effectively prevent the side wall of the bit line layer from being oxidized, so that the performance of the device structure is improved.

Further, a width dimension of the bit line layer is smaller than a width dimension of the active region. The width dimension of the exposed active region is reduced, so that the width dimension of the bit line layer is reduced, the space dimension between adjacent bit line layers is increased, and the parasitic capacitance between the adjacent bit line layers is reduced.

Drawings

FIGS. 1 to 2 are schematic views showing steps of a method for forming a memory;

fig. 3 to 23 are schematic structural diagrams illustrating steps of a method for forming a memory according to an embodiment of the invention.

Detailed Description

As described in the background, there are still many problems with the formation of vertical channel memories. The following will make a detailed description with reference to the accompanying drawings.

Referring to fig. 1, the method includes: providing a substrate 200, said substrate 200 having opposite first and second sides 201, 202, said substrate 200 comprising a plurality of active regions 203 separated from each other; forming a first isolation layer 204 on the first surface 201, wherein the first isolation layer 204 is located between adjacent active regions 203; thinning the substrate 200 from the second surface 202 to the first surface 201 until the first isolation layer 204 is exposed; etching back the active region 203 from the second surface 202 toward the first surface 201, forming a bit line opening (not shown) in the first isolation layer 204; forming a bit line layer 205 within the bit line openings; after the bit line layer 205 is formed, the first isolation layer 204 is etched back from the second face 202 toward the first face 201, exposing sidewall surfaces of the bit line layer 205.

Referring to fig. 2, after etching back the first isolation layer 204, a second isolation layer 206 is formed on the second surface 202, the second isolation layer 206 covers the bit line layer 205, and the second isolation layer 206 has a cavity 207 therein.

In this embodiment, by reforming the second isolation layer 206, and having the cavity 207 in the second isolation layer 206, the dielectric constant between adjacent bit line layers 205 is reduced by the cavity 207, thereby reducing the parasitic capacitance between adjacent bit line layers 205.

However, during the process of removing the etching back the first isolation layer 204, the bit line layer 205 is easily etched laterally, which in turn easily causes collapse of the bit line layer 205. In addition, the exposed sidewall of the bit line layer 205 is easily oxidized, thereby affecting the performance of the device structure.

On the basis, the invention provides a memory and a forming method thereof, wherein a protective layer is formed on the exposed side wall surface of an active region, and the side wall of a bit line layer is protected through the protective layer in the process of removing a second isolation layer, so that the transverse etching on the bit line layer is effectively reduced, and the problem of collapse of the bit line layer is prevented. In addition, the protective layer can also effectively prevent the side wall of the bit line layer from being oxidized, so that the performance of the device structure is improved.

In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention briefly described above will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.

Fig. 3 to 23 are schematic structural diagrams illustrating steps of a method for forming a memory according to an embodiment of the invention.

Referring to fig. 3 to 5, fig. 4 is a schematic cross-sectional view along line A-A in fig. 3, fig. 5 is a schematic cross-sectional view along line B-B in fig. 3, a substrate 100 is provided, the substrate 100 has a first surface 101 and a second surface 102 opposite to each other, the substrate 100 includes a plurality of active regions 103 separated from each other and parallel to a first direction X, the plurality of active regions 103 are arranged along a second direction Y, the first direction X is perpendicular to the second direction Y, each of the active regions 103 includes a plurality of word line regions 104 and a plurality of channel regions 105, and the plurality of word line regions 104 and the plurality of channel regions 105 in each of the active regions 103 are arranged at intervals along the first direction X.

In this embodiment, the material of the substrate 100 is silicon; in other embodiments, the material of the substrate may also be germanium, silicon carbide, gallium arsenide, or indium gallium.

In this embodiment, the channel region 105 and the word line region 104 are used to form a transistor device later.

Referring to fig. 6, the view directions of fig. 6 and fig. 4 are identical, and a first isolation layer 106 is formed between adjacent active regions 103.

In this embodiment, the method for forming the first isolation layer 106 includes: forming an initial isolation layer (not shown) between adjacent active regions 103 and on the first surface 101; the initial isolation layer is planarized until the first surface 101 is exposed, and the first isolation layer 106 is formed.

In this embodiment, the material of the first isolation layer 106 is silicon oxide.

Referring to fig. 7, the directions of the views of fig. 7 and fig. 5 are identical, a word line gate trench 107 is formed in each word line region 104, the word line gate trench 107 extends from the first face 101 to the second face 102, and the word line gate trench 107 penetrates the active region 103 along the second direction Y.

In this embodiment, the word line gate trench 107 provides space for subsequent formation of word line gate structures within the word line gate trench 107.

In this embodiment, the method for forming the word line gate trench 107 includes: forming a first patterned layer (not shown) on the first side 101 of the substrate 100, the first patterned layer exposing the word line region 104; and etching from the first surface 101 to the second surface 102 by using the first patterned layer as a mask to form the word line gate trench 107.

In this embodiment, the depth of the word line gate trench 107 is less than the depth of the first isolation layer 106. In other embodiments, the depth of the word line gate trench may also be equal to the depth of the isolation layer.

In this embodiment, in the process of forming the word line gate trench 107, the first isolation layer 106 and the word line region 104 need to be etched at the same time. Because the materials of the first isolation layer 106 and the word line region 104 are different, in the etching process, the etching rates of the first isolation layer 106 and the word line region 104 are different, which easily results in the uneven bottom of the finally formed word line gate trench 107, and thus easily affects the controllability of the subsequent process, and the stability and reliability of the finally formed device structure.

In this embodiment, please continue to refer to fig. 7, a planarization layer 121 is formed at the bottom of the word line gate trench 107.

In this embodiment, the method for forming the planarization layer 121 at the bottom of the word line gate trench 107 includes: forming a flat material layer (not shown) at the bottom of the word line gate trench 107 by a spin coating process, wherein the flat material layer is fluid; the flat material layer is cured to form the flat layer 121.

In this embodiment, the material of the planarization layer 121 includes an insulating dielectric material; the insulating dielectric material is silicon oxide.

By forming the planarization layer 121 at the bottom of the word line gate trench 107, the controllability of the subsequent process and the stability and reliability of the finally formed device structure can be effectively improved.

In other embodiments, the planarization layer may not be formed when the planarization of the bottom of the word line gate trench is higher.

Referring to fig. 8 and 9, fig. 9 is a schematic cross-sectional view along line C-C in fig. 8, in which two electrically isolated word line gate structures 108 are formed in each of the word line gate trenches 107.

In this embodiment, the method of forming two electrically isolated word line gate structures 108 within each of the word line gate trenches 107 includes: forming an initial word line gate structure (not shown) within each of the word line gate trenches 107; etching a portion of the initial word line gate structure from the first side 101 toward the second side 102, forming a plurality of openings (not labeled) in the substrate 100 parallel to the second direction Y, the openings penetrating the initial word line gate structure from the first side 101 toward the second side 102, and forming the initial word line gate structure into two word line gate structures 108 that are separated from each other; an insulating dielectric material is filled in the openings to electrically isolate the two word line gate structures 108.

In this embodiment, the depth of the opening is less than the height of the first isolation layer 106.

In this embodiment, the word line gate structure 108 includes: a word line gate dielectric layer on the side walls and bottom surface of the word line gate trench 107, and a word line gate layer (not labeled) on the word line gate dielectric layer.

In this embodiment, the word line gate layer adopts a composite structure, and the word line gate layer includes a first gate layer and a second gate layer (not labeled) located on the first gate layer, where materials of the first gate layer and the second gate layer are different.

In this embodiment, the material of the first gate layer is polysilicon, and the material of the second gate layer is metal; in other embodiments, the material of the first gate layer may also be metal, and the material of the corresponding second gate layer may be polysilicon.

In other embodiments, the word line gate layer may also have a single-layer structure, and when the word line gate layer has a single-layer structure, the material of the word line gate layer may be polysilicon or metal.

In this embodiment, the word line gate structure 108 is located on the planarization layer 121.

With continued reference to fig. 9, in this embodiment, the word line gate structure 108 does not fill the word line gate trench 107, and after forming the word line gate structure 108, further includes: a dielectric layer 109 is formed on the first side 101 of the substrate 100, the dielectric layer 109 fills the word line gate trench 107, and the dielectric layer 109 exposes the surface of the channel region 105.

Referring to fig. 10, the view directions of fig. 10 and fig. 9 are identical, a portion of the channel region 105 is etched from the first surface 101 toward the second surface 102, and a plurality of isolation openings 110 parallel to the second direction Y are formed in the substrate 100.

In this embodiment, the method for forming the isolation opening 110 includes: forming a second patterned layer (not shown) on the first side 101 of the substrate 100, the second patterned layer exposing a portion of the top surface of the dielectric layer 109 and a portion of the top surface of the channel region 105; and etching from the first surface 101 to the second surface 102 by using the first patterned layer as a mask to form the isolation opening 110.

In this embodiment, the depth of the isolation opening 110 is less than the height of the first isolation layer 106.

Referring to fig. 11, an isolation structure 111 is formed in the isolation opening 110.

In this embodiment, the method for forming the isolation structure 111 includes: forming a spacer material layer (not shown) within the spacer openings 110 and on the first face 101; the isolation material layer is planarized until the first surface 101 is exposed, so that the isolation structure 111 is formed.

In this embodiment, the isolation structure 111 is made of silicon oxide.

Referring to fig. 12, a first source-drain doped region 112 is formed in the first surface 101 of each channel region 105.

In this embodiment, the method for forming the first source-drain doped regions 112 in the first surface 101 of each channel region 105 includes: first ion implantation is performed from the first surface 101 to the second surface 102 by using an ion implantation process, and a first source/drain doped region 112 is formed in the first surface 101 of each channel region 105.

In this embodiment, the first ion is an N-type ion; in other embodiments, the first ions may also be P-type ions.

Referring to fig. 13, a plurality of capacitor structures 113 are formed on the first surface 101, and each capacitor structure 113 is electrically connected to one of the first source-drain doped regions 112.

In this embodiment, before forming the plurality of capacitor structures 113, the method further includes: forming a first conductive plug 114 on each of the first source-drain doped regions 112, each of the capacitor structures 113 being electrically connected to one of the first conductive plugs 114; in other embodiments, the first conductive plug may not be formed.

In this embodiment, the capacitor structure 113 includes: an upper electrode layer, a lower electrode layer, and a dielectric layer (not labeled) between the upper electrode layer and the lower electrode layer.

Referring to fig. 14, the substrate 100 is thinned from the second surface 102 toward the first surface 101 until the first isolation layer 106 is exposed.

The process of thinning the substrate 100 from the second surface 102 toward the first surface 101 includes a physical mechanical polishing process, a chemical mechanical polishing process, or a wet etching process. In this embodiment, the process of thinning the substrate 100 from the second surface 102 toward the first surface 101 uses a chemical mechanical polishing process.

In this embodiment, the depth of the first isolation structures 113 and the isolation structures 111 is equal to the depth of the first isolation layer 106. Thus, after the thinning process, the second side of the substrate 100 also exposes the surfaces of the first isolation structures 113 and the isolation structures 111.

In other embodiments, the depth of the first isolation structure and the second isolation structure may be smaller than the depth of the isolation layer, and the second face of the substrate does not expose the surfaces of the first isolation structure and the second isolation structure after the thinning process.

Referring to fig. 15, a second source-drain doped region 115 is formed in the second face 102 of each channel region 105.

In this embodiment, the method for forming the second source-drain doped regions 115 in the second face 102 of each channel region 105 includes: a second ion implantation process is performed from the second surface 102 to the first surface 101, so as to form a second source-drain doped region 115 in the second surface 102 of each channel region 105.

The second ion is of the same electrical type as the first ion.

In this embodiment, the second ion is an N-type ion; in other embodiments, when the first ion is a P-type ion, the second ion may also be a P-type ion.

In this embodiment, the depth of the second source-drain doped region 115 is greater than the spacing between the word line gate structure 108 and the second side 102 of the substrate 101; in other embodiments, the depth of the second source drain doped region 115 may also be equal to the spacing between the word line gate structure and the second side of the substrate.

From here on, a number of transistors are formed within the substrate 100.

Referring to fig. 16, fig. 16 is a schematic diagram of a structure with a capacitor omitted, the view directions of fig. 16 and fig. 6 are identical, and the first isolation layer 106 is etched back from the second surface 102 toward the first surface 101, so as to expose a portion of the sidewall surface of the active region 103.

In this embodiment, a wet etching process is used for etching back the first isolation layer 106; in other embodiments, the process of etching back the first isolation layer may also use a dry etching process.

Referring to fig. 17, an etching process is performed on the exposed active region 103 to reduce the width of the exposed active region 103.

In this embodiment, since the second source-drain doped region 115 is formed in the active region 103, the width of the exposed second source-drain doped region 115 is specifically reduced.

In this embodiment, the width of the exposed active region 103 is reduced, so as to reduce the width of the subsequently formed bit line layer, thereby increasing the space between adjacent bit line layers and reducing the parasitic capacitance between adjacent bit line layers.

Referring to fig. 18, a passivation layer 116 is formed on the exposed sidewall surface of the active region 103;

in this embodiment, the protective layer 116 is formed on the exposed sidewall surface of the second source-drain doped region 115.

In this embodiment, the material of the protection layer 116 is silicon nitride; in other embodiments, the material of the protective layer may also be titanium nitride or aluminum oxide.

Referring to fig. 19, after the protective layer 116 is formed, a second isolation layer 117 is formed on the second surface 102, and the second isolation layer 117 covers the sidewalls of the protective layer 116.

In this embodiment, the method for forming the protective layer 116 and the second isolation layer 117 includes: forming a protective material layer (not shown) on the exposed sidewall and top surfaces of the active region 103 and the surface of the first isolation layer 106; forming a spacer material layer (not shown) on the second face 102, the spacer material layer covering the protective material layer; the protective layer 116 and the second isolation layer 117 are formed by planarizing the isolation material layer and the protective material layer from the second surface 102 toward the first surface 101 until the surface of the active region 103 is exposed.

Referring to fig. 20, after the second isolation layer 117 is formed, the active region 103 is etched back from the second surface 102 toward the first surface 101, and a bit line opening 118 is formed in the second isolation layer 117.

In this embodiment, a wet etching process is used for etching back the active region 103; in other embodiments, the process of etching back the active region may also employ a dry etching process.

Referring to fig. 21, a bit line layer 119 is formed in the bit line opening 118.

In this embodiment, the bit line layer 119 includes: a polysilicon layer, a metal silicide layer on the polysilicon layer, and a metal layer (not shown) on the metal silicide layer.

In this embodiment, each of the bit line layers 119 is electrically connected to the second source-drain doped regions 115 in one of the active regions 109.

Referring to fig. 22, after the bit line layer 119 is formed, the second isolation layer 117 is removed.

In this embodiment, in the process of removing the second isolation layer 117, the side wall of the bit line layer 119 is protected by the protection layer 116, so that lateral etching on the bit line layer 119 is effectively reduced, and the problem of collapse of the bit line layer 119 is prevented. In addition, the protection layer 116 can also effectively prevent oxidation of the sidewall of the bit line layer 119, thereby improving the performance of the device structure.

Referring to fig. 23, after the second isolation layer 117 is removed, a third isolation layer 120 is formed on the second surface 102, the third isolation layer 120 covers the bit line layer 119 and the protection layer 116, and the third isolation layer 120 has a cavity 122 therein.

In this embodiment, by reforming the third isolation layer 120, and having the cavity 122 in the third isolation layer 120, the dielectric constant between the adjacent bit line layers 119 is reduced by the cavity 122, so as to reduce the parasitic capacitance between the adjacent bit line layers 119.

In this embodiment, by arranging the capacitor structure 113 and the bit line layer 119 on the first surface 101 and the second surface 102 of the substrate 100, the space of the capacitor structure 113 and the bit line layer 119 during arrangement can be increased, so that the difficulty of circuit wiring and manufacturing process can be effectively reduced, the area occupied by a single storage structure can be effectively reduced, and the storage density of the memory can be improved. In addition, in the process of forming the capacitor structure 113 and the bit line layer 119, the process can be performed from the first surface 101 and the second surface 102 of the substrate 100, so as to effectively improve the process efficiency.

In addition, from the perspective of the exposure process, since the capacitor structure 113 is a hole-like structure, the bit line layer 119 is a linear structure, the hole-like structure is exposed with a relatively high difficulty, the linear structure is exposed with a relatively high difficulty, and the exposure requirement is higher when the process is performed from the second surface 102. Therefore, the capacitor structure 113 with relatively high exposure difficulty is arranged on the first surface 101 of the substrate 100, and the bit line layer 119 with relatively low exposure difficulty is arranged on the second surface 102 of the substrate 100, so that the difficulty of the exposure process can be effectively reduced.

From the standpoint of signal extraction, the upper electrode plate of the capacitor structure 113 and the bit line layer 119 need to be extracted. Since the upper electrode plates of the capacitor structures 113 are connected to each other in the same memory, and thus a conductive region with a larger area is formed, the capacitor structures 113 are easily led out. The bit line layer 119 has a smaller line width and is correspondingly more difficult to be led out. Since the signal extraction is completed from the second surface 102 of the substrate 100 during the process of forming the memory, the capacitor structure 113 with smaller lead difficulty is arranged on the first surface 101 of the substrate 100, and the bit line layer 119 with larger lead difficulty is arranged on the second surface 102 of the substrate 100, so that the process difficulty during signal extraction can be effectively reduced.

In this embodiment, one of the capacitor structures 113 and one of the transistors are arranged in a two-dimensional matrix as one unit. The basic operation mechanism is divided into Read (Read) and Write (Write), and the bit line layer 119 is charged to half the operation voltage during Read, and then the transistor is turned on, so that the bit line layer 119 and the capacitor structure 113 share charges. If the internally stored value is 1, the voltage of the bit line layer 119 will be raised by charge sharing to be higher than half the operating voltage; conversely, if the value stored internally is 0, the voltage of the bit line layer 119 is pulled down to be lower than half the operation voltage, and the value inside is determined to be 0 or 1 by an amplifier after the voltage of the bit line layer 119 is obtained. Turning on the transistor when writing, and raising the voltage of the bit line layer 119 to an operating voltage when writing a 1 to cause the capacitor structure 113 to store the operating voltage; lowering the bit line layer 119 to 0 volts leaves no charge inside the capacitance structure 113 if a 0 is to be written.

Accordingly, in an embodiment of the present invention, a memory is further provided, please continue to refer to fig. 23, which includes: a substrate 100, the substrate 100 having a first side 101 and a second side 102 opposite to each other, the substrate 100 comprising a plurality of active regions 103 separated from each other and parallel to a first direction X, and the plurality of active regions 103 being arranged along a second direction Y, the first direction X being perpendicular to the second direction Y; a first isolation layer 106 located between adjacent ones of the active regions 103; a plurality of bit line layers 119 on said second side 102, each of said bit line layers 119 being electrically connected to one of said active regions 103; a protective layer 116 on the sidewall of the bit line layer 119; a third isolation layer 120 on the second side 102, the third isolation layer 120 covering the bit line layer 119 and the protection layer 116, and the third isolation layer 120 having a cavity 122 therein.

In this embodiment, the side wall of the bit line layer 119 is protected by the protection layer 116, so that lateral etching on the bit line layer 119 is effectively reduced, and the problem of collapse of the bit line layer 119 is prevented. In addition, the protection layer 116 can also effectively prevent oxidation of the sidewall of the bit line layer 119, thereby improving the performance of the device structure.

In this embodiment, the width of the bit line layer 119 is smaller than the width of the active region 103. By decreasing the width dimension of the exposed active region 103, and thus the width dimension of the bit line layer 119, the pitch dimension between adjacent bit line layers 119 is increased, and thus the parasitic capacitance between adjacent bit line layers 119 is reduced.

In this embodiment, the material of the protective layer 116 is silicon oxide. In other embodiments, the material of the protective layer may also be titanium nitride or aluminum oxide.

In this embodiment, the bit line layer 119 includes: a polysilicon layer, a metal silicide layer on the polysilicon layer, and a metal layer on the metal silicide layer.

In this embodiment, each of the active regions 109 includes a plurality of word line regions 104 and a plurality of channel regions 105, and the plurality of word line regions 104 and the plurality of channel regions 105 in each of the active regions 103 are arranged at intervals along the first direction X.

In this embodiment, further comprising: a word line gate trench 107 located within each of the word line regions 104, the word line gate trench 107 extending from the first face 101 to the second face 102, and the word line gate trench 107 extending through the active region 103 in the second direction Y; two electrically isolated word line gate structures 108 located within each of the word line gate trenches 107.

In this embodiment, further comprising: an isolation opening 110 located within each of the channel regions 105; an isolation structure 111 located within the isolation opening 110; a first source-drain doped region 112 located in each of the channel region first faces 101; a plurality of capacitor structures 113 located on the first surface 101, each capacitor structure 113 being electrically connected to one of the first source-drain doped regions 112; a second source drain doped region 115 located within the second side 102 of each of the channel regions 105.

In this embodiment, each of the bit line layers 119 is electrically connected to the second source-drain doped regions 115 in one of the active regions 103.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (16)

1. A method of forming a memory, comprising:

providing a substrate, wherein the substrate is provided with a first surface and a second surface which are opposite, the substrate comprises a plurality of active areas which are mutually separated and parallel to a first direction, and the plurality of active areas are arranged along a second direction, and the first direction is perpendicular to the second direction;

forming a first isolation layer on the first surface, wherein the first isolation layer is positioned between adjacent active areas;

thinning the substrate from the second surface to the first surface until the first isolation layer is exposed;

etching back the first isolation layer from the second surface to the first surface to expose part of the side wall surface of the active region;

forming a protective layer on the exposed side wall surface of the active region;

forming a second isolation layer on the second face after forming the protection layer, wherein the second isolation layer covers the side wall of the protection layer;

etching back the active region from the second face to the first face after forming the second isolation layer, and forming a bit line opening in the second isolation layer;

forming a bit line layer within the bit line opening;

removing the second isolation layer after forming the bit line layer;

after the second isolation layer is removed, a third isolation layer is formed on the second face, the third isolation layer covers the bit line layer and the protection layer, and a cavity is formed in the third isolation layer.

2. The method of forming a memory device of claim 1, further comprising, after exposing a portion of a sidewall surface of the active region and before forming the protective layer: and etching the exposed active region to reduce the width dimension of the exposed active region.

3. The method of forming a memory device according to claim 1, wherein the method of forming the protective layer and the second isolation layer comprises: forming a protective material layer on the exposed side wall and top surface of the active region and the surface of the first isolation layer; forming a spacer material layer on the second face, the spacer material layer covering the protective material layer; and flattening the isolation material layer and the protection material layer from the second surface to the first surface until the surface of the active region is exposed, so as to form the protection layer and the second isolation layer.

4. The method of forming a memory of claim 1, wherein the material of the protective layer comprises: silicon nitride, titanium nitride or aluminum oxide.

5. The method of forming a memory of claim 1, wherein the bit line layer comprises: a polysilicon layer, a metal silicide layer on the polysilicon layer, and a metal layer on the metal silicide layer.

6. The method of forming a memory of claim 1, wherein each of the active regions includes a plurality of word line regions and a plurality of channel regions, and the plurality of word line regions and the plurality of channel regions in each of the active regions are spaced apart along the first direction; before thinning the substrate, the method further comprises: forming a word line gate trench within each of the word line regions, the word line gate trench extending from the first face to the second face, and the word line gate trench extending through the active region in the second direction; two electrically isolated word line gate structures are formed within each of the word line gate trenches.

7. The method of forming a memory of claim 6, further comprising, after forming the word line gate structure: etching part of the channel region from the first surface to the second surface, and forming a plurality of isolation openings parallel to the second direction in the substrate; forming an isolation structure in the isolation opening; forming a first source-drain doped region in a first surface of each channel region; forming a plurality of capacitor structures on the first surface, wherein each capacitor structure is electrically connected with one first source-drain doped region; and forming a second source-drain doped region in the second surface of each channel region.

8. The method of claim 7, wherein each of said bit line layers is electrically connected to a plurality of said second source drain doped regions in one of said active regions.

9. A memory, comprising:

a substrate having opposite first and second sides, the substrate comprising a plurality of active regions separated from each other and parallel to a first direction, the plurality of active regions being arranged along a second direction, the first direction being perpendicular to the second direction;

a first isolation layer located between adjacent ones of the active regions;

a plurality of bit line layers on the second side, each bit line layer electrically connected to one of the active regions;

a protective layer located on the sidewall of the bit line layer;

and a third isolation layer on the second surface, wherein the third isolation layer covers the bit line layer and the protection layer, and a cavity is formed in the third isolation layer.

10. The memory of claim 9, wherein a width dimension of the bit line layer is less than a width dimension of the active region.

11. The memory of claim 9, wherein the material of the protective layer comprises: silicon nitride, titanium nitride or aluminum oxide.

12. The memory of claim 9, wherein the bit line layer comprises: a polysilicon layer, a metal silicide layer on the polysilicon layer, and a metal layer on the metal silicide layer.

13. The memory of claim 9, wherein each of the active regions includes a plurality of word line regions and a plurality of channel regions, and wherein the plurality of word line regions and the plurality of channel regions in each of the active regions are spaced apart along the first direction.

14. The memory of claim 13, further comprising: a word line gate trench within each of the word line regions, the word line gate trench extending from the first face to the second face, and the word line gate trench extending through the active region in the second direction; two electrically isolated word line gate structures located within each of the word line gate trenches.

15. The memory of claim 14, further comprising: an isolation opening in each of the channel regions; an isolation structure located within the isolation opening; a first source-drain doped region located in a first face of each channel region; a plurality of capacitor structures located on the first surface, each capacitor structure being electrically connected to one of the first source-drain doped regions; and a second source-drain doped region located in a second face of each channel region.

16. The memory of claim 15 wherein each of said bit line layers is electrically connected to a plurality of said second source drain doped regions in one of said active regions.

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