KR100632058B1 - High density memory device and method for manufacturing thereof - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a highly integrated semiconductor memory device and a method of manufacturing the same, and in particular, the memory device of the present invention vertically in a substrate between a top and bottom impurity junction layer and a top and bottom impurity junction layer separated from each other in a semiconductor substrate. A formed gate insulating film and a cylindrical gate electrode, a capping film formed on the top surface of the gate electrode and the gate insulating film, and a storage node electrode, a dielectric film, and a plate node electrode connected to a lower impurity junction layer in a trench in the semiconductor substrate between the gate electrode. And a bit line connected to the upper impurity junction layer through a contact hole in at least one interlayer insulating film over the semiconductor substrate. Therefore, in the present invention, since the cell transistor is formed in the vertical structure on the substrate and the capacitor is formed in the trench structure, the area of the cell transistor can be reduced in the highly integrated design rule, and the capacitor can also secure high capacitance.

Description

Highly integrated semiconductor memory device and manufacturing method therefor {HIGH DENSITY MEMORY DEVICE AND METHOD FOR MANUFACTURING THEREOF}

1 is a view showing the layout of a highly integrated semiconductor memory device according to the present invention;

2A to 2L are process flowcharts illustrating a manufacturing process of a highly integrated semiconductor memory device according to an embodiment of the present invention.

<Description of the code | symbol about the principal part of drawing>

10 semiconductor substrate 14 lower impurity junction layer (drain)

18: upper impurity junction layer (source) 36: gate electrode

54 storage node electrode 56 dielectric film

58: plate node electrode 68: bit line (B / L)

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a method of manufacturing the same. In particular, a capacitor having a trench structure capable of securing high capacitance according to high integration of a memory device, and a vertical cell transistor in a substrate to overcome a reduction in the cell area. A high integrated semiconductor memory device and a method of manufacturing the same.

In general, a semiconductor memory device refers to a device that stores data and can be read out when needed. There are various kinds of semiconductor memory mainly from DRAM (Dynamic Random Access Memory) and the like, such as magnetic disks and optical disks. Among them, semiconductor memory is compact, has high reliability, and can be operated at relatively high speed. Therefore, semiconductor memory is widely used in the form of main memory located inside a computer, investment memory in a microprocessor, and cache memory.

A typical example of nonvolatile memory, a DRAM includes a word line driven by a row address and a bit line driven by a column address and connected to the bit line and the word line. It consists of a cell transistor and a capacitor connected to the cell transistor to which data is written.

At present, in order to achieve high integration of semiconductor memory devices, research / development has been actively conducted on reduction of cell area and reduction of operating voltage. In addition, as the integration becomes higher, the area of the capacitor decreases, and thus the charge required for the operation of the memory device, that is, the capacitance secured in the unit area, must be further increased.

The basic structure of a capacitor used in a memory cell is composed of a storage node electrode, a dielectric layer, and a plate node electrode. Capacitors having such a structure have a first thin dielectric film thickness, a second three-dimensional capacitor structure to increase the effective area, or a third dielectric material in order to obtain a larger fixed capacitance in a small area. Conditions such as forming a dielectric film must be satisfied.

Among these, in order to secure a high capacitance by increasing the cross-sectional area of the storage node electrode with a three-dimensional structure, the structure of the storage node electrode is divided into stacks, trenches, cylinders, fins, and stack cylinders. stack cylinder).

SUMMARY OF THE INVENTION An object of the present invention is to provide a capacitor having a trench structure capable of securing high capacitance according to high integration of a memory device, and having a gate electrode and a source / drain junction of a vertical cylinder structure in a substrate to overcome the reduction of the cell area. The present invention provides a highly integrated semiconductor memory device having a cell transistor.

Another object of the present invention is to fabricate a cell capacitor having a trench structure capacitor and a gate electrode and a source / drain junction of a vertical cylinder structure in a substrate, thereby ensuring high capacitance and reducing cell area according to high integration of a memory device. However, the present invention provides a method of manufacturing a highly integrated semiconductor memory device capable of optimizing the performance of a cell transistor.

In order to achieve the above object, the present invention provides a semiconductor memory device comprising: an upper and a lower impurity junction layer separated from each other in a semiconductor substrate, and a gate insulating film and a cylindrical gate formed vertically in a substrate between the upper and lower impurity junction layers. A capacitor comprising a electrode, a capping film formed on the top surface of the gate electrode and the gate insulating film, a storage node electrode, a dielectric film, and a plate node electrode connected to a lower impurity junction layer in a trench in the semiconductor substrate between the gate electrode, and a semiconductor. And a bit line connected to the upper impurity junction layer through at least one contact hole in the interlayer insulating layer on the substrate.

In accordance with another aspect of the present invention, there is provided a method of manufacturing a semiconductor memory device, the method comprising: forming an upper and a lower impurity junction layer separated from each other in a semiconductor substrate, and etching from a substrate surface to a surface of the lower impurity junction layer; Forming a first trench to form a gap fill insulating film in the first trench, etching a substrate surface between the gap fill insulating film and a lower impurity bonding layer to form a second trench, and forming an insulating film on the bottom of the second trench. Forming a gate insulating film on the inner sidewall of the second trench; forming a cylindrical gate electrode by embedding the conductive film in the second trench; and forming a capping film on the upper portion of the second trench; And removing the gap fill insulating layer of the first trench and forming the lower impurity junction layer in the first trench. Forming a connected storage node electrode, forming a dielectric film and a plate note electrode on the storage node electrode, forming a second interlayer insulating film on the resultant, and forming a contact hole between the second interlayer insulating film and the first interlayer insulating film. Forming a bit line connected to the upper impurity junction layer through the semiconductor substrate.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.                     

1 is a view showing a layout of a highly integrated semiconductor memory device according to the present invention, in which the word line (W / L) and the bit line (B / L) are intersected with each other, and the cells of each intersection portion are disposed in the DRAM to which the present invention is applied. In the region, a cell capacitor is formed on the same line as the word line W / L through the trench mask 24 of the trench structure. The contact mask 67 for the bit line B / L defines an area to overlap the substrate between the word lines W / L adjacent to each other to form a bit line contact. In addition, reference numeral 70 denotes a line in which a ground (GND) or a Vss power is supplied to the cell transistor or the capacitor in parallel with the bit line. Therefore, in the DRAM of the present invention, since the cell transistor is formed in the vertical structure on the substrate and the capacitor is formed in the trench structure, the area of the cell transistor can be reduced in the highly integrated design rule, and the capacitor can also secure high capacitance.

2A to 2L are process flowcharts illustrating a manufacturing process of a highly integrated semiconductor memory device according to an exemplary embodiment of the present invention. A DRAM manufacturing process according to the present exemplary embodiment will be described with reference to these drawings.

First, as shown in FIG. 2A, a silicon oxide film (SiO 2) is grown as an insulating film 20 on the silicon substrate as the semiconductor substrate 10, and ion implantation is performed in the substrate to form the p-well 12. . In addition, n + or p + impurity ion implantation processes are performed to form upper and lower impurity junction layers 14 and 18 which are separated from each other in the p-well 12, respectively. At this time, the lower impurity junction layer 14 becomes an n + drain junction layer and the upper impurity junction layer 18 becomes an n + source junction layer. The height of the substrate 16 separating the upper and lower impurity junction layers 14 and 18 becomes the channel length of the device.

As illustrated in FIG. 2B, after depositing BPSG (Boro Phosphorus Silicate Glass) as an insulating film 22 having a different etching selectivity on the insulating film 20, a photolithography process is performed on the insulating film 22 to form a trench. The photoresist pattern 24 defining the capacitor region is formed. Patterning the insulating layers 22 and 20 exposed by the photoresist pattern 24 and dry etching the exposed substrate 10 to a predetermined depth, until the surface of the lower impurity bonding layer 14 serving as a drain region is exposed. The first trench 26 is formed.

Next, as shown in FIG. 2C, a linear layer 28 is further formed on the inner wall of the first trench 26. In this case, the liner insulating layer 28 is formed of a silicon nitride film (Si 3 N 4) or a silicon oxide film (SiO 2). If the silicon oxide film is grown by thermal oxidation to form the liner insulating film 28, n + / p + impurities of the upper and lower impurity bonding layers 18 and 14 are diffused during the thermal oxidation process, and the corresponding bonding layer ( The silicon oxide film in 18 and 14 is grown 5 to 7 times thicker than the other parts. However, in the drawings of the present invention, the liner insulating film 28 is shown to have the same thickness.

Subsequently, as shown in FIG. 2D, the silicon nitride film is buried as a gap-fill dielectric layer 30 in the first trench 26 in which the liner insulating film 28 is formed, and the surface is etched back. Or chemical mechanical polishing (CMP).                     

Subsequently, the insulating layers 20 and 22 used as the etching mask of the first trench are removed. As shown in FIG. 2E, the spacer insulating layer 32 is formed on both sidewalls of the gap fill insulating layer 30. In this case, the spacer insulating film 32 may be formed of an insulating film having an etching selectivity with the gap fill insulating film 30.

Then, as shown in FIG. 2F, using the spacer insulating film 32 as an etch mask, the substrate surface between the gap fill insulating film 30, that is, the upper impurity bonding layer 18 to the lower impurity bonding layer 14, is dried. Etching forms a second trench 33 in which a cell transistor is to be formed.

Subsequently, as shown in FIG. 2G, a silicon oxide film is grown as an insulating film 34 on the bottom of the second trench 33, and a gate insulating film 35 is formed on the inner wall of the second trench 33. In this case, the gate insulating layer 35 may be formed by depositing the silicon oxide layer by a wet or dry oxidation process. A doped polysilicon or metal is embedded in the second trench 33 to form a cylindrical gate electrode 36, and a capping layer 38 is formed thereon. Accordingly, in the second trench 33 region, a cylindrical gate 36 perpendicular to the substrate is formed, and the vertical cell transistors together with the source / drain junction layers 18 and 14 previously separated into upper and lower layers in the substrate. Configure

Then, an undoped silicate glass (USG), BPSG, or Phosphorus Silicate Glass (PSG) is deposited as the first interlayer insulating film 40 on the entire surface of the resultant, and the surface is planarized by full etching or CMP.                     

As shown in FIG. 2H, the gap fill insulating layer 30 of the first trench may be selectively etched to expose the first trench region 50 by a wet etching process, and then the liner insulating layer 28 inside the first trench may be cleaned. ).

Then, an additional spacer insulating film 52 is formed on the inner sidewall of the region of the first trench 26 and dry etching the exposed lower impurity bonding layer 14 and the substrate using the etching mask as a drain mask. It is etched to a predetermined depth until it passes completely through (14) vertically.

As shown in FIG. 2I, a gap is formed by depositing n-doped polysilicon as a conductive film and applying a photoresist 55 to a trench region etched to the lower impurity junction layer 14 and the substrate 10 to a predetermined thickness. After the photoetching or etching with CMP, the photoresist 55 is removed to form the storage node electrode 54 according to the present invention. In this case, the storage node electrode 54 is electrically connected to the drain, which is the lower impurity junction layer 14, while being separated from the source, which is the upper impurity junction layer 18, by the spacer insulating layer 52.

Next, as shown in FIG. 2J, an oxide / nitride / oxide (ONO) is deposited on the entire surface of the structure as the dielectric film 56, and an n-doped polysilicon film or a metal is deposited on the plate node electrode (as a conductive film). 58) and pattern them. Then the capacitor of the trench structure is completed according to the present invention.

This trench structure capacitor is deposited with USG, BPSG or PSG as the second interlayer insulating film 60 on the entire surface of the finished product and the surface is planarized by full etching or CMP.

2K and 2L, the contact hole exposing the upper impurity junction layer 18 while exposing the surface of the capping layer by etching the second interlayer insulating layer 60 to the first interlayer insulating layer 40 ( Not shown). In order to prevent short between the storage node electrode 54 and the plate node electrode 58 adjacent to the sidewall in the contact hole, a spacer insulating layer 66 is formed and doped polysilicon or metal is deposited as a conductive layer in the contact hole. This patterning is performed to form the upper impurity junction layer 18, that is, the bit line 68 connected to the source, to complete the DRAM cell manufacturing process according to the present invention.

By such a manufacturing process, the DRAM cell of the present invention is the source / drain junction layers 18 and 14, which are the upper and lower impurity junction layers separated from each other in the semiconductor substrate 10, and the source / drain junction layers 18, A vertical cell transistor having a gate insulating film 35 and a cylindrical gate electrode 36 arranged vertically in the substrate between the 14 is formed. A trench structure capacitor including a storage node electrode 54, a dielectric film 56, and a plate node electrode 58 connected to the drain junction layer 14 is formed in a trench in the semiconductor substrate between the gate electrodes 36. A bit line (B / L) 68 is formed to be connected to the source bonding layer 18 through contact holes in the interlayer insulating layers 60 and 40 on the substrate 10. In the DRAM of the present invention, the gate electrode 36 is used for the word line W / L of the cell transistor.

As described above, in the DRAM of the present invention, since the cell transistor is formed in the vertical structure on the substrate and the capacitor is formed in the trench structure, the area of the cell transistor can be reduced in the highly integrated design rule, and the capacitor can also secure high capacitance. Can be.

On the other hand, the present invention is not limited to the above-described embodiment, various modifications are possible by those skilled in the art within the spirit and scope of the present invention described in the claims to be described later.

Claims (16)

In the method of manufacturing a semiconductor memory device, Forming upper and lower impurity junction layers, each being separated from each other, in a semiconductor substrate; Etching from the surface of the substrate to the surface of the lower impurity bonding layer to form a first trench, and forming a gap fill insulating layer in the first trench; Forming a second trench by etching the substrate surface between the gap fill insulating layers and the lower impurity bonding layer; Forming an insulating film on the bottom of the second trench and forming a gate insulating film on the inner sidewall of the second trench; Embedding a conductive film in the second trench to form a cylindrical gate electrode and forming a capping film thereon; Forming a first interlayer insulating film on the entire surface of the resultant product; Removing the gap fill insulating layer of the first trench and forming a storage node electrode connected to the lower impurity junction layer in the first trench; Forming a dielectric film and a plate note electrode on the storage node; And Forming a second interlayer insulating film on the resultant, and forming a bit line connected to the upper impurity bonding layer through a contact hole of the first interlayer insulating film from the second interlayer insulating film. Method of preparation. The method of claim 1, wherein the forming of the upper and lower impurity junction layer, And forming an insulating film over the semiconductor substrate, and implanting impurity ions into the semiconductor substrate to form upper and lower impurity junction layers separated from each other in the substrate. 2. The method of claim 1, wherein the height difference between the upper and lower impurity junction layers is a channel length of the device. The method of claim 1, wherein the upper and lower impurity junction layers are implanted with n + or p + high concentration impurities. The method of claim 1, further comprising forming a liner insulating layer on the inner sidewall of the first trench. The method of claim 1 or 5, wherein when the liner insulating film is a silicon oxide film grown by a thermal oxidation process, impurities of the upper and lower impurity junction layers are diffused during the thermal oxidation process. Manufacturing method. The method of claim 1, wherein the forming of the second trench further comprises forming a spacer insulating film on a sidewall of the gap fill insulating film, and using the spacer insulating film as a mask to form a lower impurity bonding layer from a substrate surface between the gap fill insulating films. A method for manufacturing a highly integrated semiconductor memory device, characterized in that to form a second trench etched up to. The method of claim 1, further comprising: performing a planarization process after forming the first interlayer insulating film. The method of claim 1, further comprising, after removing the gap fill insulating layer of the first trench, further forming a spacer insulating layer inside the first trench. The method of claim 1, further comprising: forming a storage node in the trench after removing the gap fill insulating layer of the first trench, further forming a trench to penetrate the lower impurity bonding layer. A method for manufacturing a highly integrated semiconductor memory device, characterized by the above-mentioned. In a semiconductor memory device, Upper and lower impurity bonding layers each separated from each other in the semiconductor substrate; A gate insulating film and a cylindrical gate electrode vertically formed in a substrate between the upper and lower impurity junction layers; A capping layer formed on the gate electrode and an upper surface of the gate insulating layer, respectively; A capacitor comprising a storage node electrode, a dielectric film, and a plate node electrode connected to the lower impurity junction layer in trenches in the semiconductor substrate between the gate electrodes; And And a bit line connected to the upper impurity junction layer through at least one contact hole in the interlayer insulating layer on the semiconductor substrate. 12. The high density semiconductor memory device of claim 11, wherein the height difference between the upper and lower impurity junction layers is a channel length of the device. The semiconductor device of claim 11, wherein the upper and lower impurity junction layers are implanted with n + or p + high concentration impurities. 12. The highly integrated semiconductor memory device of claim 11, wherein a liner insulating film is further formed on the inner sidewall of the first trench. 12. The high density semiconductor memory device of claim 11, wherein the trench in the semiconductor substrate between the gate electrodes is formed deeper than the lower impurity junction layer. The highly integrated semiconductor memory of claim 15, wherein a spacer insulating layer is further formed on an inner sidewall of the trench from the upper impurity junction layer to the upper impurity junction layer to insulate the upper impurity junction layer from the storage node electrode. Device.

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