JP2001244433A - Dram and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a DRAM and its manufacturing method whereby the layout area of its memory cells is saved to make increasable the integration density of its memory cells. SOLUTION: In the manufacturing method of the DRAM, after forming its trenches in a substrate 500, a vertical type transistor and a trench capacitor 400a (400b) are so provided as to form them respectively in the upper and lower portions of each trench.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a DRAM (Dynamic).
More particularly, the present invention relates to a DRAM of a vertical transistor and a trench capacitor and a method of manufacturing the same.

[0002]

2. Description of the Related Art As shown in FIG. 1, a memory unit of a DRAM device is a combination of a transfer transistor T and a storage capacitor C. The source CS of the transfer transistor T is connected to the corresponding bit line BL, the drain is connected to the storage electrode 100 of the storage capacitor C, and the gate GC is connected to the corresponding word line WL. The counter electrode 102 of the storage capacitor C is connected to a fixed voltage source.

[0003] The DRAM structure is mainly divided into two types: a stacked capacitor and a trench capacitor. Regardless of whether the capacitor is a stacked capacitor or a trench capacitor, the difficulty of manufacturing technology thereof is gradually increasing in accordance with the need for minimizing the size of a semiconductor device.

As shown in a layout diagram of FIG. 2 and a sectional view of FIG. 3 (a sectional view taken along the line III-III of FIG. 2), a DRAM having a trench capacitor has a word line WL and a source / source line.
Drain 300 and one trench capacitor DT
And is formed on the semiconductor substrate 302. Source / drain 300 is electrically connected to bit line BL at bit line contact window CB.

[0005]

However, since the transistors in the horizontal direction occupy a size corresponding to the entire memory unit AA, the degree of reduction in DRAM memory cells is limited, and the density (integration degree) of the memory cell array is limited. Made it difficult to increase.

DRA having trench capacitor as described above
The layout of the M memory unit has a word line pair structure, in which the word line on the trench capacitor DT is a passive word line, and the word line adjacent to the trench capacitor DT is an active word line. Therefore, one memory unit occupies an area of 2 word line pitch × 1 bit line pitch. Since a memory unit having a rectangular shape as a whole restricts a layout method of a DRAM memory cell, it has not been possible to meet a demand for a smaller semiconductor manufacturing line width.

SUMMARY OF THE INVENTION It is an object of the present invention to replace a horizontal transistor with a vertical transistor, thereby saving the layout area of the memory cell and increasing the degree of integration of the DRA.
M and its manufacturing method.

[0008]

A method of manufacturing a DRAM according to the present invention comprises the steps of forming a trench in a substrate and forming a trench capacitor having a storage electrode, a capacitor dielectric film and an upper electrode sufficiently deep in the trench. Forming a first polysilicon film in the trench in conductive connection with the upper electrode, and forming a doping region as a source of a vertical transistor on a side wall of the substrate adjacent to the first polysilicon film; Forming a second polysilicon film as a gate in the trench insulated from the first polysilicon film and insulated from a side wall of the substrate by a gate oxide film; Forming a common drain of a vertical transistor by doping on a substrate surface portion, and forming a word line on the substrate in parallel with the common drain. Forming a bit line on the substrate in a direction perpendicular to the word line, and forming a bit line on the substrate in a direction perpendicular to the word line; Electrically connecting the common drain with a contact window.

The DRAM of the present invention has a trench capacitor, a vertical transistor, a word line and a bit line. The trench capacitor has an upper electrode formed in a trench of a substrate and a capacitor dielectric surrounding the upper electrode. A film, and a storage electrode surrounding the capacitor dielectric film, a vertical transistor is formed in the trench, and a gate insulated from the upper electrode by an insulating film;
A source formed on the substrate between the gate and the upper electrode, electrically connected to the upper electrode, and a common drain formed on the surface of the substrate above the gate;
The word line is formed on the isolation structure on the substrate surface in a direction parallel to the common drain, is electrically connected to the gate by a gate contact window, and the bit line is formed on an insulating film covering the substrate. And arranged in a direction perpendicular to the word line, and electrically connected to the common drain through a bit line contact window.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings. FIG. 4 is a layout diagram of a DRAM according to an embodiment of the present invention, and FIGS.
FIG. 4 is a diagram illustrating the DRAM in a manufacturing process order along a line IV-IV. First, an embodiment of a method of manufacturing a DRAM according to the present invention will be described with reference to FIGS.

[0011] As shown in FIG.
A pad oxide film 502 and a hard mask film 504 are sequentially formed thereon.
Then, a hard mask film 504 is defined by a photolithography etching method, and the hard mask film 50 is formed.
An opening is formed in 4 (not shown in the figure). Thereafter, using the hard mask film 504 as a mask, the substrate 500 is etched along the opening by anisotropic etching to form a pair of left and right trenches 506. Here, the pad oxide film 502
Is an oxide thin film or the like formed by a thermal oxidation method, and increases the adhesive force between the substrate 500 and the hard mask film 504. The hard mask film 504 is a silicon nitride film formed by a chemical vapor deposition method or the like. Further, the shape of the trench 506 is not limited to the shape shown in the drawings and the above-described manufacturing process, and a bottle-shaped trench may be formed by using another manufacturing process.

Next, as shown in FIG. 5A, a storage electrode 508 is formed on the side wall of the substrate 500 at the bottom of the trench 506 to form a storage electrode for a trench capacitor. After forming a doped oxide film (not shown) at the bottom of the trench 506, the storage electrode 508 is subjected to a heat treatment process on the substrate 500 so that impurity ions in the doped oxide film are formed on the side wall of the substrate 500 at the bottom of the trench 506. It is formed by diffusion. After that, the doping oxide film is removed. Storage electrode 5
After forming 08, a capacitor dielectric film 510 such as nitride / oxide is formed on the bottom sidewall of the trench 506 to cover the storage electrode 508. Thereafter, a conductive film 514 is formed in the trench 506, which fills the trench 506 and extends to the surface of the hard mask film 504.
The conductive film 514 is a doped polysilicon film formed by a chemical vapor deposition method or the like.

Subsequently, as shown in FIG. 5B, a recess 516 is formed in the conductive film 514 and the conductive film 5 is formed in the trench 506 to the same height as the capacitor dielectric film 510.
The upper electrode (opposite electrode) 514a of the pair of left and right trench capacitors is formed by filling with 14a. More specifically, the formation of the upper electrode 514a is performed by polishing the conductive film 514 to the hard mask film 504 by a chemical mechanical polishing method or the like, and furthermore, forming the conductive film 514 in the trench 506 at a predetermined height by dry etching or wet etching. This is done by etching.

Subsequently, as shown in FIG. 5B, a collar oxide film (formed by a chemical vapor deposition method or the like) is formed on the side wall of the trench 506 which is not covered by the capacitor dielectric film 510 above the upper electrode 514a. A color insulating film 512 such as a collar oxide layer) is formed. At this time, the upper electrode 51
Since the collar oxide film is also formed on the upper surface of 4a, the collar oxide film is removed to leave only the collar insulating film 512 covering the side wall of the trench 506. Then, the upper electrode 5
The conductive film 515 is filled again on 14a. This conductive film 5
15 extends to the surface of the hard mask film 504. The conductive film 515 is a doped silicon film formed by a chemical vapor deposition method or the like. Thereafter, the conductive film 51 is formed by a chemical mechanical polishing method or the like.
5 is polished to a hard mask film 504, and furthermore, the conductive film 515 is etched to a predetermined height in the trench 506 by dry etching or wet etching, so that the conductive film 515 as shown in FIG. Is slightly increased, and a conductive film 515 insulated from the substrate 500 by the surrounding collar insulating film 512 is formed. After that, the color insulating film 51 other than the conductive film 515 portion
2 is also removed.

Next, as shown in FIG.
15 and a first polysilicon film 51 on the collar insulating film 512.
8, the first polysilicon film 518 is made continuous with the conductive film 515, and the first polysilicon film 518 is formed.
To fill the trench 506 to an appropriate height. This first
The polysilicon film 518 is formed by filling the trench 506 with polysilicon and then forming a recess 520 in the polysilicon which is shallower than the etching depth of the conductive film 515 by chemical mechanical polishing and etching. Subsequently, impurity ions are implanted into the first polysilicon film 518 to turn the first polysilicon film 518 into doped polysilicon. Thereafter, a heat treatment step is performed to
An impurity is diffused from the polysilicon film 518 to the side wall of the adjacent substrate 500 to form a doping region 522. This doping region 522 is used as a source of a pair of left and right vertical transistors.

Subsequently, as shown in FIG.
A cover film 524 is formed on the side wall of the substrate 500 exposed at 0 (the trench 506 on the first polysilicon film 518). The cover film 524 is formed by forming a silicon nitride film along a surface step by a chemical vapor deposition method or the like, and then etching back the silicon nitride film to form a nitride film on the hard mask film 504 and the first polysilicon film 518. This is formed by removing the silicon film and leaving the silicon nitride film on the side wall of the substrate 500 exposed at the recess 520. At this time,
Before the formation of the silicon nitride film, an oxide thin film (omitted in the drawing) may be formed on the side wall of the substrate 500 to increase the adhesion between the side wall of the substrate 500 and the cover film 524.

Next, by performing a heat treatment step or the like in a furnace containing oxygen, an oxide film 518b is formed on the exposed surface of the first polysilicon film 518 as shown in FIG.
(Insulating film) is formed, and this oxide film 518b is used for gate and source insulation isolation. At this time, as shown in FIG. 6A, since the cover film 524 is on the side wall of the substrate 500 on the first polysilicon film 518, when the heat treatment process of the oxide film 518b is performed, the substrate 500 in the recess 520 is not formed. Is prevented from being oxidized. Then, the cover film 524
Is removed, and the substrate side wall 520a of the recess 520 is exposed again.

Thereafter, the side wall 520 of the exposed recess 520 is formed.
A sacrificial oxide thin film (not shown) is formed on the surface a. Thereafter, ion implantation (channel implantation) is performed on the side wall 520a through the sacrificial oxide thin film, and the side wall 520a is formed.
Create a vertical transistor channel in the section. At this time, the channel implantation is, for example, ion implantation having an inclination angle with respect to the side wall 520a. Thereafter, after the sacrificial oxide thin film is removed, the thermal oxidation step is again performed on the substrate 500, and the exposed surface of the side wall 520a is formed as shown in FIG.
A gate oxide film 526 is formed as shown in FIG.

Next, as shown in FIG.
0, the second surface is lower than the surface 500a of the substrate 500;
A polysilicon film 528 is formed. After depositing a polysilicon film in the recess 520, the second polysilicon film 528 is subjected to a step such as chemical mechanical polishing or etching on the polysilicon film to form a recess 530 in the polysilicon film. It is formed by forming. The second polysilicon film 528 fills the recess 520 to an appropriate height and becomes the gate of the vertical transistor. This second
The gate oxide film 526 is exposed between the polysilicon film 528 and the substrate surface 500a. This second polysilicon film 5
28 is isolated from the substrate 500 by the gate oxide film 526, and is insulated from the first polysilicon film 518 by the oxide film 518b.

Thereafter, as shown in FIGS. 4 and 7B,
By selectively forming the surface side of the substrate 500 as the isolation structure 532, the two trench capacitors 400a and 400
b and the active region 402 of the two vertical transistors. At this time, an opening is formed in the isolation structure 532 by defining the hard mask film 504, the second polysilicon film 528, the oxide film 518b, the first polysilicon film 518, and the like by, for example, photolithography and etching. Is filled with an insulating material such as a silicon dioxide film, and then the insulating material is polished with the hard mask film 504 as a polishing end point. Due to this isolation structure 532, only the source 522 formed on the substrate portion inside the pair of left and right trenches remains. After that, the hard mask film 504
And the pad oxide film 502 is removed.

Thereafter, after forming a sacrificial oxide film (not shown) on the substrate surface 500a, impurity ions are
Implant at 0 to form a well. Then, FIG.
As shown in FIG. 7, a drain 534 is formed on the surface of the substrate adjacent to the gate oxide film 526 above the second polysilicon film 528 by ion implantation or the like. This drain 534 is formed on the substrate surface between the pair of trenches,
Common drain region shared by two trench capacitors and two vertical transistors
It is. Subsequently, after removing the sacrificial oxide film, the substrate 500
Is subjected to a thermal oxidation process to form a gate oxide film 536 on the substrate surface 500a. Subsequently, a word line 404 is formed on the isolation structure 532 in parallel with the common drain 534. The word line 404 is connected to the isolation structure 53 first, for example.
Polysilicon film / tungsten silicide film 5 on 2
38, a silicon nitride film 540 is formed thereon, these polysilicon film / tungsten silicide film 538 and silicon nitride film 540 are defined, and then these polysilicon film / tungsten silicide film / silicon nitride film 538 are formed. , 540 on the side walls
Is produced by forming This word line 40
Reference numeral 4 denotes a direction parallel to the common drain 534 and located directly above the trench capacitors 400a and 400b. At this time, the isolation structure 532 is connected to the word line 404 and the second gate.
It is isolated from the polysilicon film 528.

Thereafter, an insulating film 544 such as boron-phosphosilicate glass (BPSG) is formed on the entire surface of the substrate 500 (FIG. 8).
(Shown in (b)) to cover the word line 404, the isolation structure 532, the substrate surface 500a, and the like. Thereafter, the word line 404 is exposed by flattening the insulating film 544 as shown in FIG. 8B using the chemical mechanical polishing method with the silicon nitride film 540 as a polishing end point. Since the word line 404 and the second polysilicon film (hereinafter referred to as a gate) 528 are not electrically connected, the step of forming a gate contact window 546 is advanced, and the word line 40
4 and the gate 528 are electrically connected. This gate contact window 5
First, a part of the word line 404 and the isolation structure 5 above the gate 528 are formed by photolithographic etching.
32 is defined to form a contact window opening of sufficient depth to expose gate 528. Thereafter, the opening is filled with a conductive material such as polysilicon to complete the gate contact window 546. At this time, the gate contact window 546 does not contact the first polysilicon film 518. That is,
The contact (short) between the word line 404 and the source 522 is prevented. When the gate contact window 546 is formed in this manner, opening and closing of the channel can be controlled by applying a voltage from the word line 404 to the gate. As shown in FIG. 4, if the gate contact windows 546 adjacent to the two different active regions 402 are shifted from each other in the front-rear direction, a short circuit between the gate contact windows 546 can be prevented, and the layout area can be reduced. it can.

Next, as shown in FIG. 9A, an insulating film 548 such as a TEOS oxide film is formed on the entire surface of the word line 404 and the insulating film 544, and the insulating film 544, the gate contact window 546, The word line 404 and the like are covered. Subsequently, as shown in FIG. 9B, an opening is formed by defining a gate oxide film 536 and insulating films 544 and 548 on the common drain 534 by using a photolithography and etching process. Substrate surface 50
0a is exposed. Thereafter, the opening is filled with a conductive material such as polysilicon to form a bit line contact window 550 as shown in FIG. 9B, and at the same time, a bit line 406 vertically arranged with the word line 404 on the insulating film 548. To form
Bit line 406 is conductively connected to common drain 534 at bit line contact window 550.

According to the present invention, as shown in FIG. 4, horizontal transistors of a DRAM are replaced with vertical transistors.
Ensure that the width of the word line 404 is not an important factor in determining the channel length of the DRAM transistor. As can be seen from the layout of FIG. 4, word line 404 is connected to the gate of each vertical transistor by a gate contact window 546. Therefore, each word line 404 drives each storage unit (active area 402) in cooperation with the vertical transistor to advance the read / write operation. All word lines 404
Are active word lines, each word line 404 can drive twice as many memory units as the prior art. Further, since the area of the memory unit is 1 word line width × 1 bit line width, a lot of layout space can be saved.

In a preferred embodiment of the present invention, DR
AM is a combination of trench capacitors 400a and 400b and a vertical transistor. An upper electrode 514a of the trench capacitors 400a and 400b is formed in the trench of the substrate 500, a capacitor dielectric film 510 surrounds the periphery of the upper electrode 514a, and a storage electrode 508 surrounds the capacitor dielectric film 510. The gate 528 is connected to the substrate 500
And is insulated from the upper electrode 514a by an oxide film (insulating film) 518b.
22 is provided on the substrate 500 on the trench sidewall between the gate 528 and the upper electrode 514a. The source 522 includes the upper electrode 514
is electrically connected to the upper electrode 514a through the first polysilicon film 518 and the conductive film 515 on the upper electrode a. Further, a common drain 534 is formed on the surface of the substrate above the gate 528. The DRAM further includes a word line 404 and a bit line 406. The word line 404 is connected to the common drain 53
4 is formed on the isolation structure 532 on the substrate surface in a direction parallel to 4 and is conductively connected to the gate 528 at the gate contact window 546. The bit lines 406 are arranged on the insulating film 548 on the substrate 500 so as to be arranged in a direction perpendicular to the word lines 404, are insulated from the word lines 404, and are electrically connected to the common drain 534 through the bit line contact windows 550.

As described above, the present invention has been disclosed by the preferred embodiments, but the above embodiments do not limit the present invention. As can be easily understood by those skilled in the art, the contents of the present invention can be appropriately changed and modified within the scope of the technical idea of the present invention. Therefore, the scope of patent protection of the present invention must be determined based on the claims and equivalents thereof.

[0027]

As described in detail above, according to the present invention, a DRAM is formed by combining a trench capacitor and a vertical transistor, and the conventional transistor is occupied by providing the vertical transistor above the trench capacitor. Memory area can be saved. Moreover, the layout in which the two trench capacitors share the drain makes it possible to reduce the area of the memory cell active region and greatly increase the degree of integration of the memory unit. Therefore, the industrial use value is high.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a memory unit of a DRAM.

FIG. 2 is a layout diagram of a conventional DRAM having a trench capacitor.

FIG. 3 is a sectional view taken along the line III-III in FIG. 2;

FIG. 4 is a layout diagram showing an embodiment of a DRAM according to the present invention.

5 is a view showing the embodiment of the method for manufacturing the DRAM according to the present invention, and is a cross-sectional view taken along the line IV-IV of FIG. 4;

FIG. 6 is a view showing the embodiment of the method of manufacturing the DRAM according to the present invention, and is a cross-sectional view taken along the line IV-IV of FIG. 4;

FIG. 7 is a view showing the embodiment of the method of manufacturing the DRAM according to the present invention, and is a cross-sectional view taken along the line IV-IV of FIG. 4;

8 is a view showing an embodiment of a method of manufacturing a DRAM according to the present invention, and is a cross-sectional view taken along the line IV-IV of FIG. 4;

9 is a diagram showing an embodiment of a method for manufacturing a DRAM according to the present invention, and is a cross-sectional view taken along the line IV-IV of FIG. 4;

[Explanation of symbols]

 522 Source 400a Trench capacitor 400b Trench capacitor 404 Word line 406 Bit line 508 Storage electrode 500 Substrate 510 Capacitor dielectric film 512 Color insulating film 514a Upper electrode 515 Conductive film 518 First polysilicon film 518b Oxide film 526,536 Gate oxide film 528 Second polysilicon film 532 Isolation structure 534 Common drain 544, 548 Insulating film 546 Gate contact window 550 Bit line contact window

Continuing on the front page (72) Inventor Xiao Jianjun, No. 50, No. 95, 213, 213, Crim Forest Cove, Xiangshan District, Hsinchu, Taiwan (72) Inventor Wu Zhaolu 8F, 439 Street, Lishan Mountain, Lishan, Xinpu Town, Hsinchu County, Taiwan -1 F term (reference) 5F083 AD04 AD17 AD60 GA09 JA35 JA39 JA53 KA01 KA05

Claims (20)

[Claims] A step of forming a trench in the substrate; a step of forming a trench capacitor deep enough in the trench and including a storage electrode, a capacitor dielectric film, and an upper electrode; Forming a first polysilicon film by conducting connection, forming a doping region as a source of a vertical transistor on a side wall of the substrate adjacent to the first polysilicon film; insulating the first polysilicon film in the trench with the first polysilicon film; do it,
Forming a second polysilicon film as a gate insulated from a substrate sidewall by a gate oxide film; and forming a common drain of a vertical transistor by doping in a substrate surface portion above the second polysilicon film. Forming a word line on the substrate in a direction parallel to the common drain and on the trench capacitor, and electrically connecting the second polysilicon film with a gate contact window; and forming a bit line on the substrate. In the direction perpendicular to the word line, and electrically connected to the common drain through a bit line contact window. 2. After filling the trench with a polysilicon film, a first recess is formed in the polysilicon film to form the upper electrode, and a polysilicon film is formed in the first recess. Forming the first polysilicon film by forming a second recess in the polysilicon film; forming an insulating film on the first polysilicon film; and then forming a polysilicon film on the insulating film. 2. The method according to claim 1, wherein the second polysilicon film is formed by forming the second polysilicon film. 3. The word line according to claim 2, wherein the word line is separated by an isolation structure.
The gate contact window is formed by insulating a polysilicon film, forming a contact window opening having a sufficient depth in the isolation structure, and filling the contact window opening with a polysilicon film. Item 2. A method for manufacturing a DRAM according to Item 1. Providing a substrate having a trench, forming a doping region in the substrate at the bottom of the trench to form a storage electrode of the trench capacitor, and forming a capacitor on a sidewall surface of the trench of the storage electrode. Forming a dielectric film, forming a conductive film in the trench, and forming an upper electrode covered with the capacitor dielectric film; and forming a substrate on the upper electrode by a surrounding color insulating film. Forming a conductive film insulated from the side wall; forming a first polysilicon film on the conductive film;
Forming a first doping region on the substrate at the trench sidewall portion in contact with the polysilicon film; forming an insulating film on the first polysilicon film; and forming a gate oxide film on the exposed trench sidewall above the first polysilicon film. Forming a second polysilicon film on the insulating film; and selectively transforming the substrate surface side into an isolation structure to form an active region including two trench capacitors and two vertical transistors. Defining, forming a common drain of the two vertical transistors by doping a substrate surface portion of the active region; forming a word line on the isolation structure; 1) forming an insulating film, forming a gate contact window in the isolation structure, and conducting a word line with the second polysilicon film through the gate contact window. And forming a bit line and a bit line contact window after covering the entire surface of the substrate with a second insulating film, and contacting the bit line with the common drain.
Manufacturing method of RAM. 5. The trench is formed such that a pad oxide film and a hard mask film are sequentially formed on the substrate, and the pad oxide film and the hard mask film are defined by a photolithography etching method. The method according to claim 4, wherein the substrate is formed by etching the substrate. 6. The method according to claim 5, further comprising removing the hard mask film and the pad oxide film after forming the isolation structure. 7. In the conductive film, after forming a collar insulating film on the side wall of the trench, a polysilicon film material is formed on the upper electrode, and the polysilicon film material is etched into the trench to a predetermined depth. 5. The method for manufacturing a DRAM according to claim 4, wherein said method is formed by: 8. The first polysilicon film is formed by forming a polysilicon film on the conductive film and then forming a recess in the polysilicon film that is shallower than an etching depth of the conductive film. 8. The method of manufacturing a DRAM according to claim 7, wherein: 9. The second polysilicon film, comprising: forming a polysilicon film on an insulating film on the first polysilicon film;
9. The method according to claim 8, wherein the polysilicon film is formed by forming a second recess having a depth shallower than the recess. 10. The first doping region includes the first doping region.
5. The method according to claim 4, wherein the substrate is formed by implanting ions into a polysilicon film and diffusing ions into the substrate in a heat treatment step. 11. The insulating film according to claim 4, wherein the first polysilicon film is oxidized in a state where a cover film is formed on the exposed side wall of the trench, thereby forming the insulating film thereon. DRAM manufacturing method. 12. The method according to claim 1, further comprising removing the cover film after forming the insulating film.
2. The method for manufacturing a DRAM according to 1. 13. The method of manufacturing a DRAM according to claim 4, wherein prior to forming the gate oxide film, ion implantation is performed on a side wall of the substrate at a portion where the gate oxide film is formed to form a channel of a vertical transistor. 14. The method according to claim 4, wherein an opening is first defined by a photolithographic etching method, and the isolation structure is formed by filling the opening with an insulating material. . 15. The gate contact window is defined by defining an opening on the word line and in the isolation structure, exposing the second polysilicon film in the opening, and filling the opening with a polysilicon film. The method for manufacturing a DRAM according to claim 4, wherein the DRAM is formed. 16. The bit line contact window is formed by forming an opening in the first insulating film and the second insulating film to expose the common drain and filling the opening with a polysilicon film. 5. The method for manufacturing a DRAM according to claim 4, wherein: 17. A step of preparing a substrate, forming a trench by defining the substrate with a hard mask film, forming a doping region in the substrate at the bottom of the trench, and forming a storage electrode of a trench capacitor. Forming a capacitor dielectric film on the trench sidewall of the storage electrode; forming an upper electrode of a trench capacitor in a trench inside the capacitor dielectric film; and further forming a collar insulating film thereon. Forming a conductive film insulated from the substrate; forming a first polysilicon film on the conductive film; forming a first doping region in a substrate portion of the trench sidewall in contact with the first polysilicon film. Forming as a source of a vertical transistor; forming a cover film on the trench sidewall above the first polysilicon film; Exposing the top surface of the polysilicon film; oxidizing the first polysilicon film to form an oxide film on the top surface of the first polysilicon film; removing the cover film; Exposing the upper trench sidewall; forming a gate oxide film on the trench sidewall above the oxide film; forming a second polysilicon film in the trench inside the gate oxide film; Forming an opening on the front side of the substrate and filling the opening with an insulating material to form an isolation structure defining an active region including two transistors corresponding to the two trench capacitors. Removing the hard mask film; forming a second doping region on the substrate surface of the active region; forming a common drain of the two vertical transistors Forming a word line on the isolation structure; forming a first insulating film on a surface of the substrate; forming a gate contact window in the isolation structure; Forming a word line and a bit line contact window after the entire surface on the substrate is covered with a second insulating film, and contacting the bit line with the common drain; D.
Manufacturing method of RAM. 18. After implanting ions into the first polysilicon film, performing a heat treatment process on the first polysilicon film to advance ion diffusion from the first polysilicon film to the adjacent substrate. 18. The DR according to claim 17, wherein the first doping region is formed by:
Manufacturing method of AM. 19. The method according to claim 17, wherein the cover film is not formed on the first polysilicon film. 20. A semiconductor device comprising a trench capacitor, a vertical transistor, a word line and a bit line, wherein the trench capacitor includes an upper electrode formed in a trench of the substrate, a capacitor dielectric film surrounding a periphery of the upper electrode, A storage transistor surrounding the capacitor dielectric film, wherein the vertical transistor is formed in the trench and is insulated from the upper electrode by an insulating film, and formed on the substrate between the gate and the upper electrode. A source electrically connected to the upper electrode; and a common drain formed on the surface of the substrate above the gate. The word line is disposed in a direction parallel to the common drain to isolate the surface of the substrate. A bit line is formed on the structure, is electrically connected to the gate by a gate contact window, and is formed on an insulating film covering a substrate. DRAM, characterized in that arranged in the direction of the word line and the vertical, is electrically connected to the common drain by a bit line contact window.