CN114121821A

CN114121821A - Method for forming dynamic random access memory

Info

Publication number: CN114121821A
Application number: CN202210009719.6A
Authority: CN
Inventors: 华文宇; 刘藩东; 崔胜奇; 汪亚
Original assignee: ICLeague Technology Co Ltd
Current assignee: ICLeague Technology Co Ltd
Priority date: 2022-01-05
Filing date: 2022-01-05
Publication date: 2022-03-01

Abstract

A method for forming a dynamic random access memory comprises the following steps: providing a substrate, wherein the substrate is provided with a first surface and a second surface, the substrate comprises a plurality of active regions which are mutually separated and parallel to a first direction, the active regions are arranged along a second direction, and each active region comprises a plurality of channel regions and word line regions positioned between adjacent channel regions; forming a word line gate structure in the word line region; forming a first isolation trench in the channel region; forming an adjusting structure on the inner wall surface of the first isolation trench, wherein the adjusting structure comprises a first area and a second area positioned on the first area, and the thickness of the second area is greater than that of the first area; and forming a covering layer to seal the top of the first isolation groove and form a cavity in the first isolation groove. The notch size of the first isolation groove is reduced, so that the process difficulty of sealing the first isolation groove to form a cavity is effectively reduced. And the difference of the sealing time is reduced, the uniformity among all formed cavities is improved, and the performance of the device structure is further improved.

Description

Method for forming dynamic random access memory

Technical Field

The invention relates to the technical field of semiconductor manufacturing, in particular to a forming method of a dynamic random access memory.

Background

With the rapid development of technology, semiconductor memories are widely used in electronic devices. Dynamic Random Access Memory (DRAM), which is a volatile memory, is the most commonly utilized solution for applications that store large amounts of data.

Generally, a dram is composed of a plurality of memory cells, each of which is mainly composed of a transistor and a capacitor operated by the transistor, and each of the memory cells is electrically connected to each other through a word line and a bit line.

However, the conventional dynamic random access memory still has many problems.

Disclosure of Invention

The invention aims to provide a method for forming a dynamic random access memory, which can effectively reduce the process difficulty and improve the performance of a device.

To solve the above problems, the present invention provides a method for forming a dynamic random access memory, comprising: providing a substrate, wherein the substrate is provided with a first surface and a second surface which are opposite, the substrate comprises a plurality of active regions which are separated from each other and parallel to a first direction, the active regions are arranged along a second direction, the first direction is different from the second direction, each active region comprises a plurality of channel regions and word line regions positioned between adjacent channel regions, and the word line regions in the adjacent active regions are arranged along the second direction; forming word line grating structures in the word line area, wherein each word line grating structure is parallel to the second direction and is arranged along the first direction, and each word line grating structure penetrates through a plurality of active areas; etching part of the channel region from the first surface to the second surface, and forming a first isolation groove in the channel region; forming an adjusting structure on the inner wall surface of the first isolation trench, wherein the adjusting structure comprises a first area and a second area, the distance from the second area to the first surface is less than the distance from the first area to the first surface, and the thickness of the second area is greater than that of the first area; and forming a covering layer to seal the top of the first isolation groove, and forming a cavity in the first isolation groove.

Optionally, the adjusting structure includes: the protective layer is positioned on the side walls of the first area and the second area, and the adjusting layer is positioned on the side wall of the second area.

Optionally, the method for forming the adjustment structure on the inner wall surface of the first isolation trench includes: forming a protective layer on the side wall and the bottom surface of the first isolation trench; forming a sacrificial layer in the first isolation groove, wherein the sacrificial layer is located on the protection layer, and the top surface of the sacrificial layer is lower than the first surface; after the sacrificial layer is formed, forming a regulating layer on the exposed side wall of the first isolation trench, wherein the protective layer and the regulating layer form a regulating structure; after forming the adjustment structure, removing the sacrificial layer.

Optionally, the material of the protective layer includes: silicon oxide; the material of the regulating layer comprises: silicon oxide.

Optionally, the material of the sacrificial layer is different from the material of the protective layer and the material of the adjusting layer; the material of the sacrificial layer comprises: carbon; the process for removing the sacrificial layer comprises the following steps: and (5) ashing.

Optionally, the method for forming the word line grid structure in the word line region includes: forming a word line gate trench in each word line region, wherein the word line gate trench extends from the first surface to the second surface and penetrates through the active region along the second direction; and forming the word line gate structure in each word line gate groove.

Optionally, in the process of forming the word line gate structure, the method further includes: and forming an isolation structure in the word line gate trench.

Optionally, the method for forming the word line gate structure and the isolation structure in each word line gate trench includes: forming an initial word line gate structure in each word line gate groove; etching part of the initial word line gate structure from the first face to the second face, forming a plurality of second isolation grooves parallel to the second direction in the substrate, wherein the second isolation grooves penetrate through the initial word line gate structure from the first face to the second face, and enabling the initial word line gate structure to form two mutually-separated word line gate structures; and forming the isolation structure in the second isolation groove.

Optionally, a distance between the isolation structure and the second surface is smaller than or equal to a distance between the word line grid structure and the second surface.

Optionally, before forming the word line gate trench, the method further includes: and forming an isolation layer between adjacent active regions.

Optionally, the forming method of the isolation layer includes: forming a layer of isolation material between adjacent ones of the active regions and on the first face; and carrying out planarization treatment on the isolation material layer until the first surface is exposed to form the isolation layer.

Optionally, after forming the word line gate trench and before forming the initial word line gate structure, the method further includes: forming a flat layer at the bottom of the word line gate groove; the word line gate structure is located on the flat layer.

Optionally, the method for forming the planarization layer at the bottom of the word line gate trench includes: forming a flat material layer at the bottom of the word line gate groove by adopting a spin coating process, wherein the flat material layer is fluid; and carrying out curing treatment on the flat material layer to form the flat layer.

Optionally, the material of the planarization layer includes an insulating dielectric material; the insulating dielectric material comprises: silicon oxide or silicon nitride.

Optionally, after forming the cavity in the first isolation trench, the method further includes: forming a first source drain doped region in the first surface of each channel region; thinning the substrate from the second surface to the first surface; and forming a second source-drain doped region in the second surface of each channel region after the thinning treatment.

Optionally, after forming the cavity in the first isolation trench, the method further includes: forming a plurality of capacitor structures on the first surface, wherein each capacitor structure is electrically connected with one first source drain doped region; and forming a plurality of bit line layers parallel to the first direction on the second surface, wherein each bit line layer is electrically connected with a plurality of second source-drain doped regions in one active region.

Optionally, after forming the cavity in the first isolation trench, the method further includes: forming a plurality of bit line layers parallel to the first direction on the first surface, wherein each bit line layer is electrically connected with a plurality of first source-drain doped regions in one active region; and forming a plurality of capacitor structures on the second surface, wherein each capacitor structure is electrically connected with one second source drain doped region.

Optionally, the depth of the second source-drain doped region is greater than or equal to the distance between the word line grid structure and the second surface of the substrate.

Optionally, before forming the plurality of capacitor structures, the method further includes: and forming a first conductive plug on each first source-drain doped region, wherein each capacitor structure is electrically connected with one first conductive plug.

Optionally, before forming the plurality of capacitor structures, the method further includes: and forming a first conductive plug on each second source-drain doped region, wherein each capacitor structure is electrically connected with one first conductive plug.

Optionally, before forming a plurality of bit line layers, the method further includes: and forming a plurality of second conductive plugs, wherein the second conductive plugs are used for electrically connecting each bit line layer with the second source-drain doped regions in the corresponding active region respectively.

Optionally, before forming a plurality of bit line layers, the method further includes: and forming a plurality of second conductive plugs, wherein the second conductive plugs are used for electrically connecting each bit line layer with the first source-drain doped regions in the corresponding active region respectively.

Optionally, the word line gate structure includes: the word line gate dielectric layer is positioned on the side wall and the bottom surface of the word line gate groove, and the word line gate layer is positioned on the word line gate dielectric layer.

Optionally, the word line gate layer includes: a single layer structure or a composite structure.

Optionally, when the word line gate layer is of a single-layer structure, the material of the word line gate layer includes: metal or polysilicon.

Optionally, when the word line gate layer is of a composite structure, the word line gate layer includes a first gate layer and a second gate layer located on the first gate layer, and the first gate layer and the second gate layer are made of different materials.

Optionally, the material of the first gate layer includes: metal or polysilicon; the material of the second gate layer comprises: polysilicon or metal.

Compared with the prior art, the technical scheme of the invention has the following advantages:

in the forming method of the technical scheme of the invention, an adjusting structure is formed on the surface of the inner wall of the first isolation trench, the adjusting structure comprises a first area and a second area, the distance from the second area to the first surface is less than the distance from the first area to the first surface, and the thickness of the second area is greater than that of the first area. By reducing the size of the notch of the first isolation groove, the process difficulty of sealing the first isolation groove to form a cavity is effectively reduced. And the difference of the sealing time is reduced, the uniformity among the formed cavities is improved, and the performance of the device structure is further improved.

Further, after forming the word line gate trench and before forming the initial word line gate structure, the method further includes: forming a flat layer at the bottom of the word line gate groove; the word line gate structure is located on the flat layer. By forming the flat layer at the bottom of the word line gate groove, the controllability of a subsequent process technology can be effectively improved, and the stability and reliability of a finally formed device structure can be effectively improved.

Drawings

FIGS. 1-2 are schematic structural diagrams of steps of a method for forming a DRAM;

fig. 3 to fig. 21 are schematic structural diagrams of steps of a method for forming a dynamic random access memory according to an embodiment of the invention.

Detailed Description

As described in the background, problems still exist with existing dynamic random access memories. The following detailed description will be made in conjunction with the accompanying drawings.

Fig. 1 to 2 are schematic structural diagrams of steps of a method for forming a dynamic random access memory.

Referring to fig. 1, a substrate 100 is provided, the substrate 100 has a first side 101 and a second side 102 opposite to each other, the substrate 100 includes a plurality of active regions 113 separated from each other and parallel to a first direction, and a plurality of the active regions 113 are arranged along a second direction, the first direction is perpendicular to the second direction, each of the active regions 113 includes a plurality of word line regions 103 and a plurality of channel regions 104, and a plurality of the word line regions 103 and a plurality of the channel regions 104 in each of the active regions 113 are arranged at intervals along the first direction; forming a word line gate trench (not labeled) in each of the word line regions 103, the word line gate trench extending from the first surface 101 to the second surface 102, and the word line gate trench penetrating the active region along the second direction; forming an initial word line gate structure (not shown) in each of the word line gate trenches; etching a part of the initial word line gate structure from the first surface 101 to the second surface 102, forming a plurality of first isolation trenches (not labeled) parallel to the second direction in the substrate 100, wherein the first isolation trenches penetrate through the initial word line gate structure from the first surface 101 to the second surface 102, and enabling the initial word line gate structure to form two word line gate structures 105 which are separated from each other; a first isolation structure 106 is formed within the first isolation trench.

Referring to fig. 2, etching a portion of the channel region 103 from the first surface 101 to the second surface 102, and forming a plurality of second isolation trenches (not labeled) parallel to the second direction in the substrate 100; forming a covering layer 107 to close the top of the second isolation trench to form a cavity 112; forming a first source-drain doped region 108 in the first surface 101 of each channel region 103; forming a plurality of capacitor structures 109 on the first surface 101, wherein each capacitor structure 109 is electrically connected with one first source-drain doped region 108; thinning the substrate 100 from the second surface 102 to the first surface 101; forming a second source-drain doped region 110 in the second surface 102 of each channel region 103; a plurality of bit line layers 111 parallel to the first direction are formed on the second surface 102, and each bit line layer 111 is electrically connected to a plurality of second source-drain doped regions 110 in one of the active regions 113.

In the present embodiment, the covering layer 107 is formed to close the top of the second isolation trench to form the cavity 112, and the cavity 112 has a better isolation effect. In addition, the dielectric constant within the cavity 112 is less than that of conventional isolation materials. Therefore, the formation of the cavity 112 can effectively reduce the parasitic capacitance formed between adjacent word line gate structures 105.

The prior art deposits the dielectric material of the capping layer directly to seal the notches of the second isolation trenches. However, the notch of the second isolation trench is large, so that the process difficulty of sealing is increased. In addition, because the time for sealing each of the second isolation trenches is different, the difference in time affects the amount of material entering the second isolation trenches, and thus affects the uniformity of the formed cavity 112, and thus the performance of the device structure.

On the basis, the invention provides a method for forming a dynamic random access memory, which effectively reduces the process difficulty of sealing the first isolation groove to form a cavity by reducing the size of the notch of the first isolation groove. And the difference of the sealing time is reduced, the uniformity among the formed cavities is improved, and the performance of the device structure is further improved.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

Referring to fig. 3 to 5, fig. 4 is a schematic cross-sectional view taken along line a-a in fig. 3, fig. 5 is a schematic cross-sectional view taken along line B-B in fig. 3, a substrate 200 is provided, the substrate 200 has a first surface 201 and a second surface 202 opposite to each other, the substrate 200 includes a plurality of active regions 203 separated from each other and parallel to a first direction X, and a plurality of the active regions 203 are arranged along a second direction Y, the first direction X is different from the second direction Y, each of the active regions 203 includes a plurality of channel regions 205 and word line regions 204 located between adjacent channel regions 205, and the word line regions 204 in adjacent active regions 203 are arranged along the second direction Y.

In this embodiment, the substrate 200 is made of silicon; in other embodiments, the substrate may also be germanium, silicon carbide, gallium arsenide, or indium gallium.

In the present embodiment, the channel region 205 and the word line region 204 are used to subsequently form transistor devices.

Referring to fig. 6, the views of fig. 6 and fig. 4 are in the same direction, and an isolation layer 206 is formed between adjacent active regions 203.

In this embodiment, the method for forming the isolation layer 206 includes: forming an initial isolation layer (not shown) between adjacent active regions 203 and on the first side 201; the initial isolation layer is planarized until the first side 201 is exposed, forming the isolation layer 206.

In this embodiment, the material of the isolation layer 206 is silicon oxide.

In this embodiment, after forming the isolation layer 206, the method further includes: word line grid structures are formed in the word line region 204, each word line grid structure is parallel to the second direction Y and is arranged along the first direction X, and each word line grid structure penetrates through a plurality of active regions 203. Please refer to fig. 7 to fig. 10 for a specific process of forming the word line gate structure.

Referring to fig. 7, a word line gate trench 207 is formed in each of the word line regions 204, the word line gate trench 207 extends from the first surface 201 to the second surface 202, and the word line gate trench 207 penetrates the active region 203 along the second direction Y.

In this embodiment, the word line gate trench 207 provides a space for a word line gate structure to be formed in the word line gate trench 207 subsequently.

In this embodiment, the method for forming the word line gate trench 207 includes: forming a first patterned layer (not shown) on the first side 201 of the substrate 200, the first patterned layer exposing the word line region 204; and etching from the first surface 201 to the second surface 202 by using the first patterning layer as a mask through an etching process to form the word line gate trench 207.

In the present embodiment, the depth of the word line gate trench 207 is smaller than the depth of the isolation layer 206. In other embodiments, the depth of the word line gate trench may also be equal to the depth of the isolation layer.

In this embodiment, during the process of forming the word line gate trench 207, the isolation layer 206 and the word line region 204 need to be etched simultaneously. Since the isolation layer 206 and the word line region 204 are made of different materials, in the etching process, the etching rates of the isolation layer 206 and the word line region 204 are different, which easily causes the bottom of the finally formed word line gate trench 207 to have an uneven problem, thereby easily affecting the controllability of the subsequent process and the stability and reliability of the finally formed device structure.

In the present embodiment, with continued reference to fig. 7, a planarization layer 208 is formed at the bottom of the word line gate trench 207.

In this embodiment, the method for forming the planarization layer 208 at the bottom of the word line gate trench 207 includes: forming a flat material layer (not shown) at the bottom of the word line gate trench 207 by using a spin coating process, wherein the flat material layer is a fluid; and performing a curing process on the flat material layer to form the flat layer 208.

In the present embodiment, the material of the planarization layer 208 includes an insulating dielectric material; the insulating medium material adopts silicon oxide. In other embodiments, the insulating dielectric material may also be silicon nitride.

By forming the planarization layer 208 at the bottom of the word line gate trench 207, the controllability of the subsequent process can be effectively improved, and the stability and reliability of the finally formed device structure can be effectively improved.

In other embodiments, when the flatness of the bottom of the word line gate trench is high, the planarization layer may not be formed.

Referring to fig. 8 and 9, fig. 9 is a schematic cross-sectional view taken along line C-C of fig. 8, wherein an initial word line gate structure 209 is formed in each of the word line gate trenches 207.

In this embodiment, the initial word line gate structure 209 includes: an initial wordline gate dielectric layer located on the sidewalls and bottom surface of the wordline gate trench 207, and an initial wordline gate layer (not labeled) located on the initial wordline gate dielectric layer.

With continuing reference to fig. 9, in the present embodiment, the initial word line gate structure 209 is not filled in the word line gate trench 107, and after the initial word line gate structure 209 is formed, the method further includes: a dielectric layer 210 is formed on the first surface 201 of the substrate 200, the word line gate trench 207 is filled with the dielectric layer 210, and the surface of the channel region 205 is exposed by the dielectric layer 210.

Referring to fig. 10, the view directions of fig. 10 and fig. 9 are the same, a portion of the initial word line gate structure 209 is etched from the first surface 201 to the second surface 202, a plurality of second isolation trenches 211 parallel to the second direction Y are formed in the substrate 200, the second isolation trenches 211 penetrate through the initial word line gate structure 209 from the first surface 201 to the second surface 202, and the initial word line gate structure 209 forms two word line gate structures 212 separated from each other.

In this embodiment, the word line gate structure 212 is formed by first forming an initial word line gate structure 209, and then dividing the initial word line gate structure 209 into two word line gate structures 212 separated from each other by forming the second isolation trench 211. Since the pattern size of the single word line gate structure 212 is small, the space between adjacent word line gate structures 212 is also small, and the corresponding exposure process is difficult. By forming the initial word line grid structure 209 with a larger pattern size and a larger adjacent spacing, the difficulty of the exposure process can be effectively reduced.

In this embodiment, the word line gate structure 212 includes: a word line gate dielectric layer on the sidewall and bottom surfaces of the word line gate trench 207, and a word line gate layer (not labeled) on the word line gate dielectric layer.

In this embodiment, the word line gate layer has a composite structure, and includes a first gate layer and a second gate layer (not shown) on the first gate layer, where the first gate layer and the second gate layer are made of different materials.

In this embodiment, the first gate layer is made of polysilicon, and the second gate layer is made of metal; in other embodiments, the material of the first gate layer may also be a metal, and the material of the corresponding second gate layer may also be polysilicon.

In other embodiments, the word line gate layer may also adopt a single-layer structure, and when the word line gate layer adopts a single-layer structure, the material of the word line gate layer may adopt polysilicon or metal.

In this embodiment, the word line gate structure 212 is located on the planarization layer 208.

Referring to fig. 11, the isolation structure 213 is formed in the second isolation trench 211.

In this embodiment, the method for forming the isolation structure 213 includes: forming a layer of isolation material (not shown) within the second isolation trench 211 and on the first side 201; the isolation material layer is planarized until the first surface 201 is exposed, thereby forming the isolation structure 213.

In this embodiment, the isolation structure 213 is used to connect only one side of the word line gate structure 212 to the channel region 205, so that the transistor is a single-side channel structure. The dynamic random access memory with the unilateral channel structure is not easy to generate the leakage current problem during working.

In this embodiment, the isolation structure 213 is made of silicon oxide.

In the present embodiment, the spacing between the isolation structure 213 and the second surface 202 is smaller than the spacing between the word line gate structure 212 and the second surface 202. The isolation structures 213 can completely separate the two word line gate structures 212 in the word line gate trench 207, thereby effectively preventing the two word line gate structures 212 from being shorted.

In other embodiments, a spacing between the isolation structure and the second side may also be equal to a spacing between the word line gate structure and the second side.

Referring to fig. 12, a portion of the channel region 205 is etched from the first surface 201 toward the second surface 202, and a first isolation trench 214 is formed in the channel region 205.

In this embodiment, the method for forming the first isolation trench 214 includes: forming a second patterned layer (not shown) on the first side 201 of the substrate 200, the second patterned layer exposing a portion of the top surface of the channel region 205; and etching from the first surface 201 to the second surface 202 by using the second patterning layer as a mask through an etching process to form the first isolation trench 214.

In this embodiment, after forming the first isolation trench 214, the method further includes: an adjustment structure is formed on the inner wall surface of the first isolation trench 214, the adjustment structure includes a first region and a second region, the distance from the second region to the first surface is less than the distance from the first region to the first surface 201, and the thickness of the second region is greater than the thickness of the first region. Please refer to fig. 13 to fig. 15 for a specific forming process of the adjustment structure.

Referring to fig. 13, a protection layer 215 is formed on the sidewall and bottom surface of the first isolation trench 214.

In this embodiment, the protection layer 215 is further formed on the bottom surface of the first isolation trench 214 and the first surface 201.

In the present embodiment, the forming process of the protection layer 215 adopts an atomic layer deposition process.

In this embodiment, the material of the protection layer 215 is silicon oxide. The protective layer 215 functions to: on one hand, the sidewalls of the first isolation trenches 214 can be protected, so that the sidewalls of the first isolation trenches 214 are prevented from being oxidized in a subsequent heat treatment process, and the thickness of the channel is reduced; on the other hand, when thinning is performed on the first surface 201 from the second surface 202, the protection layer 215 is exposed, and the formed cavity is exposed after thinning.

Referring to fig. 14, a sacrificial layer 216 is formed in the first isolation trench 214, the sacrificial layer 216 is located on the protection layer 215, and a top surface of the sacrificial layer 216 is lower than the first surface 201.

In this embodiment, the method for forming the sacrificial layer 216 includes: forming a sacrificial material layer (not shown) within the first isolation trench 214 and on the first side 201; planarizing the sacrificial material layer until the surface of the protection layer 215 is exposed, forming an initial sacrificial layer (not shown); and performing back etching treatment on the initial sacrificial layer to form the sacrificial layer 216.

In the present embodiment, the material of the sacrificial layer 216 is different from the material of the protective layer 215 and the subsequently formed adjustment layer.

In this embodiment, the material of the sacrificial layer 216 is carbon. The material of the sacrificial layer 216 is selected from carbon, so that the subsequent removal is facilitated.

Referring to fig. 15, after the sacrificial layer 216 is formed, an adjustment layer 217 is formed on the exposed sidewall of the first isolation trench 214, and the adjustment structure is formed by the protection layer 215 and the adjustment layer 217.

In this embodiment, the method for forming the adjustment layer 217 includes: forming an initial adjustment layer (not shown) on exposed sidewalls of the first isolation trench 214 and the first side 201; the initial adjustment layer and the protection layer 215 are planarized until the first side 201 is exposed, forming the adjustment layer 217.

In this embodiment, the adjusting structure includes a first region I and a second region II, a distance from the second region II to the first surface 201 is smaller than a distance from the first region I to the first surface 201, and a thickness of the second region II is larger than a thickness of the first region I.

The thickness direction is along the first direction X.

In this embodiment, the material of the adjustment layer 217 is silicon oxide.

With continuing reference to fig. 15, in the present embodiment, after forming the adjusting structure, the method further includes: the sacrificial layer 216 is removed.

In the present embodiment, the process of removing the sacrificial layer 216 is an ashing process.

Referring to fig. 16, a capping layer 218 is formed to seal the top of the first isolation trench 214, and a cavity 219 is formed in the first isolation trench 214.

In this embodiment, an adjusting structure is formed on the inner wall surface of the first isolation trench 214, the adjusting structure includes a first region I and a second region II, a distance from the second region II to the first surface 201 is smaller than a distance from the first region I to the first surface 201, and a thickness of the second region II is greater than a thickness of the first region I. By reducing the notch size of the first isolation trench 214, the difficulty of the process of sealing the first isolation trench 214 to form a cavity is effectively reduced. And reducing the difference in sealing time, and improving the uniformity among the cavities 219 formed, thereby improving the performance of the device structure.

In the present embodiment, the capping layer 218 is formed by a chemical vapor deposition process.

In this embodiment, the material of the capping layer 218 is silicon oxide.

Referring to fig. 17, after forming the cavity 219 in the first isolation trench 214, a first source-drain doped region 220 is formed in the first surface 201 of each channel region 205.

In this embodiment, the method for forming the first source-drain doped region 220 in the first surface 201 of each channel region 205 includes: by adopting an ion implantation process, a first ion implantation treatment is performed from the first surface 201 to the second surface 202, and a first source-drain doped region 220 is formed in the first surface 201 of each channel region 205.

In the embodiment, the first ions are N-type ions; in other embodiments, the first ions may also be P-type ions.

Referring to fig. 18, a plurality of capacitor structures 221 are formed on the first surface 201, and each capacitor structure 221 is electrically connected to one first source-drain doped region 220.

In this embodiment, before forming the plurality of capacitor structures 221, the method further includes: forming a first conductive plug 222 on each first source-drain doped region 220, wherein each capacitor structure 221 is electrically connected with one first conductive plug 222; in other embodiments, the first conductive plug may not be formed.

In this embodiment, the capacitor structure 221 includes: an upper electrode layer, a lower electrode layer, and a dielectric layer (not labeled) between the upper electrode layer and the lower electrode layer.

In other embodiments, a plurality of bit line layers parallel to the first direction may be further formed on the first surface, and each of the bit line layers is electrically connected to a plurality of first source-drain doped regions in one of the active regions; before forming a number of the bit line layers, further comprising: and forming a plurality of second conductive plugs, wherein the second conductive plugs are used for electrically connecting each bit line layer with the first source-drain doped regions in the corresponding active region respectively.

Referring to fig. 19, the substrate 200 is thinned from the second side 202 toward the first side 201.

The process of thinning the substrate 200 from the second surface 202 to the first surface 201 includes a physical mechanical polishing process, a chemical mechanical polishing process, or a wet etching process. In this embodiment, the process of thinning the substrate 200 from the second surface 202 to the first surface 201 is a chemical mechanical polishing process.

The thinning process is performed until the surface of the isolation layer 206 is exposed.

In this embodiment, the depth of the isolation structure and the adjustment structure is equal to the depth of the isolation layer 206. Thus, after the thinning process, the second side of the substrate 200 also exposes the surfaces of the isolation structure 213 and the adjustment structure.

In other embodiments, the depth of the isolation structure and the adjustment structure may be smaller than the depth of the isolation layer, and the second side of the substrate does not expose the surfaces of the isolation structure and the adjustment structure after the thinning process.

Referring to fig. 20, after the thinning process, a second source/drain doped region 223 is formed in the second side 202 of each channel region 205.

In this embodiment, the method for forming the second source/drain doped region 223 in the second surface 202 of each channel region 205 includes: and performing second ion implantation treatment from the second surface 202 to the first surface 201 by using an ion implantation process, and forming a second source-drain doped region 223 in the second surface 202 of each channel region 205.

The second ions are of the same electrical type as the first ions.

In this embodiment, the second ions are N-type ions; in other embodiments, when the first ions are P-type ions, the second ions may also be P-type ions.

In this embodiment, the depth of the second source/drain doped region 223 is greater than the distance between the word line gate structure 212 and the second surface 202 of the substrate 200; in other embodiments, the depth of the second source/drain doped region 223 may also be equal to the distance between the word line gate structure and the second surface of the substrate.

From there, transistors are formed within the substrate 200.

Referring to fig. 21, a plurality of bit line layers 224 parallel to the first direction X are formed on the second surface 202, and each of the bit line layers 224 is electrically connected to a plurality of second source/drain doped regions 223 in one of the active regions 203.

In this embodiment, the capacitor structures 221 and the bit line layers 224 are respectively arranged on the first surface 201 and the second surface 202 of the substrate 200, so that the space of the capacitor structures 221 and the bit line layers 224 during arrangement can be increased, the difficulty of circuit wiring and manufacturing processes can be further effectively reduced, the area occupied by a single storage structure can be further effectively reduced, and the storage density of the memory can be improved. In addition, in the process of forming the capacitor structure 221 and the bit line layer 224, the process can be performed from the first side 201 and the second side 202 of the substrate 200, respectively, so that the process efficiency can be effectively improved.

In addition, from the perspective of the exposure process, since the capacitor structure 221 is a hole structure and the bit line layer 224 is a line structure, the hole structure is more difficult to expose, the line structure is easier to expose, and the exposure requirement is higher when the process is performed from the second surface 202. Therefore, the capacitor structures 221 with higher exposure difficulty are arranged on the first side 201 of the substrate 200, and the bit line layer 224 with lower exposure difficulty is arranged on the second side 202 of the substrate 200, so that the difficulty of an exposure process can be effectively reduced.

From a signal extraction point of view, the upper electrode plate of the capacitor structure 221 and the bit line layer 224 need to be extracted. In the same dram, the upper electrode plates of the capacitor structures 221 are connected to each other, so that a conductive region with a large area is formed, and therefore, the capacitor structures 221 can be easily led out. The linewidth of the bit line layer 224 is small and the corresponding extraction is difficult. Since the signal is led out from the second surface 202 of the substrate 200 in the process of forming the dynamic random access memory, the capacitor structure 221 with less lead difficulty is arranged on the first surface 201 of the substrate 200, and the bit line layer 224 with greater lead difficulty is arranged on the second surface 202 of the substrate 200, which can effectively reduce the process difficulty in signal leading out.

In this embodiment, one capacitor structure 221 and one transistor are arranged in a two-dimensional matrix as a unit. The basic operation mechanism is divided into Read (Read) and Write (Write), in which the bit line layer 224 is first charged to half of the operation voltage and then the transistor is turned on to generate the charge sharing phenomenon between the bit line layer 224 and the capacitor structure 221. If the internally stored value is 1, the voltage of the bit line layer 224 is raised by charge sharing to more than half of the operating voltage; on the other hand, if the internally stored value is 0, the voltage of the bit line layer 224 is pulled down to be lower than half of the operating voltage, and after the voltage of the bit line layer 224 is obtained, the internally stored value is determined to be 0 or 1 through the amplifier. When writing, the transistor is turned on, and if 1 is to be written, the voltage of the bit line layer 224 is raised to an operating voltage, so that the operating voltage is stored on the capacitor structure 221; if a 0 is to be written, then lowering the bit line layer 224 to 0 volts leaves no charge inside the capacitive structure 221.

In the present embodiment, before forming several bit line layers 224, the method further includes: forming a plurality of second conductive plugs 225, wherein each of the bit line layers 224 is electrically connected to a plurality of second source/drain doped regions 223 in a corresponding one of the active regions 203 by the plurality of second conductive plugs 225; in other embodiments, the second conductive plug may not be formed.

The bit line layer 224 material comprises a metal including tungsten, aluminum, copper, and the like. In the present embodiment, the bit line layer 224 is made of tungsten.

In the present embodiment, the method for forming the bit line layer 224 includes: forming a bit line material layer (not shown) on the second side 202; forming a third patterned layer (not shown) on the bit line material layer, the third patterned layer exposing a portion of the bit line material layer; the bit line material layer is etched from the second side 202 to the first side 201 using the third patterned layer as a mask to form the bit line layers 224.

The process for forming the bit line material layer comprises the following steps: a metal plating process, a selective metal growth process or a deposition process; the deposition process comprises a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process. In this embodiment, the bit line material layer is formed by an atomic layer deposition process.

In other embodiments, a plurality of capacitor structures may be further formed on the second surface, and each capacitor structure is electrically connected to one of the second source-drain doped regions; before forming a plurality of capacitor structures, the method further comprises the following steps: and forming a first conductive plug on each second source-drain doped region, wherein each capacitor structure is electrically connected with one first conductive plug.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A method for forming a dynamic random access memory, comprising:

providing a substrate, wherein the substrate is provided with a first surface and a second surface which are opposite, the substrate comprises a plurality of active regions which are separated from each other and parallel to a first direction, the active regions are arranged along a second direction, the first direction is different from the second direction, each active region comprises a plurality of channel regions and word line regions positioned between adjacent channel regions, and the word line regions in the adjacent active regions are arranged along the second direction;

forming word line grating structures in the word line area, wherein each word line grating structure is parallel to the second direction and is arranged along the first direction, and each word line grating structure penetrates through a plurality of active areas;

etching part of the channel region from the first surface to the second surface, and forming a first isolation groove in the channel region;

forming an adjusting structure on the inner wall surface of the first isolation trench, wherein the adjusting structure comprises a first area and a second area, the distance from the second area to the first surface is less than the distance from the first area to the first surface, and the thickness of the second area is greater than that of the first area;

and forming a covering layer to seal the top of the first isolation groove, and forming a cavity in the first isolation groove.

2. The method of claim 1, wherein the adjusting structure comprises: the protective layer is positioned on the side walls of the first area and the second area, and the adjusting layer is positioned on the side wall of the second area.

3. The method of claim 2, wherein the step of forming the adjustment structure on the inner wall surface of the first isolation trench comprises: forming a protective layer on the side wall and the bottom surface of the first isolation trench; forming a sacrificial layer in the first isolation groove, wherein the sacrificial layer is located on the protection layer, and the top surface of the sacrificial layer is lower than the first surface; after the sacrificial layer is formed, forming a regulating layer on the exposed side wall of the first isolation trench, wherein the protective layer and the regulating layer form a regulating structure; after forming the adjustment structure, removing the sacrificial layer.

4. The method of claim 2, wherein the material of the protective layer comprises: silicon oxide; the material of the regulating layer comprises: silicon oxide.

5. The method of forming a dynamic random access memory according to claim 3, wherein a material of the sacrificial layer is different from a material of the protective layer and the adjustment layer; the material of the sacrificial layer comprises: carbon; the process for removing the sacrificial layer comprises the following steps: and (5) ashing.

6. The method of claim 1, wherein the step of forming the word line grid structure in the word line region comprises: forming a word line gate trench in each word line region, wherein the word line gate trench extends from the first surface to the second surface and penetrates through the active region along the second direction; and forming the word line gate structure in each word line gate groove.

7. The method of forming a dynamic random access memory as claimed in claim 1, further comprising, during the forming of the word line gate structure: and forming an isolation structure in the word line gate trench.

8. The method of forming a dynamic random access memory of claim 7, wherein the method of forming the word line gate structure and the isolation structure within each of the word line gate trenches comprises: forming an initial word line gate structure in each word line gate groove; etching part of the initial word line gate structure from the first face to the second face, forming a plurality of second isolation grooves parallel to the second direction in the substrate, wherein the second isolation grooves penetrate through the initial word line gate structure from the first face to the second face, and enabling the initial word line gate structure to form two mutually-separated word line gate structures; and forming the isolation structure in the second isolation groove.

9. The method of claim 8, wherein a pitch between the isolation structure and the second side is less than or equal to a pitch between the word line gate structure and the second side.

10. The method of forming a dynamic random access memory of claim 6, further comprising, prior to forming the word line gate trench: and forming an isolation layer between adjacent active regions.

11. The method of claim 10, wherein the spacer layer comprises: forming a layer of isolation material between adjacent ones of the active regions and on the first face; and carrying out planarization treatment on the isolation material layer until the first surface is exposed to form the isolation layer.

12. The method of forming a dynamic random access memory of claim 8, further comprising, after forming the word line gate trench and before forming the initial word line gate structure: forming a flat layer at the bottom of the word line gate groove; the word line gate structure is located on the flat layer.

13. The method of claim 12, wherein the step of forming a planarization layer on the bottom of the word line gate trench comprises: forming a flat material layer at the bottom of the word line gate groove by adopting a spin coating process, wherein the flat material layer is fluid; and carrying out curing treatment on the flat material layer to form the flat layer.

14. The method of claim 12, wherein the material of the planarization layer comprises an insulating dielectric material; the insulating dielectric material comprises: silicon oxide or silicon nitride.

15. The method of claim 1, further comprising, after forming the cavity in the first isolation trench: forming a first source drain doped region in the first surface of each channel region; thinning the substrate from the second surface to the first surface; and forming a second source-drain doped region in the second surface of each channel region after the thinning treatment.

16. The method of claim 15, wherein after forming the cavity in the first isolation trench, further comprising: forming a plurality of capacitor structures on the first surface, wherein each capacitor structure is electrically connected with one first source drain doped region; and forming a plurality of bit line layers parallel to the first direction on the second surface, wherein each bit line layer is electrically connected with a plurality of second source-drain doped regions in one active region.

17. The method of claim 15, wherein after forming the cavity in the first isolation trench, further comprising: forming a plurality of bit line layers parallel to the first direction on the first surface, wherein each bit line layer is electrically connected with a plurality of first source-drain doped regions in one active region; and forming a plurality of capacitor structures on the second surface, wherein each capacitor structure is electrically connected with one second source drain doped region.

18. The method of claim 15, wherein a depth of the second source-drain doped region is greater than or equal to a distance between the word line gate structure and the second side of the substrate.

19. The method of claim 16, further comprising, prior to forming the plurality of capacitor structures: and forming a first conductive plug on each first source-drain doped region, wherein each capacitor structure is electrically connected with one first conductive plug.

20. The method of forming a dynamic random access memory of claim 17, further comprising, prior to forming the plurality of capacitor structures: and forming a first conductive plug on each second source-drain doped region, wherein each capacitor structure is electrically connected with one first conductive plug.

21. The method of forming a dynamic random access memory of claim 16 further comprising, prior to forming a plurality of said bit line layers: and forming a plurality of second conductive plugs, wherein the second conductive plugs are used for electrically connecting each bit line layer with the second source-drain doped regions in the corresponding active region respectively.

22. The method of forming a dynamic random access memory of claim 17, further comprising, prior to forming a plurality of the bit line layers: and forming a plurality of second conductive plugs, wherein the second conductive plugs are used for electrically connecting each bit line layer with the first source-drain doped regions in the corresponding active region respectively.

23. The method of forming a dynamic random access memory of claim 1, wherein the word line gate structure comprises: the word line gate dielectric layer is positioned on the side wall and the bottom surface of the word line gate groove, and the word line gate layer is positioned on the word line gate dielectric layer.

24. The method of forming a dynamic random access memory of claim 23 wherein the word line gate layer comprises: a single layer structure or a composite structure.

25. The method of claim 24, wherein when the word line gate layer is a single layer structure, the material of the word line gate layer comprises: metal or polysilicon.

26. The method according to claim 25, wherein when the wordline gate layer is a composite structure, the wordline gate layer comprises a first gate layer and a second gate layer located on the first gate layer, and the first gate layer and the second gate layer are made of different materials.

27. The method of claim 26, wherein the material of the first gate layer comprises: metal or polysilicon; the material of the second gate layer comprises: polysilicon or metal.