CN114373720A

CN114373720A - Method for forming dynamic random access memory

Info

Publication number: CN114373720A
Application number: CN202210062622.1A
Authority: CN
Inventors: 刘藩东; 华文宇; 骆中伟
Original assignee: ICLeague Technology Co Ltd
Current assignee: ICLeague Technology Co Ltd
Priority date: 2022-01-19
Filing date: 2022-01-19
Publication date: 2022-04-19

Abstract

A method for forming a dynamic random access memory comprises the following steps: forming a first trench and a second trench penetrating the active region along the second direction, the first trench and the second trench both extending from the first face to the second face, and the first trench being located in the word line region and the second trench being located in the channel region; forming word line gate structures and first isolation structures on the side walls of the first trenches, wherein the two word line gate structures in each first trench are isolated from each other by the first isolation structures; forming a second isolation structure in the second groove; after the word line gate structure, the first isolation structure and the second isolation structure are formed, thinning processing is carried out on the substrate from the second surface to the first surface until the second groove is exposed. The first groove and the second groove are formed in the same photoetching process, so that a uniform device channel is formed, and the performance stability of the device is improved.

Description

Method for forming dynamic random access memory

Technical Field

The invention relates to the technical field of semiconductor manufacturing, in particular to a forming method of a dynamic random access memory.

Background

With the rapid development of technology, semiconductor memories are widely used in electronic devices. Dynamic Random Access Memory (DRAM), which is a volatile memory, is the most commonly utilized solution for applications that store large amounts of data.

The basic memory cell of the dynamic random access memory is composed of a memory transistor and a memory capacitor, and the memory array is composed of a plurality of memory cells. The storage capacitor is used for storing charges representing stored information, the storage transistor is a switch for controlling the charge flowing in and discharging of the storage capacitor, and the storage transistor is also connected with an internal circuit in storage and receives a control signal of the internal circuit. The storage transistor is formed with a source region, a drain region and a gate electrode, the gate electrode is used for controlling current flowing between the source region and the drain region and is connected to a word line, the drain region is used for forming a bit line contact region and is connected to the bit line source region and is used for forming a storage node contact region and is connected to a storage capacitor. With the continuous development of integrated circuit manufacturing technology, the device density of the memory chip needs to be further increased to obtain larger data storage capacity.

However, the conventional dynamic random access memory still has many problems.

Disclosure of Invention

The invention provides a method for forming a dynamic random access memory, which can improve the stability of the performance of a device.

To solve the above problems, the present invention provides a method for forming a dynamic random access memory, comprising: providing a substrate, wherein the substrate is provided with a first face and a second face which are opposite, the substrate comprises a plurality of active regions which are separated from each other and are parallel to a first direction, the plurality of active regions are arranged along a second direction, the first direction is vertical to the second direction, each active region comprises a plurality of word line regions and a plurality of channel regions, and the plurality of word line regions and the plurality of channel regions in each active region are arranged at intervals along the first direction; forming a first trench and a second trench penetrating the active region along the second direction, the first trench and the second trench both extending from the first face to the second face, and the first trench being located in the word line region and the second trench being located in the channel region; forming word line gate structures and first isolation structures on the side walls of the first trenches, wherein the two word line gate structures in each first trench are isolated from each other by the first isolation structures; forming a second isolation structure in the second groove; after the word line gate structure, the first isolation structure and the second isolation structure are formed, thinning processing is carried out on the substrate from the second surface to the first surface until the second groove is exposed.

Optionally, the width of the first trench is greater than the width of the second trench.

Optionally, the method for forming the plurality of first trenches and the plurality of second trenches includes: forming a first mask layer on the first surface, wherein the first mask layer is provided with a first opening and a second opening, the first opening exposes the surface of the word line region, the second opening exposes part of the surface of the channel region, and the size of the first opening in the first direction is larger than that of the second opening in the first direction; and etching the active region by taking the first mask layer as a mask to form the plurality of first grooves and the plurality of second grooves.

Optionally, the first mask layer includes a plurality of mutually discrete side walls, and the side walls have equal dimensions in the first direction.

Optionally, the word line grid structure is formed first, and then the second isolation structure is formed; the method further comprises the following steps: forming a plurality of first grooves and a plurality of second grooves, and then forming a protective layer in the plurality of second grooves; after the word line grid structure is formed and before the second isolation structure is formed, removing the protective layer in the second grooves to expose the second grooves.

Optionally, the forming method of the protective layer includes: forming initial protective layers in the plurality of first grooves and the plurality of second grooves; forming a second mask layer on the first surface, wherein the second mask layer exposes the surfaces of the initial protective layers in the first grooves; and etching the initial protective layer in the plurality of first grooves by taking the second mask layer as a mask to expose the surfaces of the plurality of first grooves, and forming the protective layer by using the initial protective layer in the plurality of second grooves.

Optionally, the method for forming the plurality of first trenches and the plurality of second trenches includes: forming a first mask layer on the first surface, wherein the first mask layer is provided with a first opening and a second opening, the first opening exposes part of the surface of the word line region, the second opening exposes part of the surface of the channel region, and the first opening and the second opening have the same size; etching the active region by taking the first mask layer as a mask to form a plurality of initial first grooves and a plurality of second grooves; and etching the plurality of initial first grooves to form the plurality of first grooves by the plurality of initial first grooves.

Optionally, the word line grid structure is formed first, and then the second isolation structure is formed; the method further comprises the following steps: after the plurality of initial first grooves and the plurality of second grooves are formed, and before the plurality of initial first grooves are etched, forming protective layers in the plurality of second grooves; after the protective layer is formed, etching the plurality of initial first grooves to form the plurality of first grooves by the plurality of initial first grooves; after the word line grid structure is formed and before the second isolation structure is formed, removing the protective layer in the second grooves to expose the second grooves.

Optionally, the forming method of the protective layer includes: forming initial protective layers in the initial first grooves and the second grooves; forming a second mask layer on the first surface, wherein the second mask layer exposes the surfaces of the initial protective layers in the initial first grooves; and etching the initial protective layer in the plurality of initial first grooves by taking the second mask layer as a mask to expose the surfaces of the plurality of initial first grooves, and forming the protective layer by using the initial protective layer in the plurality of second grooves.

Optionally, the word line gate structure includes a word line gate layer.

Optionally, the method for forming the word line gate structure and the first isolation structure includes: forming an initial word line gate layer in each first groove; etching part of the initial word line gate layer from the first surface to the second surface, forming a plurality of third grooves parallel to the second direction in the substrate, wherein the third grooves penetrate through the initial word line gate layer from the first surface to the second surface to form the word line gate layer; and forming the first isolation structure in the third groove.

Optionally, the method for forming the word line gate structure and the first isolation structure includes: forming an initial word line grid layer on the first face and the side wall and the bottom of the first groove, wherein an initial third groove is formed in the initial word line grid layer in the first groove; removing the initial word line gate layer at the bottom of the first groove, and forming a third groove by using the initial third groove; forming the first isolation structure in the third trench; and after the first isolation structure is formed, removing the initial word line gate layer exposed by the first isolation structure, and forming the word line gate layer by using the initial word line gate layer.

Optionally, the word line gate structure further includes: and the gate dielectric layer is positioned between the side wall of the first groove and the word line gate layer.

Optionally, the forming process of the gate dielectric layer includes an oxidation process; the forming method of the gate dielectric layer comprises the following steps: and forming the gate dielectric layer on the side wall of the first groove before forming the word line gate layer.

Optionally, before forming the gate dielectric layer, the method further includes: carrying out oxidation treatment on the side wall of the first groove to form an oxidation layer on the side wall of the first groove; and removing the oxide layer.

Optionally, before the word line grid structure is formed, a first insulating layer is formed at the bottom of the first trench; the word line grid structure is located on the first insulating layer.

Optionally, the thinning processing method includes thinning the substrate from the second surface to the first surface until the surface of the first insulating layer or the surface of the second isolation structure is exposed.

Optionally, the top surface of the first insulating layer is higher than or flush with the bottom surface of the second trench.

Optionally, the method for forming the first insulating layer includes: forming an initial first insulating layer in the first trench; and etching back the initial first insulating layer to form the first insulating layer.

Optionally, the method further includes: forming a first source-drain doped region in the first surface of each active region after the word line gate structure, the first isolation structure and the second isolation structure are formed; after the first source-drain doped regions are formed, a plurality of capacitor structures are formed on the first surface, and each capacitor structure is electrically connected with one first source-drain doped region; after the thinning treatment, forming a second source drain doped region in each second surface of the active region; and forming a plurality of bit lines parallel to the first direction on the second surface, wherein each bit line is electrically connected with the second source-drain doped regions in one active region.

Optionally, the top surface of the word line grid structure is lower than the first surface, and a second insulating layer is arranged on the top of the word line grid structure.

Optionally, the method for forming the word line gate structure and the second insulating layer further includes: after the first isolation structure is formed and before the second isolation structure is formed, a second insulating layer is further formed in the first trench and on the word line gate structure.

Optionally, the second isolation structure has a closed void therein.

Optionally, the thinning treatment process includes a mechanical chemical polishing process.

Optionally, a third isolation layer is further disposed between adjacent active regions.

Optionally, the first trench has a first width value, the second trench has a second width value, and a difference between the first width value and the second width value ranges from 5 nm to 50 nm; the first groove has a first depth value, the second groove has a second depth value, and the difference between the first depth value and the second depth value ranges from 50 nanometers to 100 nanometers.

Optionally, the forming process of the first trench and the second trench includes a self-aligned dual imaging process.

Compared with the prior art, the technical scheme of the invention has the following advantages:

in the forming method of the technical scheme, the first groove and the second groove penetrating through the active region along the second direction are formed, the first groove and the second groove extend from the first surface to the second surface, the first groove is located in the word line region, the second groove is located in the channel region, the first groove and the second groove are formed by adopting one-time photoetching process, the alignment deviation problem of two photoetching processes does not need to be considered, the uniform device channel is formed, and the stability of the device performance is improved.

Further, a first mask layer is formed on the surface of the substrate, a first opening and a second opening are formed in the first mask layer, the first opening exposes the surface of the word line region, the second opening exposes part of the surface of the channel region, and the size of the first opening in the first direction is larger than that of the second opening in the first direction; and etching the active region by taking the first mask layer as a mask to form the plurality of first grooves and the plurality of second grooves. Because the first opening size is larger than the second opening size, the width of the formed first groove is larger than that of the second groove, and under the influence of the load effect of photoetching, the depth of the formed first groove is larger than that of the second groove.

Further, the first mask layer is used as a mask to etch the active region, and a plurality of initial first grooves and a plurality of second grooves are formed; and etching the plurality of initial first grooves to form the plurality of first grooves by the plurality of initial first grooves. The first groove is formed by etching the formed initial first groove, which is more beneficial to the method for forming the first groove and the second groove by the load effect and is beneficial to controlling the size and the depth of the formed first groove.

Further, before forming the gate dielectric layer, the method further comprises: carrying out oxidation treatment on the side wall of the first groove to form an oxidation layer on the side wall of the first groove; and removing the oxide layer. The method can improve the quality of the formed gate dielectric layer, improve the gate control capability of gate oxide and improve the width of the first groove.

Furthermore, a closed gap is formed in the second isolation structure, and the gap can improve the insulating capability of the second isolation structure and increase the isolation effect.

Drawings

FIGS. 1 and 2 are schematic cross-sectional views of a DRAM;

fig. 3 to 14 are schematic structural diagrams illustrating steps of a method for forming a dynamic random access memory according to an embodiment of the invention;

fig. 15 to 27 are schematic structural diagrams of steps of a method for forming a dynamic random access memory according to another embodiment of the invention.

Detailed Description

It should be noted that "surface" and "upper" in the present specification are used to describe a relative positional relationship in space, and are not limited to direct contact or not.

As described in the background, problems still exist with existing dynamic random access memories. As will be specifically described below.

Fig. 1 and fig. 2 are schematic cross-sectional views of a dram.

Referring to fig. 1, the dynamic random access memory includes: the semiconductor device comprises a substrate, wherein the substrate is provided with a first face 100 and a second face 101 which are opposite, the substrate comprises a plurality of active regions which are separated from each other and parallel to a first direction, the active regions are arranged along a second direction, the first direction is vertical to the second direction, each active region comprises a plurality of word line regions I and a plurality of channel regions II, and the word line regions I and the channel regions II in each active region are arranged at intervals along the first direction; a word line gate trench (not shown) in each of the word line regions I, the word line gate trench extending from the first surface 100 to the second surface 101, and the word line gate trench penetrating the active region along the second direction; the first insulating layer 102 is positioned at the bottom of the word line gate groove, and the first insulating layer 102 is exposed from the second surface 101; two mutually-separated word line gate structures 103 which are positioned in each word line gate groove and positioned on the first insulating layer 102; a second insulating layer 104 located in the word line gate trench and on the word line gate structure 103; a first isolation trench (not shown) is located between the two word line gate structures 103 and in the second insulation layer 104; a first isolation structure 105 is positioned in the first isolation groove; a second isolation groove (not shown) is arranged in each channel region II; a second isolation structure 106 located in the second isolation trench; a first source-drain doped region 107 located in the first surface 100 of each channel region II; a plurality of capacitor structures 108 located on the first surface 100, wherein each capacitor structure 108 is electrically connected to one first source drain doped region 107; a second source-drain doped region 109 located in each of the second surfaces 101 of the channel regions II; a plurality of bit lines 110 parallel to the first direction on the second surface 101, wherein each bit line 110 is electrically connected to a plurality of second source/drain doped regions 109 in one of the active regions.

The structure is a vertical channel memory, and channels of the vertical channel memory are obtained by respectively forming the word line gate grooves and the second isolation grooves. In the two photolithography processes for forming the word gate trench and the second isolation trench, the size of two adjacent conductive trenches is different due to optical alignment deviation and size error in the photolithography and etching processes, as shown in fig. 2, the trench a is larger than the trench B, so that the uniformity of the electrical performance of the formed device is poor, and the stability of the device performance is reduced.

In order to solve the above problems, a technical solution of the present invention provides a method for forming a semiconductor structure, in which a first trench and a second trench penetrating through an active region along a second direction are formed, the first trench and the second trench both extend from a first surface to a second surface, the first trench is located in a word line region, the second trench is located in a channel region, and the first trench and the second trench are formed by a single photolithography process, which does not need to consider an alignment deviation problem of two photolithography processes, is beneficial to forming a uniform device channel, and improves stability of device performance.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

Fig. 3 to 14 are schematic structural diagrams of steps of a method for forming a dynamic random access memory according to an embodiment of the invention.

Referring to fig. 3 to 5, fig. 3 is a schematic top view structure diagram of fig. 4 and 5, fig. 4 is a schematic cross-sectional structure diagram along DD1 in fig. 3, fig. 5 is a schematic cross-sectional structure diagram along EE1 in fig. 3, a substrate 200 is provided, the substrate 200 has a first side 200a and a second side 200b opposite to each other, the substrate 200 includes a plurality of active regions separated from each other and parallel to a first direction X, and the plurality of active regions are arranged along a second direction Y, the first direction X is perpendicular to the second direction Y, each of the active regions includes a plurality of word line regions 201 and a plurality of channel regions 202, and the plurality of word line regions 201 and the plurality of channel regions 202 in each of the active regions are arranged at intervals along the first direction X.

In this embodiment, the substrate 200 is made of silicon; in other embodiments, the substrate material comprises silicon carbide, silicon germanium, a multi-component semiconductor material of group iii-v elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multielement semiconductor material formed by III-V group elements comprises InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

In this embodiment, a third isolation layer 203 is further disposed between adjacent active regions.

The method for forming the active region and the third isolation layer 203 includes: forming a patterned layer (not shown) on the first side 200a of the substrate 200, the patterned layer exposing a portion of the surface of the first side 200 a; etching the first surface 200a by using the patterned layer as a mask, and forming the active regions in the substrate 200, wherein an opening (not shown) is formed between adjacent active regions; the third isolation layer 203 is formed within the opening.

The material of the third isolation layer 203 comprises a dielectric material, and the dielectric material comprises one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride.

The word line region 201 is used to form a word line gate structure, and the channel region 202 is used to form a channel of the device.

Subsequently, a first trench and a second trench penetrating the active region along the second direction Y are formed, where the first trench and the second trench both extend from the first surface 200a to the second surface 200b, the first trench is located in the word line region 201, and the second trench is located in the channel region 202.

In this embodiment, please refer to fig. 6 for a method for forming the plurality of first trenches and the plurality of second trenches.

Referring to fig. 6, the view direction of fig. 6 is the same as that of fig. 5, a first mask layer 204 is formed on the first surface 200a, the first mask layer 204 has a first opening 205 and a second opening 206 therein, the first opening 205 exposes the surface of the word line region 201, the second opening 206 exposes a portion of the surface of the channel region 202, and the size of the first opening 205 along the first direction X is larger than that of the second opening 206 along the first direction X; and etching the active region by using the first mask layer 204 as a mask to form the first trenches 207 and the second trenches 208.

After the plurality of first trenches 207 and the plurality of second trenches 208 are formed, the first mask layer 204 is also removed.

The width of the first trench 207 is greater than the width of the second trench 208. The width refers to a dimension in a direction along the surface of the substrate 200.

Since the size of the first opening 205 is larger than that of the second opening 206, the width of the first trench 207 is larger than that of the second trench 208, and the depth of the first trench 207 is larger than that of the second trench 208 under the influence of the loading effect of the photolithography.

The first trench 207 and the second trench 208 are formed by one-time photolithography process, and the alignment deviation problem of two photolithography processes does not need to be considered, so that a uniform device channel is formed, and the stability of the device performance is improved.

The formation process of the first trench 207 and the second trench 208 includes a self-aligned dual imaging process.

Specifically, the first mask layer 204 includes a plurality of mutually discrete side walls (not shown in the figure), and the size of each side wall along the first direction X is equal. Since the sizes of the side walls in the first direction X are equal, the active region is etched by using the first mask layer 304 as a mask, and the widths of the channels of the formed devices are the same. The width refers to a direction along the first direction X.

In this embodiment, the method for forming the first mask layer 204 includes: forming a first mask material layer (not shown) on the first face 200 a; forming a plurality of sacrificial layers (not shown in the figure) on the surface of the first mask material layer, wherein the sacrificial layers are parallel to the second direction Y and are arranged along the first direction X; forming a patterned material layer (not shown) on the surface of the first mask material layer, the side wall of the sacrificial layer and the top surface; etching back the patterned material layer to form a patterned layer on the side wall of the sacrificial layer; and etching the first mask material layer by taking the patterning layer as a mask to form the plurality of mutually-separated side walls.

In this embodiment, the first mask material layer is made of silicon nitride, the patterning material layer is made of silicon oxide, and the sacrificial layer is made of amorphous carbon.

In this embodiment, the first trench 207 and the second trench 208 are formed simultaneously in one photolithography etching, which can reduce the number of processes and save the production cost.

The first trench 207 has a first width value m, the second trench 208 has a second width value n, and the difference between the first width value m and the second width value n is 5 nm to 50 nm; the first trench 207 has a first depth value h1, the second trench 208 has a second depth value h2, and the difference between the first depth value h1 and the second depth value h2 is in the range of 50 nm to 100 nm.

Subsequently, word line gate structures and first isolation structures are formed on the side walls of the first trenches 207, and the two word line gate structures in each first trench 207 are isolated from each other by the first isolation structures; a second isolation structure is formed within the second trench 208.

In this embodiment, the word line grid structure is formed first, and then the second isolation structure is formed. In another embodiment, the second isolation structure may be formed first, and then the word line gate structure may be formed.

Referring to fig. 7, the view direction of fig. 7 is the same as that of fig. 5, after the plurality of first trenches 207 and the plurality of second trenches 208 are formed, a protection layer 209 is formed in the plurality of second trenches 208.

The forming method of the protective layer 209 comprises the following steps: forming an initial protection layer (not shown) in the first trenches 207 and the second trenches 208; forming a second mask layer (not shown in the figure) on the first surface 200a, wherein the second mask layer exposes the surface of the initial protection layer in the first grooves 207; and etching the initial protection layer in the plurality of first trenches 207 by using the second mask layer as a mask to expose the surfaces of the plurality of first trenches 207, and forming the protection layer 209 by using the initial protection layer in the plurality of second trenches 208.

The material of the protective layer 209 includes an organic material. The organic material is conveniently filled in the first trench 207 and the second trench 208 by spin coating or spray coating, and is easily removed in the subsequent removal process.

In this embodiment, the organic material includes organic carbon.

In this embodiment, the forming process of the protection layer 209 includes a spin coating process.

And subsequently, forming a word line gate structure and a first isolation structure on the side wall of the first groove. The word line gate structure includes a word line gate layer. In this embodiment, please refer to fig. 8 to 9 for methods for forming the word line gate structure and the first isolation structure.

Referring to fig. 8, the view direction of fig. 8 is the same as that of fig. 5, and an initial word line gate layer is formed in each of the first trenches 207.

In this embodiment, before forming the word line gate structure, a first insulating layer 210 is formed at the bottom of the first trench 207.

Specifically, before the initial word line gate layer is formed, a first insulating layer 210 is formed at the bottom of the first trench 207.

The top surface of the first insulating layer 210 is higher than or flush with the bottom surface of the second trench 207. So as to be beneficial to forming a second source-drain doped region in each active region second face 200b subsequently to provide a space. In this embodiment, the top surface of the first insulating layer 210 is higher than the bottom surface of the second trench 207.

The method for forming the first insulating layer 210 includes: forming an initial first insulating layer (not shown) in the first trench 207; the initial first insulating layer is etched back to form the first insulating layer 210.

The method for forming the initial first insulating layer comprises the following steps: forming a first dielectric material layer (not shown) in the first trench 207 and on the first side 200 a; and flattening the first dielectric material layer until the surface of the first surface 200a is exposed.

The material of the first insulating layer 210 includes a dielectric material including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.

In this embodiment, the initial wordline gate layer includes an initial work function layer 212 and an initial gate 213 on the initial work function layer 212.

In this embodiment, the method for forming the initial word line gate layer includes: forming a work function material layer (not shown) on the first surface 200a and the surface of the first insulating layer 210; forming a gate material layer (not shown) on the work function material layer, wherein the work function material layer and the gate material layer fill the first trench 207; planarizing the work function material layer and the gate material layer until the surface of the first face 200a is exposed, forming the initial work function layer 212 with the work function material layer, and forming the initial gate 213 with the gate material layer.

In this embodiment, before forming the word line gate layer, the gate dielectric layer 211 is further formed on the sidewall of the first trench 207.

Specifically, before the initial word line gate layer is formed, the gate dielectric layer 211 is also formed on the sidewall of the first trench 207.

The forming process of the gate dielectric layer 211 includes an oxidation process.

Referring to fig. 9, the view direction of fig. 9 is the same as that of fig. 5, a portion of the initial word line gate layer is etched from the first surface 200a to the second surface 200b, a plurality of third trenches (not shown) parallel to the second direction Y are formed in the substrate 200, and the third trenches penetrate through the initial word line gate layer from the first surface 200a to the second surface 200b to form the word line gate layer; the first isolation structure 216 is formed within the third trench.

The word line gate structure includes a word line gate layer.

In this embodiment, the word line gate layer includes a work function layer 215 and a gate 214 on the work function layer 215. Specifically, the work function layer 215 is formed by the initial work function layer 212; the gate 214 is formed with the initial gate 213.

The material of the gate 214 includes metal or silicon. In this embodiment, the gate 214 is made of tungsten.

The word line gate structure further includes a gate dielectric layer 211 located between the sidewalls of the first trench 207 and the word line gate layer.

In this embodiment, the word line gate structure is located on the first insulating layer 210.

The material of the first isolation structure 216 comprises a dielectric material comprising one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.

The method for forming the first isolation structure 216 includes: forming a second dielectric material layer in the third trench and on the first face 200 a; and flattening the second dielectric material layer until the surface of the first surface 200a is exposed.

In this embodiment, the top surface of the word line grid structure is lower than the surface of the first side 200a, and the top of the word line grid structure has a second insulating layer. The methods for forming the word line gate structure and the second insulating layer are also described with reference to fig. 10.

Referring to fig. 10, the view direction of fig. 10 is the same as that of fig. 5, and the word line gate structure and the first isolation structure 216 are etched back.

In this embodiment, the top surface of the word line grid structure is lower than the surface of the first side 200 a. In other embodiments, the top surface of the word line gate structure is flush with the surface of the first side 200 a.

In this embodiment, the work function layer 215 and the gate dielectric layer 211 are also etched back. In other embodiments, the word line gate structure, the first isolation structure 216, and the work function layer 215 may be etched back, but the gate dielectric layer 211 is not etched back.

With continued reference to fig. 10, after the first isolation structures 216 are formed and before the second isolation structures are formed, a second insulating layer 217 is further formed on the word line gate structures in the first trenches 207.

Specifically, after etching back the word line gate structure and the first isolation structure 216, and before forming the second isolation structure, the second insulating layer 217 is further formed on the word line gate structure and the first isolation structure 216 in the first trenches 207.

The material of the second insulating layer 217 comprises a dielectric material comprising one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride.

The method for forming the second insulating layer 217 includes: forming a third dielectric material layer on the word line gate structure, the first isolation structure 216 and the first side 200 a; and flattening the second dielectric material layer until the surface of the first surface 200a is exposed.

Referring to fig. 11, the view direction of fig. 11 is the same as that of fig. 5, after the word line gate structure is formed and before the second isolation structure is formed, the protective layer 209 in the second trenches 208 is removed to expose the second trenches 208.

The process of removing the protection layer 209 in the second trench 208 includes one or a combination of a dry etching process and a wet etching process. In this embodiment, the process of removing the protection layer 209 in the second trench 208 is a dry etching process.

With continued reference to fig. 11, a second isolation structure 218 is formed within the second trench 208.

In this embodiment, the second isolation structure 218 has a closed void therein. The voids may improve the insulating ability of the second isolation structure 218, increasing the isolation effect. In other embodiments, the second isolation structure may not form the void.

The material of the second isolation structure 218 includes a dielectric material including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.

The method for forming the second isolation structure 218 includes: forming a fourth layer of dielectric material within said second trenches 208 and on said first face 200 a; the fourth dielectric material layer is planarized until the first side 200a is exposed.

In the present embodiment, the second isolation structure 218 is formed by a plasma enhanced chemical vapor deposition process. The pecvd process facilitates early closing of the top opening of the second trench 208, facilitating formation of a void within the second isolation structure 218.

Referring to fig. 12, the view direction of fig. 12 is the same as that of fig. 5, after the word line grid structure, the first isolation structure 216 and the second isolation structure 218 are formed, a first source drain doped region 219 is formed in each of the first surfaces 200a of the active regions; after the first source-drain doped regions 219 are formed, a plurality of capacitor structures 220 are formed on the first surface 100a, and each capacitor structure 220 is electrically connected to one first source-drain doped region 219.

The method for forming the first source-drain doped region 219 includes: first doping ions are implanted into the active region from the first face 200a, and the first doping ions include N-type ions or P-type ions. In this embodiment, the first doping ions are N-type ions.

The method for forming the capacitor structure 220 includes: forming a first dielectric layer (not shown) on the first face 200 a; forming a plurality of first grooves (not marked in the figure) in the first dielectric layer, wherein the surfaces of the first source-drain doped regions 219 are exposed by the first grooves; the capacitor structure 220 is formed in the first recess.

The capacitor structure 220 includes: a first electrode layer (not shown), a second electrode layer (not shown), and a dielectric layer (not shown) between the first electrode layer and the second electrode layer.

The shape of the dielectric layer includes: planar or "U" shaped.

When the shape of the dielectric layer is planar, the surface of the first electrode layer is flat, and the surface of the second electrode layer is flat.

When the dielectric layer is in a U shape, the surface of the first electrode layer is an uneven surface, and the surface of the second electrode layer is an uneven surface; or the surface of the first electrode layer is flat, and the surface of the second electrode layer is flat.

The material of the first electrode layer includes: a metal or metal nitride; the material of the second electrode layer includes: a metal or metal nitride; the metal includes: combinations of one or more of copper, aluminum, tungsten, cobalt, nickel, and tantalum; the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride.

In this embodiment, a capacitor plug 221 is further disposed between the capacitor structure 220 and the first source-drain doped region 219. In other embodiments, the capacitor structure 220 is directly connected to the first source/drain doped region 219 without a capacitor plug.

In this embodiment, the method for forming the capacitor plug 221 includes: a first contact hole (not shown) is further formed in the first groove, and the first contact hole exposes the surface of the first source drain doped region 219; the capacitor plug 221 is formed in the first contact hole.

Referring to fig. 13, the view direction of fig. 13 is the same as that of fig. 5, after the word line gate structure, the first isolation structure 216 and the second isolation structure 218 are formed, the substrate 200 is thinned from the second side 200b toward the first side 200a until the second trench 207 is exposed.

Specifically, after the capacitor structures 220 are formed, the substrate 200 is thinned from the second surface 200b to the first surface 200a until the second trench 207 is exposed.

The thinning method includes thinning the substrate 200 from the second side 200b to the first side 200a until the surface of the first insulating layer 210 or the surface of the second isolation structure 218 is exposed.

The thinning treatment process comprises a mechanical chemical grinding process.

In this embodiment, the substrate 200 is thinned from the second surface 200b toward the first surface 200a until the surface of the first insulating layer 210 is exposed.

Referring to fig. 14, the view direction of fig. 14 is the same as that of fig. 5, after the thinning process, a second source/drain doped region 222 is formed in each of the second faces 200b of the active regions; a plurality of bit lines 224 parallel to the first direction X are formed on the second surface 200b, and each of the bit lines 224 is electrically connected to a plurality of second source/drain doped regions 222 in one of the active regions.

The method for forming the second source-drain doped region 222 includes: second doping ions are implanted into the active region from the second face 200b, and the second doping ions include N-type ions or P-type ions. In this embodiment, the second doping ions are N-type ions.

The method for forming the bit lines 224 comprises the following steps: forming a second dielectric layer (not shown) on the surface of the second side 200 b; forming a plurality of second grooves (not marked in the figure) in the second dielectric layer, wherein the second grooves extend along the X direction, and one second groove exposes partial surfaces of the plurality of active regions; the bit lines 224 are formed within the second recesses.

In this embodiment, a bit line plug 223 is further disposed between the bit line 224 and the second source/drain doped region 222. In other embodiments, the bit line 224 is directly connected to the second source/drain doped region 222, and a bit line plug is not required.

In this embodiment, the method for forming the bit line plug includes: a second contact hole (not shown) is further formed in the second groove, and the second contact hole exposes the surface of the second source/drain doped region 222; the bit line plugs 223 are formed within the second contact holes.

In this embodiment, please refer to fig. 15 on the basis of fig. 3 to fig. 5, and please refer to fig. 15 to fig. 17 for a method for forming the plurality of first trenches and the plurality of second trenches.

Referring to fig. 15, the view direction of fig. 15 is the same as that of fig. 5, a first mask layer 304 is formed on the first surface 200a, the first mask layer 304 has a first opening 305 and a second opening 306 therein, the first opening 305 exposes a portion of the surface of the word line region 201, the second opening 306 exposes a portion of the surface of the channel region 202, and the first opening 305 and the second opening 306 have the same size; and etching the active region by using the first mask layer 304 as a mask to form a plurality of initial first trenches 307 and a plurality of second trenches 308.

The formation process of the initial first trench 307 and the second trench 308 includes a self-aligned dual imaging process.

After the initial first trench 307 and the second trench 308 are formed, the first mask layer 304 is also removed.

Subsequently, the initial trenches 307 are etched to form the first trenches 307. In this embodiment, after the initial first trenches and the second trenches are formed, and before the initial first trenches 307 are etched, please refer to fig. 16.

Referring to fig. 16, the view direction of fig. 16 is the same as that of fig. 5, after the initial trenches 307 and the second trenches 308 are formed, and before the initial trenches 307 are etched, a protection layer 309 is formed in the second trenches 308.

The protection layer 309 is used for protecting the second trench 308 when the plurality of initial first trenches 307 are etched subsequently.

The method for forming the protection layer 309 includes: forming an initial protective layer (not shown) in the plurality of initial first trenches 307 and the plurality of second trenches 308; forming a second mask layer (not shown in the figure) on the first surface 200a, wherein the second mask layer exposes the initial protection layer surfaces in the initial first trenches 307; and etching the initial protective layer in the plurality of initial first trenches 307 by using the second mask layer as a mask to expose the surfaces of the plurality of initial first trenches 307, and forming the protective layer 309 by using the initial protective layer in the plurality of second trenches 308.

The material of the protective layer 309 includes an organic material. The organic material is conveniently filled in the initial first trench 307 and the second trench 308 by spin coating or spray coating, and is easily removed in the subsequent removal process.

In this embodiment, the organic material includes organic carbon.

In this embodiment, the forming process of the protection layer 309 includes a spin coating process.

Referring to fig. 17, the view direction of fig. 17 is the same as that of fig. 5, after the protective layer 309 is formed, the plurality of initial first trenches 307 are etched, and the plurality of first trenches 303 are formed by the plurality of initial first trenches 307.

The first trench 303 and the second trench 308 are formed by one-time lithography process, and the alignment deviation problem of two-time lithography process does not need to be considered, so that a uniform device channel is formed, and the performance stability of the device is improved.

In this embodiment, the first trench 303 is formed by etching the formed initial first trench 307, which is more beneficial to the method of forming the first trench and the second trench by the loading effect and is beneficial to controlling the size and the depth of the formed first trench.

The method for etching the plurality of initial first trenches 307 further comprises: forming a third mask layer (not shown in the figure) on the first surface 200a and the protection layer 309; and etching the plurality of initial first trenches 307 by taking the third mask layer as a mask to form the plurality of first trenches 303.

The process of etching the number of initial first trenches 307 includes one or a combination of a dry etch process and a wet etch process. In this embodiment, the process of etching the plurality of initial first trenches 307 is a dry etching process, and the dry etching process is beneficial to forming trenches with better morphology.

In this embodiment, the first trench 303 is formed by etching the formed initial first trench 307, so that the instability of the loading effect caused by the non-uniform sizes of the first opening 305 and the second opening 306 can be reduced, and the size and the depth of the formed first trench 303 can be controlled.

Subsequently, word line gate structures and first isolation structures are formed on the side walls of the first trenches 303, and the two word line gate structures in each first trench 303 are isolated from each other by the first isolation structures; a second isolation structure is formed within the second trench 308. In this embodiment, before forming the word line grid structure, a first insulating layer is formed at the bottom of the first trench, and a method for forming the first insulating layer refers to fig. 18.

Referring to fig. 18, an insulating material layer (not shown) is formed in the first trench 303 and on the first surface 200 a; planarizing the insulating material layer until the surface of the first face 200a is exposed; after the planarization process, the insulating material layer is etched back to form the first insulating layer 310.

The material of the first insulating layer 310 includes a dielectric material including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.

The top surface of the first insulating layer 310 is higher than or flush with the bottom surface of the second trench 307. In this embodiment, the top surface of the first insulating layer 310 is flush with the bottom surface of the second trench 307.

In this embodiment, the word line gate structure and the first isolation structure are located on the first insulating layer 310.

The word line gate structure includes a word line gate layer. In this embodiment, please refer to fig. 19 to 22 for a method for forming the word line gate structure and the first isolation structure.

Referring to fig. 19, an initial word line gate layer is formed on the first side 200a at the bottom and the sidewall of the first trench 303, and an initial third trench 314 is formed in the initial word line gate layer in the first trench 303.

In this embodiment, the initial wordline gate layer includes a work function material layer 312 and a gate material layer 313 on the work function material layer 312.

In this embodiment, the initial word line gate layer is also located on the surface of the first insulating layer 310.

In this embodiment, before forming the initial word line gate layer, a gate dielectric layer 311 is formed on the sidewall of the first trench 303.

The forming process of the gate dielectric layer 311 includes an oxidation process.

Specifically, after the first insulating layer 310 is formed, the sidewall of the first trench 303 exposed by the first insulating layer 310 is subjected to surface oxidation by using an oxidation process to form the gate dielectric layer 311.

In other embodiments, before forming the gate dielectric layer 311, the method further includes: carrying out oxidation treatment on the side wall of the first groove to form an oxidation layer on the side wall of the first groove; and removing the oxide layer. The method can improve the quality of the formed gate dielectric layer, improve the gate control capability of gate oxide and improve the width of the first groove.

Referring to fig. 20, the initial wordline gate layer at the bottom of the first trench 303 is removed to form a third trench 315 in the initial third trench 314.

The process of removing the initial word line gate layer at the bottom of the first trench 303 includes one or a combination of a dry etching process and a wet etching process.

In this embodiment, the process of removing the initial word line gate layer at the bottom of the first trench 303 is a dry etching process.

In this embodiment, the initial word line gate layer on the surface of the substrate 200 is retained, which can protect the surface of the substrate 200 in a subsequent etching process. In other embodiments, the initial word line gate layer on the surface of the substrate 200 is etched away while the initial word line gate layer on the bottom of the first trench 303 is removed.

Referring to fig. 21, the first isolation structure 316 is formed in the third trench 315.

In this embodiment, the top surface of the first isolation structure 316 is lower than the first surface 200 a. In other embodiments, the top surface of the first isolation structure 316 may be flush with the first side 200 a.

The material of the first isolation structure 316 includes a dielectric material including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.

The method for forming the first isolation structure 316 includes: forming a layer of dielectric material in said third trench 315 and on said first face 200 a; planarizing the dielectric material layer until the surface of the first face 200a is exposed; after the planarization process, the dielectric material layer is etched back to form the first isolation structure 316.

In this embodiment, the gate dielectric layer 311 is etched back while the dielectric material layer is etched back. In other embodiments, the gate dielectric layer may not be etched back.

Referring to fig. 22, after the first isolation structure 316 is formed, the initial word line gate layer exposed by the first isolation structure 316 is removed, and the word line gate layer is formed by the initial word line gate layer.

The word line gate structure includes the word line gate layer.

In this embodiment, the word line gate layer includes a work function layer 318 and a gate 317 on the work function layer 318. Specifically, the work function layer 318 is formed by the initial work function layer 312; the gate electrode 317 is formed with the gate material layer 313.

The material of the gate 317 includes metal or silicon. In this embodiment, the gate is made of tungsten.

In this embodiment, the word line gate structure further includes a gate dielectric layer 311 located between the sidewall of the first trench 303 and the word line gate layer.

In this embodiment, the word line grid structure is located on the first insulating layer 310.

Referring to fig. 23, after the first isolation structure 316 is formed and before the second isolation structure is formed, a second insulation layer 320 is further formed on the word line gate structure in the first trenches 303.

The material of the second insulating layer 320 includes a dielectric material including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.

The method for forming the second insulating layer 320 includes: forming a layer of insulating material (not shown) within said first face 200a and said first trenches 303; the insulating material layer is planarized until the first face 200a is exposed.

Referring to fig. 24, after the word line gate structure is formed and before the second isolation structure is formed, the protection layer 309 in the second trench 308 is removed to expose the second trench 308.

Specifically, after the second insulating layer 320 is formed and before the second isolation structure is formed, the protective layer 309 in the second trench 308 is removed to expose the second trench 308.

The process of removing the protection layer 309 in the second trench 308 includes one or a combination of a dry etching process and a wet etching process. In this embodiment, the process of removing the protection layer 309 in the second trench 308 is a dry etching process.

With continued reference to fig. 24, a second isolation structure 321 is formed within the second trench 308.

In this embodiment, the second isolation structure 321 has a closed space therein. The void may improve the insulating ability of the second isolation structure 321, increasing the isolation effect. In other embodiments, the second isolation structure may not form the void.

The material of the second isolation structure 321 includes a dielectric material, and the dielectric material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride.

In this embodiment, the forming process of the second isolation structure 321 includes a plasma enhanced chemical vapor deposition process. The pecvd process facilitates the closing of the top opening of the second trench 308 in advance, and facilitates the formation of a void within the second isolation structure 321.

Referring to fig. 25, the view direction of fig. 25 is the same as that of fig. 5, and after the word line grid structure, the first isolation structure 316 and the second isolation structure 321 are formed, a first source/drain doped region 322 is formed in each of the first surfaces 200a of the active regions; after the first source-drain doped regions 322 are formed, a plurality of capacitor structures 323 are formed on the first surface 200a, and each capacitor structure 323 is electrically connected to one first source-drain doped region 322.

The method for forming the first source-drain doped region 322 includes: first doping ions are implanted into the active region from the first face 200a, and the first doping ions include N-type ions or P-type ions. In this embodiment, the first doping ions are N-type ions.

The method for forming the capacitor structure 323 comprises the following steps: forming a first dielectric layer (not shown) on the first face 200 a; forming a plurality of first grooves (not shown) in the first dielectric layer, where the first grooves expose surfaces of the first source-drain doped regions 322; the capacitor structure 323 is formed in the first recess.

The capacitor structure 323 includes: a first electrode layer (not shown), a second electrode layer (not shown), and a dielectric layer (not shown) between the first electrode layer and the second electrode layer.

The shape of the dielectric layer includes: planar or "U" shaped.

In this embodiment, a capacitor plug 324 is further disposed between the capacitor structure 323 and the first source-drain doped region 322. In other embodiments, the capacitor structure 323 is directly connected to the first source/drain doped region 322 without a capacitor plug.

In this embodiment, the method for forming the capacitor plug 324 includes: a first contact hole (not shown) is further formed in the first groove, and the first contact hole exposes the surface of the first source/drain doped region 322; the capacitor plug 324 is formed in the first contact hole.

Referring to fig. 26, the view direction of fig. 26 is the same as that of fig. 5, after the word line gate structure, the first isolation structure 316 and the second isolation structure 321 are formed, the substrate 200 is thinned from the second surface 200b to the first surface 200a until the second trench 308 is exposed.

Specifically, after the capacitor structures 323 are formed, the substrate 200 is thinned from the second side 200b toward the first side 200a until the second trench 308 is exposed.

The thinning method includes thinning the substrate 200 from the second side 200b to the first side 200a until the surface of the first insulating layer 310 or the surface of the second isolation structure 321 is exposed.

In this embodiment, the substrate 200 is thinned from the second surface 200b toward the first surface 200a until the surface of the first insulating layer 310 is exposed.

Referring to fig. 27, the view direction of fig. 27 is the same as that of fig. 5, after the thinning process, a second source/drain doped region 325 is formed in each of the active region second surfaces 200 b; a plurality of bit lines 326 parallel to the first direction X are formed on the second surface 200b, and each bit line 326 is electrically connected to a plurality of second source/drain doped regions 325 in one of the active regions.

The method for forming the second source-drain doped region 325 includes: second doping ions are implanted into the active region from the second face 200b, and the second doping ions include N-type ions or P-type ions. In this embodiment, the second doping ions are N-type ions.

The method for forming the bit lines 326 comprises the following steps: forming a second dielectric layer (not shown) on the surface of the second side 200 b; forming a plurality of second grooves (not marked in the figure) in the second dielectric layer, wherein the second grooves extend along the X direction, and one second groove exposes partial surfaces of the plurality of active regions; the bit lines 326 are formed within the second recess.

In this embodiment, a bit line plug 327 is further disposed between the bit lines 326 and the second source/drain doped region 325. In other embodiments, the bit lines 326 are directly connected to the second source/drain doped regions 325 without bit line plugs.

In this embodiment, the method for forming the bit line plug includes: a second contact hole (not shown) is further formed in the second groove, and the second contact hole exposes the surface of the second source/drain doped region 325; the bit line plugs 327 are formed within the second contact holes.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A method for forming a dynamic random access memory, comprising:

providing a substrate, wherein the substrate is provided with a first face and a second face which are opposite, the substrate comprises a plurality of active regions which are separated from each other and are parallel to a first direction, the plurality of active regions are arranged along a second direction, the first direction is vertical to the second direction, each active region comprises a plurality of word line regions and a plurality of channel regions, and the plurality of word line regions and the plurality of channel regions in each active region are arranged at intervals along the first direction;

forming a first trench and a second trench penetrating the active region along the second direction, the first trench and the second trench both extending from the first face to the second face, and the first trench being located in the word line region and the second trench being located in the channel region;

forming word line gate structures and first isolation structures on the side walls of the first trenches, wherein the two word line gate structures in each first trench are isolated from each other by the first isolation structures;

forming a second isolation structure in the second groove;

after the word line gate structure, the first isolation structure and the second isolation structure are formed, thinning processing is carried out on the substrate from the second surface to the first surface until the second groove is exposed.

2. The method of claim 1, wherein the width of the first trench is greater than the width of the second trench.

3. The method of forming a dynamic random access memory of claim 2 wherein the method of forming the first plurality of trenches and the second plurality of trenches comprises: forming a first mask layer on the first surface, wherein the first mask layer is provided with a first opening and a second opening, the first opening exposes the surface of the word line region, the second opening exposes part of the surface of the channel region, and the size of the first opening in the first direction is larger than that of the second opening in the first direction; and etching the active region by taking the first mask layer as a mask to form the plurality of first grooves and the plurality of second grooves.

4. The method according to claim 3, wherein the first mask layer comprises a plurality of mutually discrete side walls, and the size of each side wall along the first direction is equal.

5. The method according to claim 3, wherein the word line grid structure is formed first, and then the second isolation structure is formed; the method further comprises the following steps: forming a plurality of first grooves and a plurality of second grooves, and then forming a protective layer in the plurality of second grooves; after the word line grid structure is formed and before the second isolation structure is formed, removing the protective layer in the second grooves to expose the second grooves.

6. The method of claim 5, wherein the step of forming the passivation layer comprises: forming initial protective layers in the plurality of first grooves and the plurality of second grooves; forming a second mask layer on the first surface, wherein the second mask layer exposes the surfaces of the initial protective layers in the first grooves; and etching the initial protective layer in the plurality of first grooves by taking the second mask layer as a mask to expose the surfaces of the plurality of first grooves, and forming the protective layer by using the initial protective layer in the plurality of second grooves.

7. The method of forming a dynamic random access memory of claim 2 wherein the method of forming the first plurality of trenches and the second plurality of trenches comprises: forming a first mask layer on the first surface, wherein the first mask layer is provided with a first opening and a second opening, the first opening exposes part of the surface of the word line region, the second opening exposes part of the surface of the channel region, and the first opening and the second opening have the same size; etching the active region by taking the first mask layer as a mask to form a plurality of initial first grooves and a plurality of second grooves; and etching the plurality of initial first grooves to form the plurality of first grooves by the plurality of initial first grooves.

8. The method according to claim 7, wherein the word line grid structure is formed first, and then the second isolation structure is formed; the method further comprises the following steps: after the plurality of initial first grooves and the plurality of second grooves are formed, and before the plurality of initial first grooves are etched, forming protective layers in the plurality of second grooves; after the protective layer is formed, etching the plurality of initial first grooves to form the plurality of first grooves by the plurality of initial first grooves; after the word line grid structure is formed and before the second isolation structure is formed, removing the protective layer in the second grooves to expose the second grooves.

9. The method of claim 8, wherein the step of forming the passivation layer comprises: forming initial protective layers in the initial first grooves and the second grooves; forming a second mask layer on the first surface, wherein the second mask layer exposes the surfaces of the initial protective layers in the initial first grooves; and etching the initial protective layer in the plurality of initial first grooves by taking the second mask layer as a mask to expose the surfaces of the plurality of initial first grooves, and forming the protective layer by using the initial protective layer in the plurality of second grooves.

10. The method of claim 1, wherein the word line gate structure comprises a word line gate layer.

11. The method of forming a dynamic random access memory according to claim 10, wherein the method of forming the word line gate structure and the first isolation structure comprises: forming an initial word line gate layer in each first groove; etching part of the initial word line gate layer from the first surface to the second surface, forming a plurality of third grooves parallel to the second direction in the substrate, wherein the third grooves penetrate through the initial word line gate layer from the first surface to the second surface to form the word line gate layer; and forming the first isolation structure in the third groove.

12. The method of forming a dynamic random access memory according to claim 10, wherein the method of forming the word line gate structure and the first isolation structure comprises: forming an initial word line grid layer on the first face and the side wall and the bottom of the first groove, wherein an initial third groove is formed in the initial word line grid layer in the first groove; removing the initial word line gate layer at the bottom of the first groove, and forming a third groove by using the initial third groove; forming the first isolation structure in the third trench; and after the first isolation structure is formed, removing the initial word line gate layer exposed by the first isolation structure, and forming the word line gate layer by using the initial word line gate layer.

13. The method of forming a dynamic random access memory of claim 10, wherein the word line gate structure further comprises: and the gate dielectric layer is positioned between the side wall of the first groove and the word line gate layer.

14. The method of claim 13, wherein the gate dielectric layer is formed by an oxidation process; the forming method of the gate dielectric layer comprises the following steps: and forming the gate dielectric layer on the side wall of the first groove before forming the word line gate layer.

15. The method of claim 14, wherein forming the gate dielectric layer further comprises: carrying out oxidation treatment on the side wall of the first groove to form an oxidation layer on the side wall of the first groove; and removing the oxide layer.

16. The method according to claim 1, wherein before the word line gate structure is formed, a first insulating layer is formed at the bottom of the first trench; the word line grid structure is located on the first insulating layer.

17. The method of claim 16, wherein the thinning comprises thinning the substrate from the second side toward the first side until the first insulating layer surface or the second isolation structure surface is exposed.

18. The method of claim 16, wherein the top surface of the first insulating layer is higher than or flush with the bottom surface of the second trench.

19. The method of forming a dynamic random access memory according to claim 16, wherein the method of forming the first insulating layer comprises: forming an initial first insulating layer in the first trench; and etching back the initial first insulating layer to form the first insulating layer.

20. The method of forming a dynamic random access memory of claim 1, further comprising: forming a first source-drain doped region in the first surface of each active region after the word line gate structure, the first isolation structure and the second isolation structure are formed; after the first source-drain doped regions are formed, a plurality of capacitor structures are formed on the first surface, and each capacitor structure is electrically connected with one first source-drain doped region; after the thinning treatment, forming a second source drain doped region in each second surface of the active region; and forming a plurality of bit lines parallel to the first direction on the second surface, wherein each bit line is electrically connected with the second source-drain doped regions in one active region.

21. The method of claim 1, wherein a top surface of the word line gate structure is lower than the first surface, and a second insulating layer is on top of the word line gate structure.

22. The method of forming a dynamic random access memory of claim 21, wherein the method of forming the word line gate structure and the second insulating layer further comprises: after the first isolation structure is formed and before the second isolation structure is formed, a second insulating layer is further formed in the first trench and on the word line gate structure.

23. The method of claim 1, wherein the second isolation structure has a closed void therein.

24. The method of claim 1, wherein the thinning process comprises a mechanochemical polishing process.

25. The method as claimed in claim 1, wherein a third spacer is disposed between adjacent active regions.

26. The method of claim 1, wherein the first trench has a first width and the second trench has a second width, and the difference between the first width and the second width is in a range of 5 nm to 50 nm; the first groove has a first depth value, the second groove has a second depth value, and the difference between the first depth value and the second depth value ranges from 50 nanometers to 100 nanometers.

27. The method of claim 1, wherein the forming process of the first trench and the second trench comprises a self-aligned dual imaging process.