CN114220765B

CN114220765B - Memory and manufacturing method thereof

Info

Publication number: CN114220765B
Application number: CN202210160600.9A
Authority: CN
Inventors: 华文宇; 程卫华; 朱宏斌; 刘威; 刘藩东
Original assignee: ICLeague Technology Co Ltd
Current assignee: ICLeague Technology Co Ltd
Priority date: 2022-02-22
Filing date: 2022-02-22
Publication date: 2022-06-21
Anticipated expiration: 2042-02-22
Also published as: CN114220765A

Abstract

The application provides a memory and a manufacturing method thereof, wherein the manufacturing method comprises the following steps: providing a substrate; forming a plurality of first isolation structures which extend along a first direction and are parallel to each other in the substrate; the first direction is parallel to the substrate surface; a first thickness of the first isolation structure is less than a thickness of the substrate; forming a plurality of first grooves which extend along a second direction and are parallel to each other in the substrate; the second direction is parallel to the substrate surface and perpendicular to the first direction; the first trench and the first isolation structure divide the substrate into a plurality of channel columns; forming a word line structure and a second isolation structure in the first trench; the word line structures and the second isolation structures are arranged in parallel and extend along the side wall of the first groove; and forming a storage structure on the surface of the channel column adjacent to the word line structure.

Description

Memory and manufacturing method thereof

Technical Field

The present application relates to the field of semiconductor technology, and more particularly, to a memory and a method for manufacturing the same.

Background

With the continuous development of scientific technology, memories are widely used in various electronic devices. A Random Access Memory (RAM) is a volatile Memory, which is a semiconductor Memory device commonly used in computers.

The random access memory is composed of a plurality of repeated memory cells, each memory cell is mainly composed of a transistor and a capacitor controlled by the transistor, and each memory cell is electrically connected with each other through a word line and a bit line. However, the random access memory has the problems of large occupied area of the memory cells, complex wiring, high manufacturing process difficulty and the like.

Disclosure of Invention

In view of the foregoing, embodiments of the present application provide a memory and a method for manufacturing the same.

In a first aspect, an embodiment of the present application provides a method for manufacturing a memory, where the method includes:

providing a substrate;

forming a plurality of first isolation structures which extend along a first direction and are parallel to each other in the substrate; the first direction is parallel to the substrate surface; a first thickness of the first isolation structure is less than a thickness of the substrate;

forming a plurality of first grooves which extend along a second direction and are parallel to each other in the substrate; the second direction is parallel to the substrate surface and perpendicular to the first direction; the first trench and the first isolation structure divide the substrate into a plurality of channel columns;

forming a word line structure and a second isolation structure in the first trench; the word line structures and the second isolation structures are arranged in parallel and extend along the side wall of the first groove;

and forming a storage structure on the surface of the channel column adjacent to the word line structure.

In some embodiments, the method further comprises:

forming a third isolation structure with a second thickness at the bottom of the first trench; the second thickness is smaller than the depth of the first groove; the word line structure and the second isolation structure are formed over the third isolation structure.

In some embodiments, the method further comprises:

forming a first oxide layer covering the inner wall of the first groove;

forming a first protective layer covering the first oxide layer;

the forming a third isolation structure of a second thickness at the bottom of the first trench includes:

and forming the third isolation structure in the first groove with the inner wall covered with the first oxide layer and the first protective layer.

In some embodiments, the forming the third isolation structure in the first trench whose inner wall is covered with the first oxide layer and the first protection layer includes:

filling an insulating material in the first groove with the inner wall covered with the first oxide layer and the first protective layer;

removing at least part of the insulating material to enable the bottom of the first trench to retain the second thickness of the insulating material so as to form the third isolation structure;

and removing the first protective layer above the third isolation structure.

In some embodiments, the forming a word line structure and a second isolation structure in the first trench includes:

forming a first sacrificial layer covering a first sidewall of the first trench and a second sacrificial layer covering a second sidewall of the first trench over the third isolation structure; wherein the first sidewall and the second sidewall are different sidewalls opposite in the first trench;

forming a spacer layer between the first sacrificial layer and the second sacrificial layer;

removing the first sacrificial layer to form a second groove;

forming the word line structure in the second trench;

removing the second sacrificial layer to form a third groove;

forming the second isolation structure in the third trench.

In some embodiments, the forming a first sacrificial layer covering a first sidewall of the first trench and forming a second sacrificial layer covering a second sidewall of the first trench includes:

forming a sacrificial layer covering the inner wall of the first groove in the first groove;

and removing part of the sacrificial layer on the upper surface of the third isolation structure to form the first sacrificial layer and the second sacrificial layer which are separated from each other.

In some embodiments, the removing the first sacrificial layer to form a second trench includes:

forming a fourth groove on one end, close to the surface of the substrate, of the second sacrificial layer;

forming a second protective layer in the fourth trench to cover the second sacrificial layer;

and removing the first sacrificial layer to form the second groove.

In some embodiments, the removing the second sacrificial layer to form a third trench includes:

removing the second protective layer;

and removing the second sacrificial layer to form the third groove.

In some embodiments, the forming the word line structure in the second trench includes:

removing the first oxide layer in the spacing layer and the second groove;

forming a gate oxide layer on the side wall of the second groove;

filling a conductive material in the second trench;

removing at least part of the conductive material to form a word line with a third thickness, wherein the third thickness is smaller than the depth of the second groove;

filling an insulating material on the word line in the second groove to form a gate protection layer; wherein the word line structure includes the gate oxide layer, the word line, and the gate protection layer.

In some embodiments, the forming the second isolation structure in the third trench includes:

and filling an insulating material in the third groove to form the second isolation structure with an air gap in the middle.

In some embodiments, the method further comprises:

doping the first end of the channel column to form a source electrode of the transistor;

and doping the second end of the channel column to form the drain electrode of the transistor.

In some embodiments, the forming a storage structure on the surface of the channel pillar adjacent to the word line structure includes:

and forming a storage capacitor on the surface of the source electrode adjacent to the word line structure.

In some embodiments, said doping the second end of the channel pillar to form the drain of the transistor comprises:

thinning the back surface of the substrate until the third isolation structure is exposed;

and doping the second end of the channel column adjacent to the third isolation structure to form the drain electrode of the transistor.

In some embodiments, the method further comprises:

and forming a bit line connected with the drain electrode of the transistor on the back surface of the substrate.

In some embodiments, said forming a bit line connected to a drain of said transistor at a back side of said substrate comprises:

forming a bit line contact structure on the surface of the drain electrode;

the bit line is formed on the bit line contact structure.

On the other hand, an embodiment of the present application further provides a memory, where the memory includes:

a substrate;

the first isolation structures are located in the substrate and extend along a first direction; the first direction is parallel to the substrate surface; a first thickness of the first isolation structure is less than or equal to a thickness of the substrate;

a plurality of first grooves which are parallel to each other and are positioned in the substrate and extend along a second direction; the second direction is parallel to the substrate surface and perpendicular to the first direction; the first trench and the first isolation structure divide the substrate into a plurality of channel columns;

the word line structure and the second isolation structure are positioned in the first groove; the word line structures and the second isolation structures are arranged in parallel and extend along the side wall of the first groove;

a memory structure located on a surface of the channel pillar adjacent to the word line structure.

In some embodiments, the memory further comprises:

a third isolation structure with a second thickness at the bottom of the first trench; the second thickness is less than the depth of the first trench; the word line structure and the second isolation structure are located above the third isolation structure.

In some embodiments, the memory further comprises:

a first protective layer between the third isolation structure and an inner wall of the first trench;

and the first oxidation layer is positioned between the first protection layer and the inner wall of the first groove.

In some embodiments, the word line structure comprises:

word lines over the third isolation structures;

the gate oxide layer is positioned between the word line and the adjacent channel column;

and the gate protection layer is positioned above the word line.

In some embodiments, the second isolation structure has an air gap therein.

In some embodiments, the channel pillar comprises:

a source of a transistor at a first end of the channel pillar;

a drain of the transistor at the channel pillar second end.

In some embodiments, the storage structure comprises:

and the storage capacitor is positioned on the surface of the source electrode and is connected with the source electrode.

In some embodiments, the memory further comprises:

and the bit line is positioned on the back surface of the substrate and is connected with the drain electrode.

In some embodiments, the memory further comprises:

and the bit line contact structure is positioned on the surface of the drain electrode and is connected with the drain electrode and the bit line.

According to the manufacturing method of the memory provided by the embodiment of the application, the word line structures and the second isolation structures which are arranged in parallel are formed in the first groove, and the storage structures are formed on the surfaces of the adjacent channel columns of the word line structures. Thus, on one hand, by forming the transistors in a vertical arrangement, the area of the memory cell is greatly reduced; on the other hand, different structures connected with the source electrode and the drain electrode in the memory can be respectively designed on two opposite surfaces of the substrate, so that the circuit layout in the memory is simplified, and the process difficulty of manufacturing the memory is reduced.

Drawings

Fig. 1A is a schematic structural diagram of a transistor according to an embodiment of the present disclosure;

fig. 1B is a schematic structural diagram of a transistor according to an embodiment of the present disclosure;

fig. 1C is a schematic diagram of a memory cell according to an embodiment of the present disclosure;

FIG. 1D is a schematic diagram of a memory cell array according to an embodiment of the present disclosure;

fig. 1E to fig. 1G are schematic structural diagrams of a memory cell array according to an embodiment of the present disclosure;

FIG. 2 is a flowchart illustrating a method for manufacturing a memory according to an embodiment of the present disclosure;

fig. 3A to fig. 3G are schematic process diagrams of a method for manufacturing a memory according to an embodiment of the present disclosure;

fig. 4 is a schematic structural diagram of forming a third isolation structure according to an embodiment of the present disclosure;

fig. 5 is a schematic structural diagram of forming a third isolation structure according to an embodiment of the present disclosure;

fig. 6A to fig. 6C are schematic views illustrating a process of forming a third isolation structure according to an embodiment of the present disclosure;

fig. 7 is a flowchart illustrating a process of forming a word line structure and a second isolation structure according to an embodiment of the present disclosure;

fig. 8A to 8F are schematic views illustrating a process of forming a word line structure and a second isolation structure according to an embodiment of the present disclosure;

fig. 9A and 9B are schematic views illustrating a process of forming a first sacrificial layer and a second sacrificial layer according to an embodiment of the present disclosure;

fig. 10A to 10D are schematic views illustrating a process of forming a second trench according to an embodiment of the present disclosure;

fig. 11A to fig. 11E are schematic views illustrating a process of forming a word line structure according to an embodiment of the present disclosure;

fig. 12A and 12B are schematic views illustrating a process of forming a third trench according to an embodiment of the present disclosure;

fig. 13 is a schematic structural diagram of forming a second isolation structure according to an embodiment of the present disclosure;

fig. 14A and fig. 14B are schematic views illustrating a process of forming a third passivation layer according to an embodiment of the present disclosure;

fig. 15 is a schematic structural diagram of forming a source and a drain of a transistor according to an embodiment of the present disclosure;

fig. 16 is a schematic structural diagram of a memory structure formed according to an embodiment of the present application;

fig. 17A and 17B are schematic views illustrating a process of forming a drain of a transistor according to an embodiment of the present disclosure;

FIG. 18 is a schematic diagram illustrating a structure for forming a bit line according to an embodiment of the present invention;

FIG. 19 is a schematic diagram illustrating a structure for forming a bit line contact structure according to an embodiment of the present disclosure;

fig. 20A and fig. 20B are schematic structural diagrams of a memory according to an embodiment of the present disclosure;

fig. 21 is a schematic structural diagram of a third isolation structure in a memory according to an embodiment of the present disclosure;

fig. 22 is a schematic structural diagram of a first protective layer and a first oxide layer in a memory according to an embodiment of the present disclosure;

FIG. 23 is a schematic structural diagram illustrating a word line structure in a memory according to an embodiment of the present disclosure;

FIG. 24 is a schematic structural diagram of an air gap in a memory according to an embodiment of the present disclosure;

fig. 25 is a schematic structural diagram of a third passivation layer in a memory according to an embodiment of the present disclosure;

fig. 26 is a schematic structural diagram of a source and a drain of a transistor in a memory according to an embodiment of the present disclosure;

fig. 27 is a schematic structural diagram of a memory structure in a memory according to an embodiment of the present disclosure;

fig. 28A to 28C are schematic structural diagrams of a storage capacitor in a memory according to an embodiment of the present disclosure;

fig. 29A and 29B are schematic diagrams illustrating an arrangement of storage capacitors in a memory according to an embodiment of the present disclosure;

FIG. 30 is a schematic diagram illustrating a structure of a bit line in a memory according to an embodiment of the present disclosure;

fig. 31 is a schematic structural diagram of a bit line contact structure in a memory according to an embodiment of the present disclosure.

Detailed Description

To facilitate an understanding of the present application, exemplary embodiments disclosed herein will be described in more detail below with reference to the associated drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present application. It will be apparent, however, to one skilled in the art, that the present application may be practiced without one or more of these specific details. In some embodiments, some technical features that are well known in the art are not described in order to avoid confusion with the present application; that is, not all features of an actual embodiment may be described herein, and well-known functions and structures may not be described in detail.

In general, terms may be understood at least in part from the context of their use. For example, the term "one or more" as used herein may be used to describe any feature, structure, or characteristic in the singular or may be used to describe a combination of features, structures, or characteristics in the plural, depending, at least in part, on the context. Similarly, terms such as "a" or "the" may also be understood to convey a singular use or to convey a plural use, depending, at least in part, on the context. Additionally, the term "based on" may be understood as not necessarily intended to convey an exclusive set of factors, and may instead allow for the presence of additional factors that are not necessarily expressly described, again depending at least in part on the context.

Unless otherwise defined, the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

In order to thoroughly understand the present application, detailed steps and detailed structures will be presented in the following description in order to explain the technical solution of the present application. The following detailed description of the preferred embodiments of the present application, however, will suggest that the present application may have other embodiments in addition to these detailed descriptions.

In some embodiments, the transistors of the memory include Planar transistors (Planar) and Buried Channel transistors (BCAT), but structurally, the source and drain are located on both horizontal sides of the gate, whether Planar or Buried Channel transistors.

Fig. 1A is a schematic structural diagram of a planar transistor, and fig. 1B is a schematic structural diagram of a buried channel transistor. It should be understood that the dimensional relationships of the structures may not correspond to the actual structures in order to clearly illustrate the structures in the drawings. The source 101 and the drain 102 of the transistor are respectively located at two sides of the gate 103, so that the source 101 and the drain 102 respectively occupy different positions on a horizontal plane, so that the horizontal area of the transistor is larger regardless of a planar transistor or a buried channel transistor. In addition, since the Capacitor 104 (Capacitor) and the Bit Line 105 (Bit Line, BL) are on the same side of the transistor, they are located on one side of the substrate during the fabrication process. Taking the buried channel transistor as an example, the contact line of the capacitor 104 needs to pass through the bit line 105, so that the overall process complexity is high, and extremely high requirements are imposed on the photolithography process and the alignment.

FIG. 1C is a diagram of a memory cell in the RAM, and FIG. 1D is a diagram of a memory cell array in the RAM. The word line is used for controlling the on-off of the transistor, the bit line is used for reading and writing the capacitor when the transistor is conducted, one end of the capacitor is connected with the transistor, and the other end of the capacitor is grounded.

FIG. 1E is a schematic diagram of the layout of the active regions of the transistors of the memory cell array in some embodiments. As shown in FIG. 1E, the orientation of the active region 210 may be 18-25 degrees from the bit line.

FIG. 1F is a schematic diagram of a memory cell array in some embodiments. As shown in fig. 1F, Word lines 220 (WL) and bit lines 230 are perpendicular to each other, and each active region 210 intersects two Word lines 220 and one bit Line 230.

FIG. 1G is a schematic diagram of a portion of an array of memory cells in some embodiments. As shown in fig. 1G, each active region 210 has two Storage Node Contact structures 211 (SNC) and one Bit Line Contact structure 212 (BLC). Wherein two storage node contact structures 211 are respectively connected to two capacitors, one bit lineThe contact structure 212 is connected to one bit line 230. Thus, a single bit line 230 can control two adjacent capacitors through the switches of two word lines 220, respectively, to perform read and write operations. The unit cell size is 6F when viewed in plan²(F is the minimum physical dimension of the memory cell, F²It means a unit area), the occupied area is large.

As shown in fig. 2, an embodiment of the present application provides a method for manufacturing a memory, where the corresponding structure is as shown in fig. 3A to 3F, and the method includes the following steps:

step S10, providing the substrate 300;

step S20, forming a plurality of mutually parallel first isolation structures 310 extending along a first direction in the substrate 300; the first direction is parallel to the substrate 300 surface; the first thickness of the first isolation structure 310 is less than the thickness of the substrate 300;

step S30, forming a plurality of mutually parallel first trenches 320 extending in a second direction in the substrate 300; the second direction is parallel to the substrate 300 surface and perpendicular to the first direction; the first trench 320 and the first isolation structure 310 divide the substrate 300 into a plurality of channel pillars 330;

step S40, forming a word line structure 340 and a second isolation structure 350 in the first trench 320; wherein the word line structure 340 and the second isolation structure 350 are arranged in parallel and extend along the sidewall of the first trench 320;

in step S50, a memory structure 360 is formed on the surface of the channel pillar 330 adjacent to the word line structure 340.

In the embodiment of the present application, the substrate 300 may be a semiconductor material such as silicon (Si), germanium (Ge), or the like. In some embodiments, the substrate 300 may also be doped, or include doped and undoped regions in the substrate. One surface of the substrate 300 for forming the first trench 320 may be a surface of the substrate 300, and a surface opposite to the surface of the substrate 300 may be a back surface of the substrate 300.

In the embodiment of the present application, a table on a substrate 300 is shown in FIG. 3AA plurality of first isolation structures 310 extending in a first direction are formed on the face. Wherein the first direction is parallel to the surface of the substrate and is consistent with the Y direction; as shown in fig. 3B, a first thickness of the first isolation structure 310 in the Z-direction is less than a thickness of the substrate 300. Optionally, forming a plurality of isolation trenches extending along a first direction on the surface of the substrate 300 by an Etching (Etching) and/or Photolithography (Photolithography) process; a first isolation structure 310 is then formed in the isolation trench by a deposition process. The material of the first isolation structure 310 includes, but is not limited to, silicon dioxide (SiO)₂) Spin-on Dielectrics (SOD), silicon nitride (Si)₃N₄) Silicon oxynitride (SiON). It should be noted that in the embodiment of the present application, the etching on the substrate is a partial etching performed in the Z direction, and the substrate is not etched through by the etching process. Generally, the Etching process can be divided into Dry Etching (Dry Etching) and Wet Etching (Wet Etching). Wherein, the dry Etching may include Ion Milling Etching (Ion Neam Milling Etching), Plasma Etching (Plasma Etching), Reactive Ion Etching (Reactive Ion Etching) or Laser Ablation (Laser Ablation), etc.; wet etching is etching using a solvent or solution, such as an acid-base solution. Deposition processes include, but are not limited to, Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), or Physical Vapor Deposition (PVD), among others.

As shown in fig. 3C, after the first isolation structure 310 is formed, a plurality of first trenches 320 extending in a second direction and parallel to each other may be formed on the surface of the substrate 300 through an etching and/or photolithography process. Wherein the second direction is parallel to the surface of the substrate 300, is coincident with the X direction, and is perpendicular to the first direction. As shown in fig. 3D, the depth of the first trench 320 in the Z direction is less than the thickness of the substrate 300. The first trench 320 and the first isolation structure 310 divide the substrate 300 into a plurality of channel pillars 330. The length direction of the channel pillar 330 coincides with the Z direction so that the channel pillar 330 is close to both ends of the surface and the back surface of the substrate 300, and the source and the drain of the transistor in the memory can be formed, respectively, i.e., the direction of the transistor in the memory is perpendicular to the surface of the substrate. Thus, the vertical transistor occupies a smaller area, and the density of the memory cell per unit area is higher.

As shown in fig. 3E, a word line structure 340 and a second isolation structure 350 are formed within the first trench 320. The word line structures 340 and the second isolation structures 350 are arranged in parallel in the Y direction and extend along the sidewalls of the first trenches 320 in the X direction. The word line structure 340 and the second isolation structure 350 cover two opposite sidewalls of the first trench 320, respectively, and the second isolation structure 350 serves to electrically isolate the word line structure 340 and the channel pillar 330 in an adjacent transistor. Alternatively, sacrificial layers corresponding to the word line structure 340 and the second isolation structure 350 may be formed in the first trench 320, and then the sacrificial layers are sequentially replaced to form the word line structure 340 and the second isolation structure 350. The word line structure 340 may include a word line, a gate oxide layer, a gate protection layer, and the like, wherein the word line is a conductive material including, but not limited to, one or more of tungsten (W), titanium nitride (TiN), copper (Cu), and silver (Ag). The material of the second isolation structure 350 includes, but is not limited to, one or more of silicon dioxide, spin-on dielectric, silicon nitride, and silicon oxynitride.

As shown in fig. 3F, a memory structure 360 is formed on the surface of the channel pillar 330 adjacent to the word line structure 340. The direction of the channel pillar 330 coincides with the Z direction, so that the source and the drain of the transistor can be formed at both ends of the channel pillar 330, respectively, i.e., the direction of the transistor in the memory is perpendicular to the substrate surface. The memory structure 360 may be formed on a surface of either end of the channel pillar 330 to connect to a source or drain of a transistor, and the other end of the channel pillar 330 may be used to form a bit line or the like. In a random access memory, the storage structure 360 may be a capacitor. Therefore, different structures connected with the source electrode and the drain electrode in the memory can be respectively designed on two opposite surfaces of the substrate 300, so that the circuit layout in the memory is simplified, and the process difficulty of manufacturing the memory is reduced.

In some embodiments, as shown in fig. 3G, before forming the first trench 320, a silicon oxide layer and a silicon nitride layer may be sequentially formed on the surface of the substrate 300 through a deposition process to protect the surface of the substrate 300 in a subsequent process.

In some embodiments, as shown in fig. 4, the method further comprises:

forming a third isolation structure 321 with a second thickness at the bottom of the first trench 320; the second thickness is less than the depth of the first trench 320; the word line structure 340 and the second isolation structure 350 are formed over the third isolation structure 321.

In the embodiment of the present application, the third isolation structure 321 may be formed at the bottom of the first trench 320 by a deposition process or the like, and the thickness of the third isolation structure 321 in the Z direction is smaller than the depth of the first trench 320. The word line structure 340 and the second isolation structure 350 are formed above the third isolation structure 321, and the third isolation structure 321 is used for preventing the word line structure 340 from generating a leakage current phenomenon at the bottom of the first trench 320. The material of the third isolation structure 321 includes, but is not limited to, one or more of silicon dioxide, spin-on insulating dielectric, silicon nitride, and silicon oxynitride.

In some embodiments, as shown in fig. 5, the method further comprises:

forming a first oxide layer 322 covering the inner wall of the first trench 320;

forming a first protective layer 323 covering the first oxide layer 322;

the third isolation structure 321 with the second thickness formed at the bottom of the first trench 320 includes:

the third isolation structure 321 is formed in the first trench 320 whose inner wall is covered with the first oxide layer 322 and the first protection layer 323.

In the embodiment of the present application, the first Oxide layer 322 may be formed on the inner wall of the first trench 320 by a deposition process, where the inner wall includes the sidewall and the bottom of the first trench 320, the first Oxide layer 322 may be a line Oxide (line Oxide), and the first Oxide layer 322 may protect the inner wall of the first trench 320 in a subsequent process. Then, a first protective layer 323 covering the first oxide layer 322 is formed by a deposition process, the first protective layer 323 may be silicon nitride or the like, and the first protective layer 323 may serve as a stop layer for subsequent thinning of the substrate 300 from the back side. Illustratively, the first oxide layer 322 and the first protective layer 323 are sequentially formed in the first trench 320 by using an atomic layer deposition method, and then the third isolation structure 321 having a second thickness is formed at the bottom of the first trench 320 whose inner wall is covered with the first oxide layer 322 and the first protective layer 323, and the second thickness is smaller than the depth of the first trench 320.

In some embodiments, as shown in fig. 6A to 6C, the forming the third isolation structure 321 in the first trench 320 whose inner wall is covered with the first oxide layer 322 and the first protection layer 323 includes:

filling an insulating material in the first trench 320 whose inner wall is covered with the first oxide layer 322 and the first protective layer 323;

removing at least a portion of the insulating material, leaving the second thickness of the insulating material at the bottom of the first trench 320 to form the third isolation structure 321;

the first protection layer 323 above the third isolation structure 321 is removed.

In the embodiment of the present application, as shown in fig. 6A, an insulating material may be filled in the first trench 320 whose inner wall is covered with the first oxide layer 322 and the first protection layer 323 by a spin-on insulating dielectric process, where the insulating material may be silicon dioxide, etc., but other suitable processes may also be used. As shown in fig. 6B, a portion of the insulating material may be removed by etching or the like, so that the insulating material with the second thickness remains at the bottom of the first trench 320, thereby forming a third isolation structure 321. As shown in fig. 6C, the first protective layer 323 over the third isolation structure 321 may be removed by selective etching. Since the word line structure 340 is formed above the third isolation structure 321 in the subsequent process, and the first protection layer 323 only serves as a stop layer for thinning the substrate 300 from the back side, accordingly, the first protection layer 323 above the third isolation structure 321 may be removed. Illustratively, phosphoric acid (H) is employed₃PO₄) Selective etching solution such as hydrofluoric acid (HF), etc., can remove the first protection layer 323 of silicon nitride material without contacting the first oxide layer 322 and the silicon dioxide material in the third isolation structure 321.

In some embodiments, as shown in fig. 7, the forming of the word line structure 340 and the second isolation structure 350 in the first trench 320 includes the following steps, and the corresponding structures are shown in fig. 8A to 8F:

step S401: forming the third isolation structure 321 at the bottom of the first trench 320;

step S402: forming a first sacrificial layer 324 covering a first sidewall of the first trench 320 and a second sacrificial layer 325 covering a second sidewall of the first trench 320 over the third isolation structure 321; wherein the first sidewall and the second sidewall are different sidewalls opposite to each other in the first trench 320;

step S403: forming a spacer layer 326 between said first sacrificial layer 324 and said second sacrificial layer 325;

step S404: removing the first sacrificial layer 324 to form a second trench 327;

step S405: forming the word line structure 340 in the second trench 327;

step S406: removing the second sacrificial layer 325 to form a third trench 328;

step S407: the second isolation structure 350 is formed in the third trench 328.

In the embodiment of the present application, as shown in fig. 8A, first sacrificial layer 324 and second sacrificial layer 325 may be formed over third isolation structure 321 by an atomic layer deposition process, and first sacrificial layer 324 and second sacrificial layer 325 may be a Polycrystalline Silicon (Poly-Si) material. The first sacrificial layer 324 covers a first sidewall of the first trench 320, the second sacrificial layer 325 covers a second sidewall of the first trench 320, and the first sidewall and the second sidewall are two sidewalls of the first trench 320 opposite to each other in the Y direction. First sacrificial layer 324 and second sacrificial layer 325 are separated from each other with a gap between first sacrificial layer 324 and second sacrificial layer 325. The first sacrificial layer 324 and the second sacrificial layer 325 are used to form a word line structure 340 and a second isolation structure 350 arranged side by side in the first trench 320 and extending in the X direction.

As shown in fig. 8B, a spacer 326 may be formed in a gap between the first sacrificial layer 324 and the second sacrificial layer 325 by a deposition process, etc., and the spacer 326 may be made of silicon dioxide, etc. for protecting the second sacrificial layer 325 during the subsequent processes of removing the first sacrificial layer 324 and forming the word line structure 340.

As shown in fig. 8C, the first sacrificial layer 324 may be removed by etching or the like to form a second trench 327, and the second trench 327 is used to form the word line structure 340.

As shown in fig. 8D, a word line structure 340 may be formed in the second trench 327 by a deposition process or the like. The word line structure 340 may include a word line, a gate oxide layer, a gate protection layer, and the like, wherein the word line is a conductive material including, but not limited to, one or more of tungsten (W), titanium nitride (TiN), copper (Cu), and silver (Ag).

As shown in fig. 8E, the second sacrificial layer 325 may be removed by etching or the like to form a third trench 328, and the third trench 328 is used to form a second isolation structure 350.

As shown in fig. 8F, a second isolation structure 350 may be formed in the third trench 328 by a deposition or the like process. The second isolation structure 350 serves to electrically isolate the word line structure 340 from the channel pillar 330 in an adjacent transistor. The material of the second isolation structure 350 includes, but is not limited to, one or more of silicon dioxide, spin-on insulating dielectric, silicon nitride, and silicon oxynitride.

In some embodiments, as shown in fig. 9A and 9B, the forming a first sacrificial layer 324 covering a first sidewall of the first trench 320 and forming a second sacrificial layer 325 covering a second sidewall of the first trench 320 includes:

forming a sacrificial layer 329 covering the inner wall of the first trench 320 in the first trench 320;

a portion of the sacrificial layer 329 on the upper surface of the third isolation structure 321 is removed to form the first sacrificial layer 324 and the second sacrificial layer 325 which are separated from each other.

In the embodiment of the present application, as shown in fig. 9A, a sacrificial layer 329 covering the inner wall of the first trench 320 and extending in the X direction may be formed by a deposition process or the like. Where the inner walls include the first sidewall and the second sidewall of the first trench 320 and the upper surface of the third isolation structure 321, the sacrificial layer 329 may be a polysilicon material.

As shown in fig. 9B, a portion of the sacrificial layer 329 on the upper surface of the third isolation structure 321 may be removed by a dry etching process, so that the sacrificial layers 329 on the first and second sidewalls are separated from each other, thereby forming the first and second

sacrificial layers

324 and 325. The first sacrificial layer 324 and the second sacrificial layer 325 are used to form a word line structure 340 and a second isolation structure 350 arranged in parallel in the first trench 320 and extending in the X direction.

In some embodiments, as shown in fig. 10A-10D, the removing the first sacrificial layer 324 and forming the second trench 327 includes:

forming a fourth groove 3251 on an end of the second sacrificial layer 325 near the surface of the substrate 300;

forming a second protective layer 3252 in the fourth groove 3251 to cover the second sacrificial layer 325;

the first sacrificial layer 324 is removed to form the second trench 327.

In the embodiment of the present application, as shown in fig. 10A, a fourth groove 3251 may be formed on one end of the second sacrificial layer 325 close to the substrate 300 by an etching and/or photolithography process, the fourth groove 3251 is used to form the second protection layer 3252, and a projection of the fourth groove 3251 on the XY plane completely covers the second sacrificial layer 325.

As shown in fig. 10B, a second protection layer 3252 covering the second sacrificial layer 325 may be formed in the fourth groove 3251 by deposition or the like, and the second protection layer 3252 may be made of silicon dioxide or the like. Second protective layer 3252 and spacer layer 326 completely separate first sacrificial layer 324 from second sacrificial layer 325, thereby protecting second sacrificial layer 325 during subsequent removal of first sacrificial layer 324 and formation of word line structure 340.

It should be noted that, since the fourth trench 3251 has a height difference with the surface of the substrate 300, after the second protection layer 3252 is deposited and formed, as shown in fig. 10C, the surfaces of the second protection layer 3252 and the substrate 300 may have an uneven phenomenon, which affects the subsequent processes. Optionally, after the second protection layer 3252 is deposited, the surface of the substrate 300 may be planarized, such as Chemical Mechanical Polishing (CMP), to remove excess semiconductor material.

As shown in fig. 10D, the first sacrificial layer 324 may be removed by etching or the like to form a second trench 327, and the second trench 327 is used to form the word line structure 340.

In some embodiments, as shown in fig. 11A-11E, the forming the word line structure 340 in the second trench 327 includes:

removing the spacer layer 326 and the first oxide layer 322 in the second trench 327;

forming a gate oxide layer 341 on the sidewall of the second trench 327;

filling the second trench 327 with a conductive material;

removing at least a portion of the conductive material to form a word line 342 having a third thickness, the third thickness being less than the depth of the second trench 327;

filling an insulating material on the word line 342 in the second trench 327 to form a gate protection layer 343; wherein the word line structure 340 includes the gate oxide 341, the word line 342, and the gate protection layer 343.

In the embodiment of the present application, as shown in fig. 11A, in order to form a gate oxide layer with a target thickness and a good quality on the sidewall of the second trench 327, the spacer 326 and a portion of the first oxide layer 322 in the second trench 327 above the third isolation structure 321 may be removed by etching or the like, so as to expose the adjacent channel pillar 330 and the second sacrificial layer 325, so as to form a gate oxide layer on the sidewall of the second trench 327 by performing an oxidation process. Optionally, after removing the spacer 326 and a portion of the first oxide layer 322, a wet cleaning process is performed to remove the residual contaminants inside the second trench 327.

As shown In fig. 11B, a gate oxide layer 341 of a target thickness may be formed on the sidewalls of the second trench 327 through a Thermal Oxidation process, which may be In-Situ Steam generation (ISSG), Rapid Thermal Oxidation (RTO), or the like. It is noted that the gate oxide layer 341 is located on the sidewalls of the second trench 327 adjacent to the adjacent channel pillar 330. The oxide layer on the sidewalls of the second trench 327 adjacent to the second sacrificial layer 325 is used to protect the word line structure 340 during the subsequent removal of the second sacrificial layer 325.

As shown in fig. 11C, a conductive material may be filled in the second trench 327 having the gate oxide layer 341 by a deposition process or the like to form a word line. The conductive material includes, but is not limited to, one or more of tungsten, titanium nitride, copper, and silver.

As shown in fig. 11D, at least a portion of the conductive material may be removed by etching or the like to form a word line 342 with a third thickness, wherein the third thickness of the word line 342 is smaller than the depth of the second trench 327, so as to form a gate protection layer above the word line 342.

As shown in fig. 11E, an insulating material may be filled above the word line 342 by a deposition process or the like to form a gate protection layer 343. Optionally, the insulating material may be silicon nitride. The gate protection layer 343 prevents a leakage current from occurring at an end of the word line 342 near the surface of the substrate 300, and protects the word line 342 in a subsequent process.

The word line structure 340 includes the gate oxide layer 341, the word line 342, and the gate protection layer 343 described above.

In some embodiments, as shown in fig. 12A and 12B, the removing the second sacrificial layer 325 and forming a third trench 328 includes:

removing the second protective layer 3252;

the second sacrificial layer 325 is removed to form the third trench 328.

In the embodiment of the present application, as shown in fig. 12A, the surface of the substrate 300 may be processed by a chemical mechanical polishing process or the like to remove the second protection layer 3252, and an excess semiconductor material remained on the surface of the substrate 300 after the word line structure 340 is formed, so as to expose an end of the second sacrificial layer 325 on the surface of the substrate 300, and form an opening for removing the second sacrificial layer 325.

As shown in fig. 12B, the second sacrificial layer 325 may be removed by etching or the like to form a third trench 328. The third trench 328 is used to form a second isolation structure 350.

In some embodiments, as shown in fig. 13, the forming the second isolation structure 350 in the third trench 328 includes:

the third trench 328 is filled with an insulating material to form the second isolation structure 350 having an Air Gap 351 (Air Gap) therebetween.

In the embodiment of the present application, as shown in fig. 13, the third trench 328 may be filled with an insulating material by a deposition process or the like, and a second isolation structure 350 having an air gap 351 in the middle may be formed by an etching process or the like. The length of the air gap 351 in the Z direction is equal to or greater than the third thickness of the word line 342. Optionally, the insulating material may be silicon dioxide. The air gap 351 may improve the dielectric properties of the second isolation structure 350, thereby improving the performance of the semiconductor device.

In some embodiments, as shown in fig. 14A and 14B, after the forming the second isolation structure 350 with the air gap 351 in the middle, the method further includes:

forming a fifth trench 352 at an end of the second isolation structure 350 close to the surface of the substrate 300;

an insulating material is filled in the fifth trench 352 to form a third protection layer 353.

In the embodiment of the present application, as shown in fig. 14A, a fifth trench 352 may be formed at an end of the second isolation structure 350 close to the surface of the substrate 300 by etching or the like. Wherein the fifth trench 352 is not communicated with the air gap 351, and the fifth trench 352 is used to form the third protective layer 353.

As shown in fig. 14B, the fifth trench 352 may be filled with an insulating material by deposition or the like to form a third protection layer 353. The insulating material may be silicon nitride or the like. The third protective layer 353 may protect the air gap 351 and improve dielectric properties of the second isolation structure 350. Since the surface of the substrate 300 may be uneven after the third protective layer 353 is formed, the surface of the substrate 300 may be optionally planarized by a chemical mechanical polishing process.

In some embodiments, as shown in fig. 15, the method further comprises:

doping a first end of the channel column 330 to form a source 331 of a transistor;

the second end of the channel pillar 330 is doped to form the drain 332 of the transistor.

In the embodiment of the present application, as shown in fig. 15, the first end and the second end of the channel pillar 330 may be doped through an ion implantation (Implant) process to form a source 331 and a drain 332 of the transistor. Wherein the first end and the second end are two ends of the channel pillar 330 opposite in the Z direction. It is understood that the first end may be an end of the channel pillar 330 near the surface of the substrate 300, or an end of the channel pillar 330 near the back surface of the substrate 300.

In some embodiments, since the surface of the substrate 300 has a residual material such as a silicon oxide layer, a silicon nitride layer, etc., after the source electrode 331 and/or the drain electrode 332 of the transistor are formed, the residual material needs to be removed by etching, chemical mechanical polishing, etc. to expose the source electrode 331 and/or the drain electrode 332.

In some embodiments, as shown in fig. 16, the forming a memory structure 360 on the surface of the channel pillar 330 adjacent to the word line structure 340 includes:

a storage capacitor 361 is formed on a surface of the source 331 adjacent to the word line structure 340.

In the embodiment of the present application, as shown in fig. 16, the source 331 adjacent to the word line structure 340 refers to the source 331 in the channel pillar 330 near one side of the gate oxide 341. It is understood that the storage capacitor 361 can be formed on the surface of the source electrode 331 or the surface of the drain electrode 332. One end of the storage capacitor 361 is connected to the source 331 or the drain 332, and the other end is grounded.

In some embodiments, as shown in fig. 17A and 17B, the doping the second end of the channel pillar 330 to form the drain 332 of the transistor includes:

thinning the back side of the substrate 300 until the third isolation structure 321 is exposed;

the second end of the channel pillar 330 adjacent to the third isolation structure 321 is doped to form a drain 332 of the transistor.

In the embodiment of the present application, as shown in fig. 17A, the back surface of the substrate 300 is thinned by using a chemical mechanical polishing process or the like until the first protection layer 323 at the bottom of the third isolation structure 321 is exposed, and the first protection layer 323 can be used as a stop layer of the chemical mechanical polishing process.

As shown in fig. 17B, a drain 332 of the transistor is formed by doping a second end of the channel pillar 330 adjacent to the third isolation structure 321 through an ion implantation (implantation) process, where the second end refers to an end of the channel pillar 330 near the back surface of the substrate 300. It is understood that the source 331 of the transistor may also be formed at the end of the channel pillar 330 near the back side of the substrate 300.

In some embodiments, as shown in fig. 18, the method further comprises:

on the back side of the substrate 300, a bit line 370 is formed connecting the drain 332 of the transistor.

In the embodiment of the present application, as shown in fig. 18, a bit line 370 connected to the drain 332 of the transistor is formed on the back surface of the substrate 300, and the bit line 370 is a conductive material. When the word line 342 controls conduction between the source 331 and the drain 332, the bit line 370 performs data reading and writing operations on the storage capacitor 361. It can be understood that the bit line 370 and the storage capacitor 361 are respectively formed on two opposite surfaces of the substrate 300, thereby simplifying the circuit layout inside the memory and reducing the process difficulty of manufacturing the memory.

In some embodiments, as shown in fig. 19, the forming a bit line 370 connected to the drain 332 of the transistor on the back side of the substrate 300 includes:

forming a bit line contact structure 371 on the surface of the drain 332;

the bit line 370 is formed on the bit line contact 371.

In the embodiment of the present application, as shown in fig. 19, a bit line contact structure 371 is formed on the surface of the drain 332, and a bit line 370 is formed on the bit line contact structure 371. The bit line contact 371 is a conductive material for connecting the drain 332 to the bit line 370.

As shown in fig. 20A and 20B, an embodiment of the present application further provides a memory 40, where the memory 40 includes:

a substrate 400;

a plurality of first isolation structures 410 located in the substrate 400 and extending in a first direction, the first isolation structures being parallel to each other; the first direction is parallel to the substrate 400 surface; the first thickness of the first isolation structure 410 is less than or equal to the thickness of the substrate 400;

a plurality of first trenches 420 located in the substrate 400 and extending in a second direction, the first trenches being parallel to each other; the second direction is parallel to the substrate 400 surface and perpendicular to the first direction; the first trench 420 and the first isolation structure 410 divide the substrate into a plurality of channel pillars 430;

a word line structure 440 and a second isolation structure 450 located within the first trench 420; wherein the word line structure 440 and the second isolation structure 450 are arranged in parallel and extend along the sidewall of the first trench 420;

a memory structure 460 located on a surface of the channel pillar 430 adjacent to the word line structure 440.

In the embodiment of the present application, the substrate 400 may be a semiconductor material such as silicon (Si), germanium (Ge), or the like. In some embodiments, the substrate 400 may also be doped, or include doped and undoped regions in the substrate 400. The surface of the substrate 400 where the first trench 420 is located may be a surface of the substrate 400, and a surface opposite to the surface of the substrate 400 may be a back surface of the substrate 400.

As shown in fig. 20A, the first isolation structure 410 is located on the surface of the substrate 400 and extends along the first direction. Wherein the first direction is parallel to the surface of the substrate 400, coinciding with the Y-direction. A first thickness of the first isolation structure 410 in the Z-direction is less than or equal to a thickness of the substrate 400. The storage structure 460 is not shown in fig. 20A.

As shown in fig. 20A, the first trench 420 is located on the surface of the substrate 400 and extends along the second direction. Wherein the second direction is parallel to the surface of the substrate 400, is coincident with the X-direction, and is perpendicular to the first direction. As shown in fig. 20B, the depth of the first trench 420 in the Z direction is less than or equal to the thickness of the substrate 400. The first trench 420 and the first isolation structure 410 divide the substrate 400 into a plurality of channel pillars 430. The length direction of the channel pillar 430 is the same as the Z direction, so that the channel pillar 430 is close to both ends of the surface and the back surface of the substrate 400, and the source and the drain of the transistor in the memory can be formed respectively, that is, the direction of the transistor in the memory is perpendicular to the surface of the substrate 400. Thus, the vertical transistor occupies a smaller area, and the density of the memory cell per unit area is higher.

As shown in fig. 20A, the word line structure 440 and the second isolation structure 450 are juxtaposed in the Y direction and extend along the sidewall of the first trench 420 in the X direction. As shown in fig. 20B, the word line structure 440 and the second isolation structure 450 respectively cover two opposite sidewalls of the first trench 420, and the second isolation structure 450 serves to electrically isolate the word line structure 440 and the channel pillar 430 in the adjacent transistor. The word line structure 440 may include a word line, a gate oxide layer, a gate protection layer, and the like, wherein the word line is a conductive material including, but not limited to, one or more of tungsten (W), titanium nitride (TiN), copper (Cu), and silver (Ag). The material of the second isolation structure 450 includes, but is not limited to, one or more of silicon dioxide, spin-on dielectric, silicon nitride, and silicon oxynitride.

As shown in fig. 20B, a memory structure 460 is located on the surface of the channel pillar 430 adjacent to the word line structure 440. It is understood that the memory structure 460 may be located on the surface of either end of the channel pillar 430 and connected to the source or drain of the transistor, and the other end of the channel pillar 430 may be connected to a bit line, etc. In a random access memory, the storage structure 460 may be a capacitor. Therefore, different structures connected with the source electrode and the drain electrode in the memory can be respectively designed on two opposite surfaces of the substrate 400, so that the circuit layout in the memory is simplified, and the process difficulty of manufacturing the memory is reduced.

In some embodiments, as shown in fig. 21, the memory further comprises:

a third isolation structure 421 having a second thickness at the bottom of the first trench 420; the second thickness is less than the depth of the first trench 420; the word line structure 440 and the second isolation structure 450 are located above the third isolation structure 421.

In the embodiment of the present application, the third isolation structure 421 is located at the bottom of the first trench 420, and the thickness of the third isolation structure 421 in the Z direction is smaller than the depth of the first trench 420. The word line structure 440 and the second isolation structure 450 are located above the third isolation structure 421, and the third isolation structure 421 is used to prevent the word line structure 440 from leaking current at the bottom of the first trench 420. The material of the third isolation structure 421 includes, but is not limited to, one or more of silicon dioxide, spin-on insulating dielectric, silicon nitride, and silicon oxynitride.

In some embodiments, as shown in fig. 22, the memory further comprises:

a first protective layer 423 between the third isolation structure 421 and an inner wall of the first trench 420;

and a first oxide layer 422 between the first protective layer 423 and an inner wall of the first trench 420.

In the embodiment of the present application, the first protection layer 423 is located between the third isolation structure 421 and the inner wall of the first trench 420, and the first protection layer 423 may be made of silicon nitride or the like; the first oxide layer 422 is located between the first protection layer 423 and the inner wall of the first trench 420, and the first oxide layer 422 may be a linear oxide layer. The first protection layer 423 and the first oxide layer 422 can improve the dielectric property of the third isolation structure 421, and prevent the word line structure 440 from generating a leakage current at the bottom of the first trench 420.

In some embodiments, as shown in fig. 23, the word line structure 440 includes:

a word line 442 located over the third isolation structure 421;

a gate oxide layer 441 between the word line 442 and the adjacent channel pillar 430;

a gate protection layer 443 over the word line 442.

In the embodiment of the present application, the word line structure 440 includes: word line 442, gate oxide layer 441, and gate protective layer 443. The word line 442 is located above the third isolation structure 421, the top end of the word line 442 is lower than the surface of the substrate 400, and the word line 442 is made of a conductive material, including but not limited to one or more of tungsten, titanium nitride, copper, and silver.

A gate oxide layer 441 is positioned between the word line 442 and the adjacent channel pillar 430, and the gate oxide layer 441 may be formed by performing a thermal oxidation process on sidewalls of the first trench 420.

The gate passivation layer 443 covers the word line 442, and the gate passivation layer 443 may be a silicon nitride material to prevent a leakage current from occurring at one end of the word line 442 near the surface of the substrate 400.

In some embodiments, as shown in fig. 24, the second isolation structure 450 has an air gap 451 therein.

In the present embodiment, the second isolation structure 450 has an air gap 451 therein. The second isolation structure 450 may be an insulating material such as silicon dioxide; the length of the air gap 451 in the Z direction is greater than or equal to the length of the word line 442 in the Z direction, and the air gap 451 can improve the dielectric property of the second isolation structure 450, thereby improving the performance of the semiconductor device.

In some embodiments, as shown in fig. 25, the second isolation structure 450 further comprises:

and a third passivation layer 453 over the air gap 451.

In the embodiment of the present application, the third protection layer 453 is disposed above the air gap 451, and the third protection layer 453 may be an insulating material such as silicon nitride, for protecting the air gap 451 and improving the dielectric property of the second isolation structure 450.

In some embodiments, as shown in fig. 26, the channel post 430 includes:

a source 431 of a transistor at a first end of the channel pillar 430;

a drain 432 of the transistor at a second end of the channel pillar 430.

In the embodiment of the present application, the source 431 and the drain 432 of the transistor are respectively located at two ends of the channel pillar 430 opposite in the Z direction. It is understood that the source 431 of the transistor can be located at either the end of the channel pillar 430 near the surface of the substrate 400 or the end of the channel pillar 430 near the back surface of the substrate 400.

In some embodiments, as shown in FIG. 27, the storage structure 460 comprises:

and a storage capacitor 461 located on the surface of the source 431 and connected to the source 431.

In the embodiment of the present application, the storage capacitor 461 is located on the surface of the source 431 and connected to the source 431 for storing the written data. It is understood that the storage capacitor 461 can be located on the surface of the source 431 or the surface of the drain 432. One end of the storage capacitor 461 is connected to the source 431 or the drain 432, and the other end is grounded.

In some embodiments, as shown in fig. 28A to 28C, the storage capacitor 461 includes but is not limited to: cup-shaped (Cup-Type), Cylinder-shaped (Cylinder-Type), and Pillar-shaped (pilar-Type) capacitors.

In the embodiment of the present application, as shown in fig. 28A, a structural diagram of a cup-shaped capacitor is shown, in which the lower electrode 4611 is in a cup shape opened upward, and the upper electrode 4612 is located inside the lower electrode 4611.

Fig. 28B is a schematic structural view of a cylindrical capacitor, in which the lower electrode 4611 is in the shape of a cup which is open upward; the upper electrode 4612 surrounds the inside and outside of the lower electrode 4611.

Fig. 28C is a schematic structural view of a cylindrical capacitor, in which the lower electrode 4611 is cylindrical, and the upper electrode 4612 surrounds and is open downward to the lower electrode 4611.

The upper electrode 4612 and the lower electrode 4611 are both conductive materials, including metals and metal nitride materials, such as one or more of tungsten, nickel, tantalum nitride, and titanium nitride; the capacitor dielectric layer 4613 is a high-K dielectric material such as titanium oxide, zirconium oxide, hafnium oxide, etc.

In some embodiments, as shown in fig. 29A and 29B, the arrangement of the storage capacitor 461 on the surface of the substrate 400 includes, but is not limited to: square arrangement and hexagonal arrangement.

In the embodiment of the present application, as shown in fig. 29A, which is a schematic diagram that the storage capacitors 461 are arranged in a square on the surface of the substrate 400, the pitch of each storage capacitor 461 in the X and Y directions may be equal to the pitch of each channel pillar 430. The center of the storage capacitor 461 in the XY plane may be offset from the center of the channel pillar 430.

As shown in fig. 29B, which is a schematic diagram of the storage capacitors 461 arranged in a hexagonal shape on the surface of the substrate 400, two adjacent rows of the storage capacitors 461 may be arranged in a staggered manner along the X direction.

In some embodiments, the cross-sectional shape of the storage capacitor 461 in the Z-direction may be elliptical, and the axis of the elliptical cross-section of the storage capacitor 461 is not parallel to the X-direction, so as to reduce the area occupied by the capacitor.

In some embodiments, as shown in fig. 30, the memory further comprises:

a bit line 470 on the back side of the substrate 400, the bit line 470 connecting the drain 432.

In the embodiment of the present application, the bit line 470 is located on the back side of the substrate 400 and connected to the drain 432, and the bit line 470 is a conductive material. When the word line 442 controls conduction between the source 431 and the drain 432, the bit line 470 performs data reading and writing operations on the storage capacitor 461. It can be understood that the bit line 470 and the storage capacitor 461 are formed on two opposite sides of the substrate 400, so as to simplify the circuit layout inside the memory and reduce the difficulty of the memory manufacturing process.

In some embodiments, as shown in fig. 31, the memory further comprises:

a bit line contact structure 471 at a surface of the drain 432, the bit line contact structure 471 connecting the drain 432 and the bit line 470.

In the embodiment of the present application, a bit line contact structure 471 is located on the surface of the drain electrode 432, and the bit line contact structure 471 is a conductive material and connects the bit line 470 and the drain electrode 432.

It should be noted that the embodiments provided in the present application can be applied to Random Access Memory (RAM), Dynamic Random Access Memory (DRAM), Ferroelectric Random Access Memory (FRAM), Phase Change Random Access Memory (PCRAM), Magnetic Random Access Memory (MRAM), and the like.

It should be noted that the features disclosed in the several method or apparatus embodiments provided in the present application may be combined arbitrarily to obtain new method or apparatus embodiments without conflict.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A method of manufacturing a memory, the method comprising:

providing a substrate;

forming a plurality of first grooves which extend along a second direction and are parallel to each other in the substrate; the second direction is parallel to the substrate surface and perpendicular to the first direction; the first trench and the first isolation structure divide the substrate into a plurality of channel columns; wherein the first trench has opposing first and second sidewalls;

forming a storage structure on the surface of the channel column adjacent to the word line structure;

wherein, the forming of the word line structure and the second isolation structure in the first trench includes:

forming a first sacrificial layer covering the first sidewall and a second sacrificial layer covering the second sidewall;

removing the first sacrificial layer, and forming a word line structure at the position where the first sacrificial layer is removed;

and removing the second sacrificial layer, and forming a second isolation structure at the position where the second sacrificial layer is removed.

2. The method of claim 1, further comprising:

forming a third isolation structure with a second thickness at the bottom of the first trench; the second thickness is less than the depth of the first trench; the word line structure and the second isolation structure are formed over the third isolation structure.

3. The method of claim 2, further comprising:

forming a first oxide layer covering the inner wall of the first groove;

forming a first protective layer covering the first oxide layer;

4. The method of claim 3, wherein forming the third isolation structure in the first trench having the inner wall covered with the first oxide layer and the first protection layer comprises:

removing at least part of the insulating material to enable the bottom of the first trench to remain a second thickness of the insulating material so as to form a third isolation structure;

and removing the first protective layer above the third isolation structure.

5. The method of claim 4, wherein forming a word line structure and a second isolation structure within the first trench comprises:

forming a first sacrificial layer covering a first sidewall of the first trench and a second sacrificial layer covering a second sidewall of the first trench over the third isolation structure;

removing the first sacrificial layer to form a second groove;

forming the word line structure in the second trench;

removing the second sacrificial layer to form a third groove;

forming the second isolation structure in the third trench.

6. The method of claim 5, wherein forming a first sacrificial layer covering a first sidewall of the first trench and forming a second sacrificial layer covering a second sidewall of the first trench comprises:

7. The method of claim 5, wherein the removing the first sacrificial layer to form a second trench comprises:

and removing the first sacrificial layer to form the second groove.

8. The method of claim 7, wherein the removing the second sacrificial layer to form a third trench comprises:

removing the second protective layer;

and removing the second sacrificial layer to form the third groove.

9. The method of claim 5, wherein forming the word line structure in the second trench comprises:

removing the first oxide layer in the spacing layer and the second groove;

forming a gate oxide layer on the side wall of the second groove;

filling a conductive material in the second trench;

10. The method of claim 5, wherein said forming the second isolation structure in the third trench comprises:

11. The method of claim 2, further comprising:

12. The method of claim 11, wherein forming a storage structure on a surface of the channel pillar adjacent to the word line structure comprises:

13. The method of claim 11, wherein doping the second end of the channel pillar to form a drain of the transistor comprises:

14. The method of claim 13, further comprising:

15. The method of claim 14, wherein forming a bit line connecting the drain of the transistor on the back side of the substrate comprises:

forming a bit line contact structure on the surface of the drain electrode;

the bit line is formed on the bit line contact structure.

16. A memory, comprising:

a substrate;

a plurality of first grooves which are parallel to each other and are positioned in the substrate and extend along a second direction; the second direction is parallel to the substrate surface and perpendicular to the first direction; the first trench and the first isolation structure divide the substrate into a plurality of channel columns; wherein the first trench has opposing first and second sidewalls;

a memory structure located on a surface of the channel pillar adjacent to the word line structure;

wherein the forming of the word line structure and the second isolation structure comprises:

removing the first sacrificial layer, and forming the word line structure at the position of removing the first sacrificial layer;

and removing the second sacrificial layer, and forming the second isolation structure at the position where the second sacrificial layer is removed.

17. The memory of claim 16, further comprising:

a third isolation structure having a second thickness at the bottom of the first trench; the second thickness is less than the depth of the first trench; the word line structure and the second isolation structure are located above the third isolation structure.

18. The memory of claim 17, further comprising:

19. The memory of claim 17, wherein the word line structure comprises:

word lines over the third isolation structures;

and the gate protection layer is positioned above the word line.

20. The memory of claim 17, wherein the second isolation structure has an air gap therein.

21. The memory of claim 16, wherein the channel pillar comprises:

a source of a transistor at a first end of the channel pillar;

a drain of the transistor at the channel pillar second end.

22. The memory of claim 21, wherein the storage structure comprises:

and the storage capacitor is positioned on the surface of the source electrode and connected with the source electrode.

23. The memory of claim 21, further comprising:

24. The memory as recited in claim 23, further comprising: