CN113629054A - U-shaped transistor array and forming method thereof, semiconductor device and forming method thereof - Google Patents

U-shaped transistor array and forming method thereof, semiconductor device and forming method thereof Download PDF

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Publication number
CN113629054A
CN113629054A CN202110748780.8A CN202110748780A CN113629054A CN 113629054 A CN113629054 A CN 113629054A CN 202110748780 A CN202110748780 A CN 202110748780A CN 113629054 A CN113629054 A CN 113629054A
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shaped
forming
drain
transistor
wafer
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骆中伟
华文宇
丁潇
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ICLeague Technology Co Ltd
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ICLeague Technology Co Ltd
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
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    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
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    • H10B—ELECTRONIC MEMORY DEVICES
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    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
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    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
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    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/488—Word lines

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Abstract

The embodiment of the application provides a U-shaped transistor array and a forming method thereof, a semiconductor device and a forming method thereof, wherein the U-shaped transistor array comprises a plurality of U-shaped transistors which are arranged along a first direction and a second direction respectively; wherein each U-shaped transistor comprises: a channel region; a source electrode positioned at a first end of the channel region; the drain electrode is positioned at the second end of the channel region, wherein the first end and the second end are two opposite ends of the channel region in the third direction respectively; the first end and the second end have different sizes in the first direction; the source electrode, the channel region and the drain electrode form a U-shaped structure; the channel region is positioned on any side of the grid electrode; a gate oxide layer between the channel region and the gate; the plane formed by the first direction and the second direction is vertical to the third direction; the third direction is a thickness direction of the wafer forming the channel region.

Description

U-shaped transistor array and forming method thereof, semiconductor device and forming method thereof
Technical Field
The present application relates to the field of semiconductor technology, and more particularly, but not exclusively, to a U-shaped transistor array and a method for forming the same, and a semiconductor device and a method for forming the same.
Background
Transistor arrays are widely used as switching devices or driving devices in semiconductor electronic devices. For example, each transistor in the transistor array may be used in a Dynamic Random Access Memory (DRAM) for controlling a capacitance in each Memory cell.
The related art Transistor Array mainly includes a planar (planar) Transistor Array and a Buried Channel Array (BCAT) Transistor Array, however, in both the planar Transistor Array and the Buried Channel Transistor Array, the Source (S) and the Drain (Drain, D) are located on two horizontal sides of the Gate (Gate, G), and the Source and the Drain occupy different positions respectively, so that the area of the Transistor Array is large. In addition, as the integration of semiconductor devices is continuously increased, the sizes of transistors are made smaller and smaller, which is limited by the influence of the channel sizes of the planar transistors in the planar transistor array and the buried transistors in the buried transistor array, and the transistor array in the related art cannot bear high current.
Disclosure of Invention
Embodiments of the present application provide a U-shaped transistor array and a method of forming the same, a semiconductor device and a method of forming the same.
In a first aspect, an embodiment of the present application provides a U-shaped transistor array, including:
a plurality of U-shaped transistors arranged in a first direction and a second direction, respectively; wherein each of the U-shaped transistors includes:
a channel region;
a source electrode positioned at a first end of the channel region;
the drain electrode is positioned at a second end of the channel region, wherein the first end and the second end are two opposite ends of the channel region in a third direction respectively; the first end and the second end are different in size in the first direction; the source electrode, the channel region and the drain electrode form a U-shaped structure;
the channel region is positioned on any side of the grid electrode;
the grid oxide layer is positioned between the channel region and the grid;
a plane formed by the first direction and the second direction is perpendicular to the third direction; the third direction is a thickness direction of a wafer on which the channel region is formed.
In some embodiments, in the second direction, the gates of each of the U-shaped transistors in the array of U-shaped transistors are connected to each other.
In some embodiments, each of the U-shaped transistors further comprises: an isolation layer;
the isolation layer is located on the surface of the grid electrode, and in the second direction, the isolation layer of each U-shaped transistor in the U-shaped transistor array is connected with each other.
In some embodiments, the gate oxide layer is also located between the isolation layer and the source or the drain.
In some embodiments, the angle between the first direction and the second direction is 0-90 degrees.
In a second aspect, embodiments of the present application provide a semiconductor device, including: memory cells, word lines and bit lines; the memory cell comprises at least the U-shaped transistor array of the preceding claims; the U-shaped transistor array comprises a plurality of U-shaped transistors which are arranged along a first direction and a second direction respectively; wherein each U-shaped transistor at least comprises: a gate, a source and a drain;
the word line extending along the second direction is connected with the gate of each U-shaped transistor, and is used for providing a word line voltage and controlling each U-shaped transistor to be switched on or switched off through the word line voltage;
the bit line extending along the first direction is connected with a source or a drain of each U-shaped transistor, and the bit line is used for performing reading or writing operation on the memory unit when each U-shaped transistor is conducted.
In some embodiments, the memory cell further comprises: a storage capacitor corresponding to each U-shaped transistor;
one end of each storage capacitor is connected with the source electrode or the drain electrode of one U-shaped transistor, the other end of each storage capacitor is grounded, and the storage capacitors are used for storing data written into the memory units.
In some embodiments, the semiconductor device includes, but is not limited to, any of: a dynamic random access memory, a ferroelectric memory, a phase change memory, a magneto-resistive memory, or a resistive memory.
In a third aspect, an embodiment of the present application provides a method for forming a U-shaped transistor array, where the method includes:
providing a wafer, wherein the wafer comprises a plurality of silicon column rows arranged along a first direction, and each silicon column row comprises a plurality of silicon columns arranged along a second direction; a first insulating layer is filled between any two adjacent silicon columns;
determining every two adjacent silicon column columns as a transistor column in sequence;
etching the first insulating layer between two silicon column columns in each transistor column to correspondingly form a U-shaped groove;
forming a gate oxide layer in each U-shaped groove;
forming a grid electrode in each U-shaped groove with the grid electrode oxidation layer;
forming a source electrode at the first end of each silicon pillar;
forming a drain in a drain forming region, wherein the drain forming region is two silicon pillars arranged along the first direction in each transistor row and a corresponding wafer region between the two silicon pillars; the drain forming region is located at a second end of the silicon pillar, wherein the first end and the second end are two opposite ends of the silicon pillar in a third direction respectively, and the first end and the second end have different sizes in the first direction; the silicon pillar between the source electrode and the drain electrode forms a channel region of the transistor;
and a plane formed by the first direction and the second direction is perpendicular to the third direction, and the third direction is the thickness direction of the wafer forming the channel region.
In some embodiments, the plurality of silicon pillars and the first insulating layer are formed by:
partially etching the wafer along the third direction by taking the first surface of the wafer as an etching starting point to form a grid-shaped etching groove consisting of the plurality of silicon columns, wherein the plurality of silicon columns are respectively arranged along the first direction and the second direction; each silicon column has a first preset thickness, and the first preset thickness is smaller than the initial thickness of the wafer; the first surface of the wafer is any one surface of the wafer along the third direction;
depositing an insulating material in the grid-shaped etching groove to form the first insulating layer wrapping each silicon column;
and carrying out chemical mechanical polishing treatment on the first insulating layer until the silicon pillars are exposed.
In some embodiments, the forming a gate oxide layer in each of the U-shaped trenches includes:
and respectively forming the gate oxide layer on the side wall and the bottom of each U-shaped groove between two adjacent silicon columns which are arranged along the first direction in an in-situ oxidation mode.
In some embodiments, the forming a gate in the U-shaped trench formed with the gate oxide layer includes:
depositing a grid electrode material in each U-shaped groove formed with the grid electrode oxidation layer to form a grid electrode; wherein the dimension of the gate in the third direction is smaller than the dimension of the U-shaped trench in the third direction.
In some embodiments, the method further comprises:
depositing an isolation material in each U-shaped groove formed with the grid oxide layer and the grid to form an isolation layer;
and carrying out chemical mechanical polishing treatment on the isolation layer so that the surface of the isolation layer is flush with the surface of the silicon pillar.
In some embodiments, prior to forming the drain, the method further comprises:
thinning the wafer from the second surface of the wafer to enable the wafer at the bottom of the silicon column to have a second preset thickness;
removing the wafer positioned on the first insulating layer in the third direction, and exposing the side face of the drain electrode forming area; the drain forming region has the second preset thickness in the third direction;
isolating the drain forming region by using a second insulating layer;
wherein the second side of the wafer is a side opposite to the first side of the wafer.
In a fourth aspect, an embodiment of the present application provides a method for forming a semiconductor device, where the method includes:
forming a memory cell, wherein the memory cell comprises at least the U-shaped transistor array of the preceding claims; the U-shaped transistor array is formed by the method for forming the U-shaped transistor array provided by the claims; the U-shaped transistor array comprises a plurality of U-shaped transistors which are arranged along a first direction and a second direction respectively; wherein each U-shaped transistor at least comprises: a gate, a source and a drain;
forming a word line, wherein the word line is connected with the grid electrode of each U-shaped transistor, and is used for providing a word line voltage and controlling each U-shaped transistor to be switched on or switched off through the word line voltage;
and forming a bit line, wherein the bit line is connected with the source electrode or the drain electrode of each U-shaped transistor, and the bit line is used for performing reading or writing operation on the memory unit when each U-shaped transistor is conducted.
In some embodiments, the forming a word line includes:
in the second direction, the gates of each U-shaped transistor in the U-shaped transistor array are connected with each other to form the word line.
In some embodiments, the drains of the U-shaped transistors are isolated by a second insulating layer; the forming a bit line includes:
forming a dielectric layer on the drain electrode of the U-shaped transistor array and the surface of the second insulating layer;
etching the dielectric layer to expose the drain electrode and form a bit line groove;
and filling a metal material in the bit line groove to form the bit line.
According to the U-shaped transistor array and the forming method thereof, the semiconductor device and the forming method thereof, the U-shaped transistor array comprises the plurality of U-shaped transistors which are arranged along the first direction and the second direction respectively, and the source electrode and the drain electrode of each U-shaped transistor are located at the first end and the second end of the channel region in the thickness direction of the wafer respectively, so that the area of the U-shaped transistor array is greatly reduced. In addition, each U-shaped transistor in the U-shaped transistor array provided by the embodiments of the present application has dual vertical channels, so that the driving current intensity of each U-shaped transistor in the transistor array can be increased.
Drawings
In the drawings, which are not necessarily drawn to scale, like reference numerals may describe similar components in different views. Like reference numerals having different letter suffixes may represent different examples of similar components. The drawings illustrate generally, by way of example, but not by way of limitation, various embodiments discussed herein.
FIGS. 1a to 1d are schematic structural views of a transistor and a transistor array in the related art;
fig. 2a is an alternative structural schematic diagram of a U-shaped transistor array according to an embodiment of the present application;
fig. 2b is an alternative structural schematic diagram of a U-shaped transistor in the U-shaped transistor array according to the embodiment of the present application;
fig. 3 is an alternative schematic flow chart of a method for forming a U-shaped transistor array according to an embodiment of the present disclosure;
FIGS. 4a to 4m and 5a to 5l are schematic diagrams illustrating the formation of a U-shaped transistor array according to an embodiment of the present disclosure;
fig. 6 is a schematic structural diagram of an alternative semiconductor device provided in an embodiment of the present application;
fig. 7 is an alternative schematic structural diagram of a method for forming a semiconductor device according to an embodiment of the present disclosure;
fig. 8a and 8b are schematic views illustrating the formation of bit lines according to the embodiments of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, specific technical solutions of the present invention will be described in further detail below with reference to the accompanying drawings in the embodiments of the present application. The following examples are intended to illustrate the present application but are not intended to limit the scope of the present application.
In the following description, suffixes such as "module" or "unit" used to denote elements are used only for facilitating the explanation of the present application, and have no specific meaning in themselves. Thus, "module" or "unit" may be used mixedly.
In the related art, the transistor array of the mainstream semiconductor device includes a planar transistor array and a buried channel transistor array, however, in the structure of the planar transistor or the buried channel transistor, the source and the drain are located on the two horizontal sides of the gate. Fig. 1a to 1D are schematic structural diagrams of a transistor and a transistor array in the related art, and as shown in fig. 1a to 1D, a source S and a drain D of the transistor in the related art are respectively located at two horizontal sides of a gate G. Under the structure, the source electrode and the drain electrode respectively occupy different positions, so that the area of the planar transistor array or the buried channel transistor array is larger.
In addition, as the integration of semiconductor devices is increased, the sizes of transistors are reduced and limited by the channel sizes of planar transistors and buried transistors, and the transistor arrays in the related art cannot bear high current.
Based on the above problems in the related art, embodiments of the present application provide a U-shaped transistor array and a method for forming the same, a semiconductor device and a method for forming the same, which can provide a transistor array structure with a smaller area, and the transistor array structure provided by embodiments of the present application can improve the driving current intensity of each transistor.
Fig. 2a is an alternative structural schematic diagram of a U-shaped transistor array according to an embodiment of the present application, and as shown in fig. 2a, the U-shaped transistor array 20 includes: a plurality of U-shaped transistors 200 arranged in a first direction and a second direction, respectively.
In the embodiment of the present application, the first direction intersects with the second direction, and an included angle between the first direction and the second direction may be any angle between 0 ℃ and 90 ℃, for example, the first direction may be perpendicular to the second direction. Here, the first direction is defined as an X-axis direction, and the second direction is defined as a Y-axis direction.
Fig. 2b is an alternative structural schematic diagram of a U-shaped transistor in a U-shaped transistor array according to an embodiment of the present application, and as shown in fig. 2b, each U-shaped transistor 200 in the U-shaped transistor array includes: channel region 201, source 202, drain 203, gate 204, and gate oxide 205.
Wherein, the source 202 is located at a first end of the channel region 201; the drain 203 is located at a second end of the channel region 201, and the source, the channel region and the drain form a U-shaped structure. The first end and the second end are two ends of the channel region opposite to each other in the third direction respectively.
The third direction is a thickness direction of a wafer on which the channel region is formed, a plane formed by the first direction and the second direction is perpendicular to the third direction, and the third direction is defined as a Z-axis direction. In the embodiment of the present application, the positions of the source 202 and the drain 203 can be interchanged.
In some embodiments, the first end and the second end differ in size in the X-axis direction.
The channel region 201 is located on either side of the gate 204 and corresponds to the gate 204, and the gate oxide layer 205 is located between the channel region 201 and the gate 204.
In the embodiment of the present application, since the transistor is U-shaped, the source is formed in two spaced apart regions of the first end of the channel region. After the transistor is formed, the sources of the two regions are connected by a connection line 206 to form a complete source. Here, the connection line is composed of a conductive material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof.
In other embodiments, the first end of the channel region may also be used to form a drain, the drain is formed in two spaced apart regions of the first end of the channel region, and after the transistor is formed, the drains of the two regions are connected by a conductive material to form a complete drain.
In the embodiment of the present application, the source and the drain are respectively located at two opposite ends in the thickness direction of the wafer on which the channel region is formed, that is, the source and the drain of the U-shaped transistor provided in the embodiment of the present application are located in two opposite faces of the wafer, so that the area of the transistor is greatly reduced.
With continued reference to fig. 2a, in some embodiments, the gates 204 of each of the U-shaped transistors in the U-shaped transistor array 20 are connected to each other in the Y-axis direction. Each of the U-shaped transistors further includes: an isolation layer 207; the isolation layer 207 is located on the surface of the gate, and in the Y-axis direction, the isolation layers of each U-shaped transistor in the U-shaped transistor array 20 are connected to each other.
In some embodiments, the gate oxide layer 205 is also located between the isolation layer 207 and the source or the drain.
The U-shaped transistor array provided by the embodiments of the present application can be formed by the method for forming the U-shaped transistor array provided by the following embodiments.
Fig. 3 is an alternative schematic flow chart of a method for forming a U-shaped transistor array according to an embodiment of the present application, and as shown in fig. 3, the method for forming the U-shaped transistor array includes the following steps:
step S301, providing a wafer, wherein the wafer comprises a plurality of silicon column rows arranged along a first direction, and each silicon column row comprises a plurality of silicon columns arranged along a second direction; and a first insulating layer is filled between any two adjacent silicon columns.
In the embodiment of the present application, the wafer includes an even number of silicon pillar rows arranged along the X-axis direction, for example, the wafer includes two silicon pillar rows or four silicon pillar rows arranged along the X-axis direction. Each silicon pillar column includes at least one silicon pillar arranged in the Y-axis direction. Each silicon pillar is used for forming a transistor, and the first insulating layer is used for isolating any two adjacent silicon pillars in the forming process of the transistor.
Step S302, two adjacent silicon pillar columns are determined as a transistor column.
For example, the wafer includes 6 silicon pillar columns arranged along the first direction, and then the 1 st and 2 nd silicon pillar columns are determined as one transistor column; determining the 3 rd and 4 th silicon column columns as a transistor column; the 5 th and 6 th silicon columns are determined as one transistor column.
Step S303, etching the first insulating layer between two silicon pillar columns in each transistor column to form a U-shaped trench correspondingly.
Step S304, forming a gate oxide layer in each U-shaped trench.
Step S305, forming a gate in each U-shaped trench formed with the gate oxide layer.
Step S306, forming a source at the first end of each silicon pillar.
Step S307, forming a drain in a drain forming region, wherein the drain forming region is two silicon pillars arranged along the first direction in each transistor row and a corresponding wafer region between the two silicon pillars; the drain forming region is located at a second end of the silicon pillar.
The first end and the second end are two opposite ends of the silicon pillar in a third direction respectively, and the first end and the second end have different sizes in the first direction; the silicon pillar between the source and the drain constitutes a channel region of the transistor.
And a plane formed by the first direction and the second direction is perpendicular to the third direction, and the third direction is the thickness direction of the wafer forming the channel region.
Fig. 4a to 4m and 5a to 5l are schematic diagrams illustrating formation of a U-shaped transistor array according to an embodiment of the present application, and a method for forming a U-shaped transistor array according to an embodiment of the present application will be described in detail with reference to fig. 4a to 4m and 5a to 5 l.
First, referring to fig. 4a and 4b, step S301 is executed to provide a wafer, where the wafer includes a plurality of silicon pillar rows arranged along a first direction, and each of the silicon pillar rows includes a plurality of silicon pillars arranged along a second direction; and a first insulating layer is filled between any two adjacent silicon columns.
As shown in fig. 4a and 4b, the wafer includes 4 silicon pillar rows 401 arranged along the X-axis direction, and each silicon pillar row 401 includes silicon pillars 4011 arranged along the Y-axis direction.
In some embodiments, the transistor forming region is formed by:
and S3011, partially etching the wafer along the third direction by using the first surface of the wafer as an etching starting point to form a grid-shaped etching groove consisting of the plurality of silicon columns.
With reference to fig. 4a and 4b, the wafer is etched along the Z-axis direction with the first surface S1 of the wafer as the etching starting point to form a grid-shaped etched trench composed of a plurality of silicon pillars 4011, wherein fig. 4a is a top view and fig. 4b is a cross-sectional view. The silicon columns are arranged along the X-axis direction and the Y-axis direction respectively; each silicon pillar 4011 has a first preset thickness h1 in the Z-axis direction, and the first preset thickness h1 is smaller than the initial thickness h0 of the wafer in the Z-axis direction; the first surface S1 of the wafer is any surface of the wafer along the Z-axis direction.
It should be noted that fig. 4a and 4b only show a part of the silicon pillars by way of example, and the number of the silicon pillars does not have a practical meaning, and is only convenient for understanding the scheme.
Here, the wafer may be etched using a dry etching process, for example, a plasma etching process or a reactive ion etching process. It should be noted that, in the embodiment of the present application, the etching on the wafer is a partial etching performed in the thickness direction of the wafer, that is, the wafer is not etched through in the etching process.
And S3012, depositing an insulating material in the grid-shaped etched grooves to form a first insulating layer surrounding each silicon pillar.
In the embodiment of the present application, the insulating material may be a silicon dioxide material or other insulating materials.
As shown in fig. 4c and 4d, an insulating material is deposited in the grid-like etched trenches, and the periphery of each silicon pillar 401 is filled with the insulating material, forming a first insulating layer 402.
It should be noted that, during the actual deposition of the insulating material, the insulating material usually covers the surface of each silicon pillar, so step S3013 is performed after the deposition of the insulating material.
In step S3013, a Chemical Mechanical Polishing (CMP) process is performed on the first insulating layer until the silicon pillars 401 are exposed.
Referring to fig. 4e to 4g, step S302 and step S303 are performed to sequentially determine each two adjacent silicon pillar columns as a transistor column, and etch the first insulating layer between the two silicon pillar columns in each transistor column to correspondingly form a U-shaped trench.
As shown in fig. 4e to 4g, the 1 st silicon pillar column and the 2 nd silicon pillar column are determined as one transistor column 40, and the 3 rd silicon pillar column and the 4 th silicon pillar column are determined as the other transistor column 40. The first insulating layer 402 between two silicon pillar columns in each transistor column 40 is etched along the Z-axis direction, and a U-shaped trench 403 is formed corresponding to each transistor column 40. Wherein fig. 4e is a top view, fig. 4f is a cross-sectional view, and fig. 4g is a three-dimensional structure view.
Next, referring to fig. 4h to 4j, step S304 is performed to form a gate oxide layer in each of the U-shaped trenches.
In some embodiments, the step S304 may be implemented by:
and respectively forming the gate oxide layer on the side wall and the bottom of each U-shaped groove between two adjacent silicon columns which are arranged along the first direction in an in-situ oxidation mode.
As shown in fig. 4h to 4j, a gate oxide layer 404 is formed on the sidewall and the bottom of each U-shaped trench arranged in the X-axis direction between two adjacent silicon pillars 4011. Fig. 4h is a top view, fig. 4i is a cross-sectional view, and fig. 4j is a three-dimensional structure view.
Here, the gate oxide layer silicon dioxide may be formed by in-situ oxidizing the bottom and sidewalls of the U-shaped trench between two adjacent silicon pillars arranged in the Z-axis direction by heating or pressing.
Next, referring to fig. 4k to 4m, step S305 is performed to form a gate in each U-shaped trench formed with the gate oxide layer.
In some embodiments, the step S305 may be implemented by:
and depositing a grid electrode material in each U-shaped groove formed with the grid electrode oxide layer to form the grid electrode.
Here, the gate electrode may be formed by depositing a gate material in the U-shaped trench after the gate oxide Layer is formed through a Chemical Vapor Deposition (PVD), Physical Vapor Deposition (PVD), or Atomic Layer Deposition (ALD) process. In the embodiment of the present application, the gate material may be any one of a metal material or a semiconductor conductive material, such as copper, cobalt, tungsten, doped silicon, polysilicon, or any combination thereof.
As shown in fig. 4k to 4m, a gate material is deposited in the U-shaped trench deposited with the gate oxide layer 404 to form a gate 405, and a dimension h2 of the gate 405 in the Z-axis direction is smaller than an initial dimension h3 of the U-shaped trench in the Z-axis direction. Wherein fig. 4k is a top view, fig. 4l is a cross-sectional view, and fig. 4m is a three-dimensional structure view.
In some embodiments, after forming the gate, the method further comprises:
and depositing an isolation material in the U-shaped groove formed with the grid oxide layer and the grid to form an isolation layer.
And carrying out chemical mechanical polishing treatment on the isolation layer so that the surface of the isolation layer is flush with the surface of the silicon pillar.
As shown in fig. 5a to 5c, an isolation material is deposited in the U-shaped trench formed with the gate oxide layer 404 and the gate 405 to form an isolation layer 406, and the isolation layer is subjected to CMP processing so that the surface of the isolation layer 406 is flush with the surface of the silicon pillar 4011. Wherein, fig. 5a is a top view, fig. 5b is a cross-sectional view, and fig. 5c is a three-dimensional structure view.
In embodiments of the present application, the isolation material may be deposited by any suitable deposition process, and the isolation material may comprise any insulating material, such as silicon nitride, silicon oxynitride, silicon carbide, or silicon dioxide.
Next, referring to fig. 5d to 5f, step S306 is performed to form a source at the first end of each silicon pillar.
Here, the first end is an end of the silicon pillar in the Z-axis direction. As shown in fig. 5d to 5f, in the embodiment of the present application, the first end of the silicon pillar is ion-implanted to a predetermined depth, so as to form the source electrode 407. The dimension of the source 407 in the Z-axis direction is larger than the dimension of the spacer 406 in the Z-axis direction, i.e. there is an overlap region between the source and the gate oxide layer and the gate. Wherein, fig. 5d is a top view, fig. 5e is a cross-sectional view, and fig. 5f is a three-dimensional structure view.
In some embodiments, the shape of the source electrode comprises any one of: square, semi-circular, triangular or any polygon.
Next, referring to fig. 5g to 5l, step S307 is performed to form a drain in the drain forming region.
In an embodiment of the present invention, the drain formation region is two silicon pillars arranged along the first direction in each of the transistor rows and a wafer region corresponding to between the two silicon pillars.
In some embodiments, before forming the drain electrode, the method for forming the U-shaped transistor array further comprises the following steps:
and step S40, starting from the second surface of the wafer, thinning the wafer so that the wafer at the bottom of the silicon pillar has a second preset thickness.
As shown in fig. 5g and 5h, the wafer is turned over, and the wafer is thinned from the second side S2, so that the wafer at the bottom of the silicon pillars 4011 has a second predetermined thickness h 4. The second side S2 of the wafer is the side opposite to the first side S1 of the wafer. Wherein fig. 5g is a top view and fig. 5h is a cross-sectional view.
Step S41, removing the wafer located on the first insulating layer in the third direction, and exposing the side surface of the drain formation region; the drain forming region has the second predetermined thickness in the third direction.
And step S42, isolating the drain forming region by using a second insulating layer.
As shown in fig. 5i and 5j, the wafer on the first insulating layer 402 in the Z-axis direction is removed by using a dry etching technique to expose the side surface of the drain formation region 408, and the drain formation region 408 is isolated by using a second insulating layer 409, where fig. 5i is a top view and fig. 5j is a cross-sectional view.
Here, the second insulating layer 409 is made of any insulating material, and the material of the second insulating layer 409 may be the same as or different from that of the first insulating layer 402. In the embodiment of the present application, the material of the first insulating layer is the same as that of the second insulating layer.
In some embodiments, the first side S1 of the wafer needs to be fixed on a support structure before the second side of the wafer is thinned, so as to prevent the structure of the formed transistor array from being damaged when the second side S2 of the wafer is thinned.
After forming the drain forming region, the drain is formed in the drain forming region. In an embodiment of the present application, the drain formation region is located at a second end of the silicon pillar, and the first end and the second end are two opposite ends of the silicon pillar in the Z-axis direction, respectively.
As shown in fig. 5k and 5l, a drain 410 is formed by ion implantation into a drain forming region 408 at the second end of the silicon pillar, wherein fig. 5k is a top view and fig. 5l is a cross-sectional view.
In some embodiments, the shape of the drain electrode comprises any one of: square, semi-circular, triangular or any polygon.
It should be noted that the three-dimensional structure views provided by the embodiments of the present application do not show the first insulating layer and the second insulating layer filled between two adjacent transistors, and in fact, the first insulating layer is filled between adjacent silicon pillar columns, the first insulating layer is also filled between adjacent silicon pillars arranged along the second direction in each silicon pillar column, and the second insulating layer is filled between the drains of each transistor.
In the embodiment of the application, the region between the source electrode and the drain electrode forms the channel region of each U-shaped transistor array.
It should be noted that, since the source in the channel region is separated into two mutually independent portions by the isolation layer, after the source is formed, a connection line needs to be formed between the two sources to connect the two mutually independent sources to form a complete source. Here, the connection line is composed of any suitable conductive material.
In the embodiment of the present application, the positions of the source and the drain may be interchanged, that is, the source may be formed first or the drain may be formed first, and the source and the drain of each U-shaped transistor in the U-shaped transistor array formed in the embodiment of the present application may have the same shape or different shapes.
In some embodiments, the horizontal cross-section of the first end of the channel region is two rectangles (squares), semicircles, triangles, and polygons; the horizontal cross-section of the second end of the channel region may be of any shape.
In some embodiments, a cross-sectional shape of each U-type transistor in the array of U-type transistors along a direction perpendicular to the third direction may be square, oval, or diamond. FIG. 5m is an alternative cross-sectional view of each U-shaped transistor provided in the embodiments of the present application, wherein the cross-section of the U-shaped transistor in the diagrams a and d in FIG. 5m is rectangular; the cross section of the U-shaped transistor in the diagrams b and e in fig. 5m is oval, and the cross section of the U-shaped transistor in the diagrams c and f in fig. 5m is diamond. In fig. 5m, a, b, c and d, e, f are different in that the gate extends in different directions, i.e., the second direction of each U-shaped transistor in the U-shaped transistor array is different.
The forming method of the U-shaped transistor array provided in the embodiment of the present application is similar to that of the U-shaped transistor array in the above embodiment, and for technical features not disclosed in the embodiment of the present application in detail, please refer to the above embodiment for understanding, and details are not repeated herein.
According to the U-shaped transistor array formed by the method for forming the U-shaped transistor array, the source electrode and the drain electrode of each U-shaped transistor are respectively located at the two ends of the channel region in the thickness direction of the wafer, so that the area of the transistor array is greatly reduced. In addition, each U-shaped transistor in the U-shaped transistor array provided by the embodiments of the present application has dual vertical channels, so that the driving current intensity of each U-shaped transistor in the transistor array can be increased.
An embodiment of the present application provides a semiconductor device, fig. 6 is an alternative schematic structural diagram of the semiconductor device provided in the embodiment of the present application, and as shown in fig. 6, the semiconductor device 60 includes: memory cells, word lines 602 and bit lines 603; the memory cell 601 includes at least a U-shaped transistor array 601; the U-shaped transistor array 601 includes a plurality of U-shaped transistors 6011 arranged in a first direction and a second direction, respectively; each of the U-shaped transistors 6011 at least includes: a gate G, a source S and a drain D.
In some embodiments, each of the U-shaped transistors 601 further includes a channel region C, and the source of each of the channel transistors is located at a first end of the channel region C; the drain electrode of each U-shaped transistor is positioned in the drain electrode forming area of the second end of the channel area; the first end and the second end are two opposite ends of the channel region in the Z-axis direction respectively, and the Z-axis direction is the thickness direction of a wafer forming the channel region.
With reference to fig. 6, the word line 602 extending along the Y-axis is connected to the gate of each U-shaped transistor 6011, and the word line 602 is used to provide a word line voltage and control each U-shaped transistor to turn on or turn off through the word line voltage. The bit line 603 extending along the X-axis direction is connected to a source or a drain of each U-shaped transistor 6011, and the bit line 603 is used for performing a read or write operation on the memory cell when each U-shaped transistor is turned on.
In the embodiments of the present application, the material of the word line and the bit line includes, but is not limited to, tungsten, cobalt, copper, aluminum, polysilicon, doped silicon, silicide, or any combination thereof.
In some embodiments, the memory cell further comprises: a storage capacitor (not shown) corresponding to each of the U-shaped transistors; one end of each storage capacitor is connected with the source electrode or the drain electrode of one U-shaped transistor, the other end of each storage capacitor is grounded, and the storage capacitors are used for storing data written into the memory units.
The semiconductor device provided by the embodiment of the application comprises various types of memories. For example, NAND Flash (Flash), Nor Flash, DRAM, Static Random Access Memory (SRAM), Phase-Change Memory (PCM), ferroelectric Memory, magnetic Random Access Memory, or resistive Random Access Memory.
In some embodiments, when the semiconductor device is a PCM, the memory cell further includes: an adjustable resistor corresponding to each U-shaped transistor, each adjustable resistor being connected between the bit line 603 and the source of each U-shaped transistor 6011, or each adjustable resistor being connected between the bit line 603 and the drain of each U-shaped transistor 6011, each adjustable resistor being used for adjusting a state of data stored in the memory cell by a bit line voltage provided by the bit line.
In the embodiments of the present application, some common semiconductor devices are only exemplified, the scope of protection of the present application is not limited thereto, and any semiconductor device including the U-shaped transistor array provided in the embodiments of the present application falls within the scope of protection of the present application.
For technical features not disclosed in the embodiments of the present application in detail, please refer to the above embodiments for understanding, and details are not repeated here.
The semiconductor device provided by the embodiment of the application at least comprises the U-shaped transistor array, and the source electrode and the drain electrode of each U-shaped transistor in the U-shaped transistor array are respectively located at the first end and the second end of the channel region in the thickness direction of the wafer, so that the area of the U-shaped transistor array is greatly reduced, and the formed semiconductor device is further miniaturized. In addition, each U-shaped transistor in the U-shaped transistor array is provided with a double vertical channel, so that the driving current intensity of each U-shaped transistor in the transistor array is increased, and the electrical performance of the semiconductor device can be improved.
In addition, an embodiment of the present application further provides a method for forming a semiconductor device, and fig. 7 is an alternative schematic structural diagram of the method for forming a semiconductor device provided in the embodiment of the present application, as shown in fig. 7, the method includes the following steps:
step S701, forming a memory unit, wherein the memory unit at least comprises a U-shaped transistor array, and the U-shaped transistor array comprises a plurality of U-shaped transistors which are respectively arranged along a first direction and a second direction; each U-shaped transistor at least comprises: a gate, a source and a drain.
In the embodiment of the present application, the U-shaped transistor array is formed by the method for forming the U-shaped transistor array in the above embodiment.
Step S702, forming a word line, where the word line is connected to the gate of each U-shaped transistor, and the word line is used to provide a word line voltage and control the on/off of each U-shaped transistor through the word line voltage.
In some embodiments, the word line may be formed by:
in the second direction, the gates of each U-shaped transistor in the U-shaped transistor array are connected with each other to form the word line.
Step S703, forming a bit line, where the bit line is connected to the source or the drain of each U-shaped transistor, and the bit line is used to perform a read or write operation on the memory cell when each U-shaped transistor is turned on.
In some embodiments, the drain of the U-shaped transistor is isolated by a second insulating layer, and the bit line may be formed by:
step S7031, a dielectric layer is formed on the drain of the U-shaped transistor array and the surface of the second insulating layer.
Step S7032, the dielectric layer is etched to expose the drain electrode and form a bit line groove.
Step S7033, filling a metal material in the bit line trench to form the bit line.
Fig. 8a and 8b are schematic diagrams illustrating the formation of bit lines according to an embodiment of the present application, in which fig. 8a is a top view and fig. 8b is a cross-sectional view, and as shown in fig. 8a and 8b, a plurality of bit lines 603 are formed on the surface of the drain 410.
In some embodiments, the method of forming a semiconductor device further includes: and forming a storage capacitor corresponding to each U-shaped transistor, wherein one end of each storage capacitor is connected with the source electrode or the drain electrode of one U-shaped transistor, the other end of each storage capacitor is grounded, and the storage capacitors are used for storing data written into the memory unit.
In some embodiments, the method of forming a semiconductor device further includes: and forming an adjustable resistor corresponding to each U-shaped transistor, wherein each adjustable resistor is connected between the bit line and the source electrode of each U-shaped transistor, or each adjustable resistor is connected between the bit line and the drain electrode of each U-shaped transistor, and each adjustable resistor is used for adjusting the state of the data stored in the memory unit through the bit line voltage provided by the bit line.
The method for forming the semiconductor device provided in the embodiment of the present application is similar to the semiconductor device in the foregoing embodiment, and for technical features that are not disclosed in the embodiment of the present application in detail, please refer to the foregoing embodiment for understanding, and details are not described here again.
According to the method for forming the semiconductor device, the formed semiconductor device at least comprises the U-shaped transistor array, and the source electrode and the drain electrode of each U-shaped transistor in the U-shaped transistor array are respectively located at the first end and the second end of the channel region in the thickness direction of the wafer, so that the area of the U-shaped transistor array is greatly reduced, and the formed semiconductor device is further miniaturized. In addition, each U-shaped transistor in the U-shaped transistor array has double vertical channels, so that the driving current intensity of each U-shaped transistor in the transistor array is increased, and the electrical property of the formed semiconductor device can be improved.
In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in a non-target manner. The above-described device embodiments are merely illustrative, for example, the division of the unit is only a logical functional division, and there may be other division ways in actual implementation, such as: multiple units or components may be combined, or may be integrated into another system, or some features may be omitted, or not implemented. Additionally, the various components shown or discussed are coupled or directly coupled to each other.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed on a plurality of network units; some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
The features disclosed in the several method or apparatus embodiments provided in the present application may be combined arbitrarily, without conflict, to arrive at new method embodiments or apparatus embodiments.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.

Claims (17)

1. A U-shaped transistor array, comprising: a plurality of U-shaped transistors arranged in a first direction and a second direction, respectively; wherein each of the U-shaped transistors includes:
a channel region;
a source electrode positioned at a first end of the channel region;
the drain electrode is positioned at a second end of the channel region, wherein the first end and the second end are two opposite ends of the channel region in a third direction respectively; the first end and the second end are different in size in the first direction; the source electrode, the channel region and the drain electrode form a U-shaped structure;
the channel region is positioned on any side of the grid electrode;
the grid oxide layer is positioned between the channel region and the grid;
a plane formed by the first direction and the second direction is perpendicular to the third direction; the third direction is a thickness direction of a wafer on which the channel region is formed.
2. The transistor array of claim 1, wherein the gates of each of the U-shaped transistors in the array of U-shaped transistors are connected to each other in the second direction.
3. The transistor array of claim 1 or 2, wherein each of the U-shaped transistors further comprises: an isolation layer;
the isolation layer is located on the surface of the grid electrode, and in the second direction, the isolation layer of each U-shaped transistor in the U-shaped transistor array is connected with each other.
4. The transistor array of claim 3, wherein the gate oxide layer is further located between the isolation layer and the source or the drain.
5. The transistor array of claim 3, wherein the angle between the first direction and the second direction is 0-90 degrees.
6. A semiconductor device, characterized in that the semiconductor device comprises: memory cells, word lines and bit lines; the memory unit at least comprises the U-shaped transistor array as claimed in any one of claims 1 to 4; the U-shaped transistor array comprises a plurality of U-shaped transistors which are arranged along a first direction and a second direction respectively; wherein each U-shaped transistor at least comprises: a gate, a source and a drain;
the word line extending along the second direction is connected with the gate of each U-shaped transistor, and is used for providing a word line voltage and controlling each U-shaped transistor to be switched on or switched off through the word line voltage;
the bit line extending along the first direction is connected with a source or a drain of each U-shaped transistor, and the bit line is used for performing reading or writing operation on the memory unit when each U-shaped transistor is conducted.
7. The semiconductor device of claim 6, wherein the memory cell further comprises: a storage capacitor corresponding to each U-shaped transistor;
one end of each storage capacitor is connected with the source electrode or the drain electrode of one U-shaped transistor, the other end of each storage capacitor is grounded, and the storage capacitors are used for storing data written into the memory units.
8. The semiconductor device according to claim 6 or 7, wherein the semiconductor device includes, but is not limited to, any of: a dynamic random access memory, a ferroelectric memory, a phase change memory, a magneto-resistive memory, or a resistive memory.
9. A method for forming a U-shaped transistor array, the method comprising:
providing a wafer, wherein the wafer comprises a plurality of silicon column rows arranged along a first direction, and each silicon column row comprises a plurality of silicon columns arranged along a second direction; a first insulating layer is filled between any two adjacent silicon columns;
determining every two adjacent silicon column columns as a transistor column in sequence;
etching the first insulating layer between two silicon column columns in each transistor column to correspondingly form a U-shaped groove;
forming a gate oxide layer in each U-shaped groove;
forming a grid electrode in each U-shaped groove with the grid electrode oxidation layer;
forming a source electrode at the first end of each silicon pillar;
forming a drain in a drain forming region, wherein the drain forming region is two silicon pillars arranged along the first direction in each transistor row and a corresponding wafer region between the two silicon pillars; the drain forming region is located at a second end of the silicon pillar, wherein the first end and the second end are two opposite ends of the silicon pillar in a third direction respectively, and the first end and the second end have different sizes in the first direction; the silicon pillar between the source electrode and the drain electrode forms a channel region of the transistor;
and a plane formed by the first direction and the second direction is perpendicular to the third direction, and the third direction is the thickness direction of the wafer forming the channel region.
10. The method of claim 9, wherein the plurality of silicon pillars and the first insulating layer are formed by:
partially etching the wafer along the third direction by taking the first surface of the wafer as an etching starting point to form a grid-shaped etching groove consisting of the plurality of silicon columns, wherein the plurality of silicon columns are respectively arranged along the first direction and the second direction; each silicon column has a first preset thickness, and the first preset thickness is smaller than the initial thickness of the wafer; the first surface of the wafer is any one surface of the wafer along the third direction;
depositing an insulating material in the grid-shaped etching groove to form the first insulating layer wrapping each silicon column;
and carrying out chemical mechanical polishing treatment on the first insulating layer until the silicon pillars are exposed.
11. The method of claim 9 or 10, wherein said forming a gate oxide layer in each of said U-shaped trenches comprises:
and respectively forming the gate oxide layer on the side wall and the bottom of each U-shaped groove between two adjacent silicon columns which are arranged along the first direction in an in-situ oxidation mode.
12. The method of claim 9 or 10, wherein forming a gate in each U-shaped trench in which the gate oxide layer is formed comprises:
depositing a grid electrode material in each U-shaped groove formed with the grid electrode oxidation layer to form a grid electrode; wherein the dimension of the gate in the third direction is smaller than the dimension of the U-shaped trench in the third direction.
13. The method of claim 12, further comprising:
depositing an isolation material in each U-shaped groove formed with the grid oxide layer and the grid to form an isolation layer;
and carrying out chemical mechanical polishing treatment on the isolation layer so that the surface of the isolation layer is flush with the surface of the silicon pillar.
14. The method of claim 9 or 10, wherein prior to forming the drain, the method further comprises:
thinning the wafer from the second surface of the wafer to enable the wafer at the bottom of the silicon column to have a second preset thickness;
removing the wafer positioned on the first insulating layer in the third direction, and exposing the side face of the drain electrode forming area; the drain forming region has the second preset thickness in the third direction;
isolating the drain forming region by using a second insulating layer;
wherein the second side of the wafer is a side opposite to the first side of the wafer.
15. A method of forming a semiconductor device, the method comprising:
forming a memory cell, wherein the memory cell comprises at least the U-shaped transistor array of any one of claims 1 to 5; the U-shaped transistor array is formed by the method for forming the U-shaped transistor array provided by any one of claims 9 to 14; the U-shaped transistor array comprises a plurality of U-shaped transistors which are arranged along a first direction and a second direction respectively; wherein each U-shaped transistor at least comprises: a gate, a source and a drain;
forming a word line, wherein the word line is connected with the grid electrode of each U-shaped transistor, and is used for providing a word line voltage and controlling each U-shaped transistor to be switched on or switched off through the word line voltage;
and forming a bit line, wherein the bit line is connected with the source electrode or the drain electrode of each U-shaped transistor, and the bit line is used for performing reading or writing operation on the memory unit when each U-shaped transistor is conducted.
16. The method of claim 15, wherein forming the word line comprises:
in the second direction, the gates of each U-shaped transistor in the U-shaped transistor array are connected with each other to form the word line.
17. The method according to claim 15 or 16, wherein the drain of the U-shaped transistor is isolated by a second insulating layer; the forming a bit line includes:
forming a dielectric layer on the drain electrode of the U-shaped transistor array and the surface of the second insulating layer;
etching the dielectric layer to expose the drain electrode and form a bit line groove;
and filling a metal material in the bit line groove to form the bit line.
CN202110748780.8A 2021-07-02 2021-07-02 U-shaped transistor array and forming method thereof, semiconductor device and forming method thereof Pending CN113629054A (en)

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CN102522407A (en) * 2011-12-23 2012-06-27 清华大学 Memory array structure with vertical transistor and forming method thereof
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