CN113506737B - Pillar transistor and method of manufacturing the same, semiconductor device and method of manufacturing the same - Google Patents

Pillar transistor and method of manufacturing the same, semiconductor device and method of manufacturing the same Download PDF

Info

Publication number
CN113506737B
CN113506737B CN202110422036.9A CN202110422036A CN113506737B CN 113506737 B CN113506737 B CN 113506737B CN 202110422036 A CN202110422036 A CN 202110422036A CN 113506737 B CN113506737 B CN 113506737B
Authority
CN
China
Prior art keywords
transistor
wafer
forming
column
pillar
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202110422036.9A
Other languages
Chinese (zh)
Other versions
CN113506737A (en
Inventor
华文宇
王喜龙
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ICLeague Technology Co Ltd
Original Assignee
ICLeague Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ICLeague Technology Co Ltd filed Critical ICLeague Technology Co Ltd
Priority to CN202110422036.9A priority Critical patent/CN113506737B/en
Priority to PCT/CN2021/111345 priority patent/WO2022222310A1/en
Priority to KR1020237038547A priority patent/KR20240008849A/en
Publication of CN113506737A publication Critical patent/CN113506737A/en
Application granted granted Critical
Publication of CN113506737B publication Critical patent/CN113506737B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/488—Word lines

Abstract

The embodiment of the application provides a cylindrical transistor and a manufacturing method thereof, a semiconductor device and a manufacturing method thereof, wherein the manufacturing method of the cylindrical transistor comprises the following steps: providing a wafer, wherein the wafer is provided with a plurality of transistor forming areas, each transistor forming area is provided with a transistor column, and each transistor column is provided with an exposed side wall; forming a grid oxide layer and a grid on the side wall of each crystal column in sequence; forming a source electrode at a first end of the transistor column; forming a drain electrode at a second end of the crystal column, wherein the first end and the second end are opposite ends of the crystal column in a first direction, and the first direction is a thickness direction of the wafer; a column of transistors between the source and the drain constitutes a channel region of the transistor.

Description

Pillar transistor and method of manufacturing the same, semiconductor device and method of manufacturing the same
Technical Field
The present application relates to the field of semiconductor technology, and relates to, but is not limited to, a pillar transistor and a method of manufacturing the same, a semiconductor device and a method of manufacturing the same.
Background
Transistors are widely used as switching devices or driving devices in electronic devices. For example, transistors may be used in dynamic random access memory (Dynamic Random Access Memory, DRAM) to control capacitance in each memory cell.
In the related art, the transistors mainly include a planar transistor and a buried channel transistor, however, the Source (S) and the Drain (Drain, D) of the planar transistor or the buried channel transistor are located at two horizontal sides of the Gate (Gate, G), and the Source and the Drain occupy different positions respectively under the structure, so that the area of the transistor is large. In addition, in the memory device, the source and drain of the transistor are connected to different structures after being formed, and when the source and drain are located at two horizontal sides of the gate, the circuit wiring inside the memory is easily complicated, and the manufacturing process is difficult.
Disclosure of Invention
In view of this, embodiments of the present application provide a pillar transistor and a method of manufacturing the same, a semiconductor device and a method of manufacturing the same.
In a first aspect, an embodiment of the present application provides a method for manufacturing a pillar transistor, including:
providing a wafer, wherein the wafer is provided with a plurality of transistor forming areas, each transistor forming area is provided with a transistor column, and each transistor column is provided with an exposed side wall;
Forming a grid oxide layer and a grid on the side wall of each crystal column in sequence;
forming a source electrode at a first end of the transistor column;
forming a drain electrode at a second end of the crystal column, wherein the first end and the second end are opposite ends of the crystal column in a first direction, and the first direction is a thickness direction of the wafer; a column of transistors between the source and the drain forms a channel region of the transistor.
In some embodiments, the transistor forming region further has an insulating layer surrounding other sidewalls of the transistor string; the transistor forming region is formed by:
partially etching the wafer along the first direction by taking the first surface of the wafer as an etching starting point to form grid-shaped etching grooves formed by a plurality of silicon columns, wherein each silicon column has a first preset thickness which is smaller than the initial thickness of the wafer; the first surface of the wafer is any surface of the wafer along the first direction;
depositing an insulating material in the grid-shaped etched grooves to form an insulating layer surrounding each silicon column;
And etching the silicon column and the insulating layer to form the transistor column with the exposed side wall, thereby obtaining the transistor forming region.
In some embodiments, the etching the silicon pillar and the insulating layer to form the crystal pillar having a bare side wall comprises:
taking the edge position of the silicon column as an etching starting point, carrying out partial etching treatment on the silicon column and the insulating layer along the first direction, removing the silicon column and the insulating layer which have preset dimensions in the second direction and have the first preset thickness in the first direction, forming the crystal column with the exposed side wall, and forming an etching groove; wherein the preset dimension is less than an initial dimension of the silicon pillar in the second direction; the second direction is perpendicular to the first direction.
In some embodiments, prior to forming the gate oxide and the gate, the method further comprises:
depositing a first isolation layer at the bottom of the etched groove;
correspondingly, the step of sequentially forming a gate oxide layer and a gate on the side wall of each transistor column comprises the steps of:
Forming an initial gate oxide layer on the side wall of the crystal string in an in-situ oxidation mode;
depositing a polysilicon material in the etching groove to form a polysilicon layer;
and simultaneously etching the initial gate oxide layer and the polysilicon layer in the first direction, and removing part of the initial gate oxide layer and the polysilicon layer in the first direction to form the gate oxide layer and the gate.
In some embodiments, after forming the gate oxide layer and the gate, the method further comprises:
and depositing a second isolation layer in the etched groove, wherein the second isolation layer is positioned in a projection area of the crystal column in the second direction, and the dimension of the second isolation layer in the third direction is equal to the dimension of the crystal column in the third direction.
In some embodiments, prior to forming the drain, the method further comprises:
thinning the wafer from the second surface of the wafer until the first isolation layer and the second end of the crystal column are exposed; wherein the second side of the wafer is the side opposite to the first side of the wafer.
In some embodiments, the source and the drain are the same or different in shape;
the shape of the source electrode and the drain electrode includes any one of the following: square, semi-circular, triangular or any polygon.
In a second aspect, embodiments of the present application provide a pillar transistor, the transistor comprising:
a channel region;
a source electrode positioned at a first end of the channel region;
the drain electrode is positioned at the second end of the channel region, wherein the first end and the second end are respectively opposite ends of the channel region in a first direction, and the first direction is the thickness direction of a wafer forming the channel region;
a gate electrode located on either side of the channel region and corresponding to the channel region;
and the gate oxide layer is positioned between the channel region and the gate.
In a third aspect, embodiments of the present application provide a method for forming a semiconductor device, the method including:
forming at least one memory cell, wherein each memory cell comprises at least: a pillar transistor; the pillar transistor includes: a gate, a source and a drain; the columnar transistor is manufactured by the manufacturing method of the columnar transistor;
Forming a word line, wherein the word line is connected with the grid electrode of the columnar transistor, is used for providing word line voltage, and controls the on or off of the columnar transistor through the word line voltage;
a bit line is formed, the bit line being connected to the source or drain of the pillar transistor, the bit line being for performing a read or write operation on the memory cell when the pillar transistor is turned on.
In a fourth aspect, embodiments of the present application provide a semiconductor device, including: at least one memory cell, a word line, and a bit line, each of the memory cells comprising at least: the pillar transistor described above; the pillar transistor includes at least: a gate, a source and a drain;
the word line is connected with the grid electrode of the columnar transistor, is used for providing word line voltage and controls the on or off of the columnar transistor through the word line voltage;
the bit line is connected with a source or a drain of the pillar transistor, and is used for performing read or write operations on the memory cell when the pillar transistor is turned on.
In some embodiments, the memory cell further comprises: a storage capacitor;
One end of the storage capacitor is connected with the drain electrode or the source electrode of the columnar transistor, the other end of the storage capacitor is grounded, and the storage capacitor is used for storing data written into the memory unit.
In some embodiments, the memory cell further comprises: an adjustable resistor;
the adjustable resistor is connected between the bit line and the source of the pillar transistor or between the bit line and the drain of the pillar transistor, and is used for adjusting the state of data stored in the memory cell through the bit line voltage provided by the bit line.
In some embodiments, when the semiconductor device includes a plurality of the memory cells, the plurality of the memory cells are connected in parallel or in series.
According to the cylindrical transistor, the manufacturing method thereof, the semiconductor device and the manufacturing method thereof, the source electrode and the drain electrode of the formed cylindrical transistor are respectively positioned at the first end and the second end of the channel region in the first direction, and the first direction is the thickness direction of the wafer forming the channel region, so that the area of the transistor is greatly reduced. The columnar transistor provided by the embodiment of the application can be used for forming a memory, and as the drain electrode and the source electrode of the transistor are positioned on different surfaces of the wafer, different structures connected with the source electrode and the drain electrode in the memory can be respectively designed in two surfaces of the wafer, namely in two opposite surfaces of the wafer, so that the circuit layout in the memory is simplified, and the process difficulty of manufacturing the memory is reduced.
Drawings
In the drawings (which are not necessarily drawn to scale), like numerals may describe similar components in different views. Like reference numerals having different letter suffixes may represent different instances of similar components. The drawings illustrate generally, by way of example and not by way of limitation, various embodiments discussed herein.
FIG. 1A is a schematic diagram of a planar transistor in the related art;
FIG. 1B is a schematic diagram of a buried channel transistor according to the related art;
FIG. 1C is a schematic diagram of a DRAM memory cell formed by planar transistors according to the related art;
FIG. 1D is a schematic diagram of a DRAM memory cell formed by using a buried channel transistor according to the related art;
fig. 2 is a schematic structural diagram of an alternative pillar transistor according to an embodiment of the present application;
fig. 3A is a schematic flow chart of an alternative method for manufacturing a pillar transistor according to an embodiment of the present application;
fig. 3B is a cross-sectional view of a grid-shaped etched trench provided in an embodiment of the present application along a first direction;
FIG. 3C is a top view of a grid-like etched trench provided in an embodiment of the present application;
fig. 3D is a top view of forming an insulating layer in grid-like etched trenches according to an embodiment of the present disclosure;
FIG. 3E is a top view of a crystal string provided by an embodiment of the present application;
fig. 3F is a schematic structural diagram of forming a first isolation layer according to an embodiment of the present disclosure;
fig. 3G is a schematic structural diagram of forming an initial gate oxide layer according to an embodiment of the present disclosure;
fig. 3H is a schematic structural diagram of forming a gate oxide layer and a gate according to an embodiment of the present disclosure;
FIG. 3I is a schematic diagram of a structure for forming a second isolation layer according to an embodiment of the present disclosure;
fig. 3J is a schematic structural diagram of forming a source according to an embodiment of the present disclosure;
fig. 3K is a schematic structural diagram of a transistor after thinning a second surface of a wafer according to an embodiment of the present application;
fig. 3L is a schematic structural diagram of forming a drain according to an embodiment of the present application;
fig. 3M is a schematic structural diagram of an alternative pillar transistor according to an embodiment of the present application;
fig. 3N is a schematic structural diagram of an alternative pillar transistor according to an embodiment of the present application;
fig. 4A is a schematic structural diagram of an alternative semiconductor device according to an embodiment of the present application;
FIG. 4B is a schematic diagram of an alternative structure of a DRAM memory cell according to an embodiment of the present application;
FIG. 4C is a schematic diagram of an alternative structure of a PCM memory cell according to an embodiment of the present application;
Fig. 5 is a schematic structural diagram of an alternative method for forming a semiconductor device according to an embodiment of the present application.
Detailed Description
For the purposes, technical solutions and advantages of the embodiments of the present application to be more apparent, the following detailed description of the specific technical solutions of the present invention will be further described with reference to the accompanying drawings in the embodiments of the present application. The following examples are illustrative of the present application, but are not intended to limit the scope of the present application.
In the following description, suffixes such as "module" or "unit" for representing elements are used only for facilitating the description of the present application, and have no specific meaning per se. Thus, "module" or "unit" may be used in a hybrid.
In the related art, the transistors of the mainstream memory include a Planar transistor (Planar) and a buried channel transistor (Buried Channel Array Transistor, BCAT), however, both the Planar transistor and the buried channel transistor are structured such that the source and the drain are located on both sides of the gate. Fig. 1A is a schematic structural diagram of a planar transistor in the related art, and fig. 1B is a schematic structural diagram of a buried channel transistor in the related art, as shown in fig. 1A and 1B, in which a source S and a drain D of the transistor are respectively located at two horizontal sides of a gate G. With this structure, the source and drain occupy different positions, respectively, so that the area of either the planar transistor or the buried channel transistor is large.
In addition, since a transistor can be manufactured over a silicon substrate, the transistor can be used in various memories such as a DRAM. In general, a DRAM is composed of a plurality of memory cells, each of which is mainly composed of one transistor and one capacitor controlled by the transistor, i.e., a DRAM is a memory cell of 1 transistor and 1 capacitor C (1T 1C). Fig. 1C is a schematic diagram of a DRAM memory cell formed by using a planar transistor in the related art, fig. 1D is a schematic diagram of a DRAM memory cell formed by using a buried channel transistor in the related art, as shown in fig. 1C and 1D, a source (or drain) 101 of a transistor in the DRAM memory cell is connected to a bit line 102, and a drain (or source) 103 is connected to a capacitor 104. For Chips formed using BCAT, packaging is typically performed using Chip On Board (COB) to form a memory. Because the source and drain of the planar transistor and the buried channel transistor are respectively located at two sides of the gate level, the bit line and the capacitor in the DRAM memory cell are also located at the same side of the gate, and the connection between the bit line, the transistor and the capacitor, the connection between the Word Line (WL) and the transistor, and the like are also required to be implemented in the subsequent process, so that the circuit wiring is complex in the memory array area of the DRAM memory, and the manufacturing process is difficult.
Based on the above-mentioned problems in the related art, embodiments of the present application provide a pillar-shaped transistor and a method for manufacturing the same, a semiconductor device and a method for manufacturing the same, which can provide a transistor structure with a smaller area, and by the transistor structure provided by the embodiments of the present application, the circuit layout inside the memory can be simplified, and the process difficulty of manufacturing the memory can be reduced.
Fig. 2 is a schematic structural diagram of an alternative pillar transistor provided in an embodiment of the present application, as shown in fig. 2, where the pillar transistor 20 includes: channel region 201, source 202, drain 203, gate 204, and gate oxide 205.
Wherein the channel region 201 has a vertical structure, and the source 202 is located at a first end of the channel region 201; the drain 203 is located at a second end of the channel region 201, where the first end and the second end are opposite ends of the channel region in a first direction (e.g., a Z-axis direction in fig. 2) of a thickness direction of a wafer on which the channel region is formed. In the embodiment of the present application, the positions of the source electrode 202 and the drain electrode 203 may be interchanged.
The gate 204 is located on either side of the channel region 201 and, corresponding to the channel region 204, a gate oxide 205 is located between the channel region 201 and the gate 204.
In the embodiment of the application, the source electrode and the drain electrode are respectively located at two opposite ends of the wafer forming the channel region in the thickness direction, namely, the source electrode and the drain electrode of the columnar transistor provided by the embodiment of the application are located in two opposite surfaces of the wafer, so that the area of the transistor is greatly reduced.
The pillar transistor provided by the embodiments of the present application may be formed by the method for manufacturing the pillar transistor provided by the following embodiments.
Fig. 3A is a schematic flow chart of an alternative method for manufacturing a pillar transistor according to an embodiment of the present application, as shown in fig. 3A, where the method for manufacturing a pillar transistor includes the following steps:
step S301, providing a wafer, wherein the wafer has a plurality of transistor forming regions, each transistor forming region has a transistor column, and each transistor column has a bare sidewall.
And step S302, sequentially forming a gate oxide layer and a gate on the side wall of each transistor column.
Step S303, forming a source electrode at the first end of the crystal string.
And step S304, forming a drain electrode at the second end of the crystal column.
The first end and the second end are respectively opposite ends of the crystal string in a first direction, and the first direction is the thickness direction of the wafer; a column of transistors between the source and the drain forms a channel region of the transistor.
Next, referring to fig. 3B to 3L, a method for manufacturing a pillar transistor according to an embodiment of the present application is described in further detail.
In this embodiment, the transistor forming regions are regions for forming transistors on a wafer, each of the transistor forming regions has a transistor pillar, and each transistor pillar has a bare sidewall. The transistor forming region also has an insulating layer surrounding other sidewalls of the transistor string.
First, referring to fig. 3B to 3E, step S301 is performed to provide a wafer having a plurality of transistor forming regions, each of the transistor forming regions having a transistor pillar, each of the transistor pillars having a bare sidewall. In some embodiments, the transistor forming region is formed by:
and step S3011, partially etching the wafer along the first direction by taking the first surface of the wafer as an etching starting point to form grid-shaped etching grooves formed by a plurality of silicon columns.
Each silicon column has a first preset thickness, and the first preset thickness is smaller than the initial thickness of the wafer; the first surface of the wafer is any surface of the wafer along the first direction.
Here, the thickness direction of the wafer is defined as a first direction. Defining two second directions and a third direction intersecting each other in a top surface or a bottom surface of the wafer perpendicular to the first direction, and determining the top surface or the bottom surface of the wafer perpendicular to the first direction based on the second direction and the third direction. For example, the second direction and the third direction are perpendicular to each other, so that the first direction, the second direction and the third direction are perpendicular to each other. Here, the first direction may be defined as a Z-axis direction, the second direction as an X-axis direction, and the third direction as a Y-axis direction.
Fig. 3B is a cross-sectional view of the grid-shaped etching groove provided in the embodiment of the present application along the first direction, and fig. 3C is a top view of the grid-shaped etching groove provided in the embodiment of the present application, and in combination with fig. 3B and 3C, it can be seen that, along the Z-axis direction, the first surface 30-1 of the wafer is taken as an etching starting point, and the wafer 30 is partially etched to form the grid-shaped etching groove 31 composed of a plurality of silicon pillars 301, where each silicon pillar 301 is located at an intersection point in the grid, and an equal gap exists between any two adjacent silicon pillars. In this embodiment, each silicon pillar 301 has a first preset thickness a in the Z-axis direction, where the first preset thickness is smaller than an initial thickness B of the wafer; the first surface 30-1 of the wafer is any surface of the wafer along the Z-axis direction. The wafer also includes a second side 30-2 opposite the first side 30-1.
Here, the wafer may be etched using a dry etching process, for example, a plasma etching process or a reactive ion etching process. It should be noted that, in the embodiment of the present application, the etching of the wafer is a partial etching performed in the thickness direction of the wafer, that is, the etching process does not etch through the wafer.
And step S3012, depositing an insulating material in the grid-shaped etched grooves to form an insulating layer surrounding each silicon column.
In the embodiment of the application, the insulating material may be a silicon dioxide material or other insulating materials. Fig. 3D is a top view illustrating an insulating layer formed in the grid-like etched trenches according to an embodiment of the present application, and as shown in fig. 3D, an insulating material SiO is deposited in the grid-like etched trenches 31 2 The periphery of each silicon column 301 is filled with an insulating material SiO 2 An insulating layer 32 is formed.
In the actual process of depositing the insulating material, the insulating material SiO 2 Will cover the surface of the silicon pillars 301, typically after deposition is completePolishing to remove excessive insulating material SiO by adopting chemical mechanical polishing (Chemical Mechanical Polishing, CMP) process 2 To expose the surface of the silicon pillars 301.
Step S3013, etching the silicon pillar and the insulating layer to form the transistor pillar with a exposed sidewall, thereby obtaining the transistor forming region.
In some embodiments, the etching the silicon pillar and the insulating layer to form the crystal pillar having a bare side wall comprises: and taking the edge position of the silicon column as an etching starting point, carrying out partial etching treatment on the silicon column and the insulating layer along a first direction, removing the silicon column and the insulating layer which have preset dimensions in the second direction and have the first preset thickness in the first direction, forming the crystal column with a naked side wall, and forming an etching groove.
Fig. 3E is a top view of a transistor column according to an embodiment of the present application, as shown in fig. 3E, with an edge position of the silicon column as an etching start point, performing etching treatment on the silicon column and the insulating layer along an X-axis direction, removing the silicon column and the insulating layer having a preset dimension C in the X-axis direction and a first preset thickness a in the Z-axis direction, and forming a transistor column 302 and an etching groove 303, thereby forming a transistor forming region 30', wherein the transistor column has a bare sidewall 302-1. In this embodiment, the preset dimension C is smaller than the initial dimension D of the silicon pillar 301 in the X-axis direction.
It should be noted that, many transistors are formed on one wafer, and thus, there are many transistor forming regions in one wafer, and in this embodiment, for convenience of explanation, only a limited number of transistor forming regions are exemplarily shown.
Next, referring to fig. 3F and 3G, step S302 is performed to sequentially form a gate oxide layer and a gate on the sidewall of each of the transistor columns.
In some embodiments, before performing step S302, the method for manufacturing a transistor further includes:
and S10, depositing and forming a first isolation layer at the bottom of the etched groove.
Here, the material of the first isolation layer includes, but is not limited to, any one of the following: silicon nitride, silicon oxynitride, silicon carbide, or silicon dioxide.
Next, a subsequent formation process will be described by taking a column of crystals on the wafer as an example. Fig. 3F is a schematic structural diagram of forming a first isolation layer according to an embodiment of the present application, as shown in fig. 3F, where a first isolation layer 304 is deposited at the bottom of an etched groove (not shown in fig. 3F). Here, the first isolation layer may be deposited by any suitable deposition process.
In some embodiments, after forming the first isolation layer, the above-mentioned process of forming the gate oxide layer and the gate is performed, where the gate oxide layer and the gate are sequentially formed on the sidewall of each of the transistor columns, and the method includes the following steps:
In step S3021, an initial gate oxide layer is formed on the sidewall of the transistor string by in-situ oxidation.
Fig. 3G is a schematic structural diagram of forming an initial gate oxide layer according to an embodiment of the present application, as shown in fig. 3G and fig. 3F, where the exposed portion of the sidewall 302-1 'of the transistor column 301 may be oxidized in situ by heating or pressurizing to form an initial gate oxide layer 305'.
And step S3022, depositing a polysilicon material in the etched recess to form a polysilicon layer.
Here, the polysilicon layer may be formed by depositing a polysilicon material in the etched recesses after the first isolation layer 304 is deposited through a process of chemical vapor deposition (Chemical Vapor Deposition, PVD), physical vapor deposition (Physical Vapour Deposition, PVD), or atomic layer deposition (Atomic Layer Deposition, ALD).
In step S3023, in the first direction, etching is performed on the initial gate oxide layer and the polysilicon layer at the same time, and the initial gate oxide layer and the polysilicon layer with partial thickness in the first direction are removed to form the gate oxide layer and the gate.
Fig. 3H is a schematic structural diagram of forming a gate oxide layer and a gate according to an embodiment of the present application, and as shown in fig. 3H, the initial gate oxide layer and the polysilicon layer formed above are simultaneously partially etched along the Z-axis direction, so as to obtain a gate oxide layer 305 and a gate 306. In this embodiment, a dry etching technique may be used to etch the initial gate oxide layer and the polysilicon layer.
In some embodiments, after forming the gate oxide layer and the gate, the method of manufacturing the transistor further comprises:
and S11, depositing a second isolation layer in the etched groove, wherein the second isolation layer is positioned in a projection area of the crystal column in the second direction, and the dimension of the second isolation layer in the third direction is equal to the dimension of the crystal column in the third direction.
In this embodiment of the present application, the third direction is perpendicular to the second direction and the first direction in pairs. In other embodiments, the third direction may not be perpendicular to the second direction, and the included angle between the third direction and the second direction may be any angle.
Here, the material of the second isolation layer includes, but is not limited to, any one of the following: silicon nitride, silicon oxynitride, silicon carbide, or silicon dioxide; the second isolation layer is the same as or different from the first isolation layer.
Fig. 3I is a schematic structural diagram of forming a second isolation layer according to the embodiment of the present application, as shown in fig. 3I, the second isolation layer 307 is located in a projection area of the wafer pillar 302 in the X-axis direction, and a dimension of the second isolation layer in the Y-axis direction is equal to a dimension of the wafer pillar in the Y-axis direction.
Referring next to fig. 3J, step S303 is performed to form a source electrode at the first end of the transistor string.
Here, the first end of the crystal string is an end of the crystal string in the Z-axis direction. Fig. 3J is a schematic view of a structure for forming a source electrode according to an embodiment of the present application, and as shown in fig. 3J, the source electrode 308 is formed by performing ion implantation on a first end of a transistor column.
In some embodiments, the shape of the source includes any one of: square, semi-circular, triangular or any polygon.
In some embodiments, before performing step S304, the method for manufacturing a transistor further includes:
and step S12, starting from the second surface of the wafer, thinning the wafer until the first isolation layer and the second end of the crystal column are exposed.
Here, with continued reference to fig. 3J, the second side 30-2 of the wafer is the side opposite the first side 30-1 of the wafer. In this embodiment, before the second surface of the wafer is thinned, the first surface of the wafer needs to be fixed on a supporting structure, so as to prevent the structure of the transistor from being damaged when the second surface 30-2 of the wafer is thinned.
The first end and the second end are opposite ends of the crystal string in a first direction, respectively. Fig. 3K is a schematic structural diagram of a transistor after thinning the second surface of the wafer according to the embodiment of the present application, and as shown in fig. 3K, the thinning process is performed on the second surface of the wafer, which exposes the first isolation layer 304 and the second end 309' of the transistor column.
Next, referring to fig. 3L, step S304 is performed to form a drain at the second end of the transistor string.
Fig. 3L is a schematic diagram of a structure for forming a drain according to an embodiment of the present application, and as shown in fig. 3L, the drain 309 is formed by performing ion implantation on the second end 309' of the transistor string.
In some embodiments, the shape of the drain electrode includes any one of: square, semi-circular, triangular or any polygon.
Fig. 3M and 3N are schematic structural diagrams of an alternative pillar transistor according to an embodiment of the present application, where, as shown in fig. 3M, the cross-sectional shapes of the source and the drain of the pillar transistor are semicircular, and as shown in fig. 3N, the cross-sectional shapes of the source and the drain of the pillar transistor are triangular.
In the embodiment of the application, the positions of the source electrode and the drain electrode can be interchanged, and the shapes of the source electrode and the drain electrode of the columnar transistor formed by the embodiment of the application can be the same or different.
With continued reference to fig. 3L, in an embodiment of the present application, after forming the source and drain, a column of transistors between the source and drain forms a channel region 310 of the transistor.
The columnar transistor formed by the columnar transistor manufacturing method provided by the embodiment of the application has the advantages that the source electrode and the drain electrode are respectively positioned at the first end and the second end of the channel region in the first direction, and the first direction is the thickness direction of the wafer forming the channel region, so that the area of the transistor is greatly reduced.
In some embodiments, when the pillar transistor provided in the embodiments of the present application is applied to a memory, since the drain and the source of the pillar transistor are located on different sides of a wafer, different structures to which the source and the drain are connected in the memory can be respectively designed in two sides of the wafer, so that the circuit layout inside the memory is simplified, and the process difficulty of manufacturing the memory is reduced.
An embodiment of the present application provides a semiconductor device, fig. 4A is a schematic structural diagram of an alternative semiconductor device provided in the embodiment of the present application, as shown in fig. 4A, where the semiconductor device 40 includes: at least one memory cell, word line 402, and bit line 403.
Wherein each of the memory cells comprises at least one pillar transistor 401, the pillar transistor 401 comprising at least a gate G, a source S and a drain D.
The pillar transistors 401 further include a channel region, and a source of each pillar transistor is located at a first end of the channel region; the drain electrode of each columnar transistor is positioned at the second end of the channel region; the first end and the second end are respectively opposite ends of the channel region in a first direction, and the first direction is a thickness direction of a wafer forming the channel region. That is, the pillar transistor 401 in the embodiment of the present application has a vertical channel, and the source and the drain of the pillar transistor 401 are located at two ends of the vertical channel, respectively.
In this embodiment, the word line 402 is connected to the gate G of the pillar transistor 401, and is used to provide a word line voltage, and control the pillar transistor 401 to be turned on or off by the word line voltage.
The bit line 403 is connected to the source S or drain D of the pillar transistor 401 for performing a read or write operation on the memory cell when the pillar transistor is on.
In some embodiments, when the source S of the pillar transistor 401 is connected to the bit line 403, the drain of the pillar transistor is grounded; when the drain of the pillar transistor 401 is connected to the bit line 403, the source of the pillar transistor is grounded.
The semiconductor device provided by the embodiment of the application comprises various types of memories. For example, NAND Flash (Flash), nors Flash, DRAM, static random access Memory (Static Random Access Memory, SRAM), and Phase-Change Memory (PCM).
In some embodiments, when the semiconductor device is a DRAM, the memory cell further includes: and a storage capacitor.
As shown in fig. 4B, an alternative schematic structural diagram of a DRAM memory cell according to an embodiment of the present application may be seen, in a DRAM memory cell 40', one end of a storage capacitor 404 is connected to the drain or the source of the pillar transistor 401, the other end of the storage capacitor 404 is grounded, and the storage capacitor 404 is used for storing data written into the memory cell.
In some embodiments, when the semiconductor device is a PCM, the memory cell further includes: and the resistance can be adjusted.
As shown in fig. 4C, an alternative schematic structure of the PCM memory cell according to the embodiment of the present application is shown, where in the PCM memory cell 40″ an adjustable resistor 405 is connected between the bit line 403 and the source of the pillar transistor 401, or the adjustable resistor 405 is connected between the bit line 403 and the drain of the pillar transistor 401, and the adjustable resistor 405 is used to adjust the state of the data stored in the memory cell by using the bit line voltage provided by the bit line.
In some embodiments, when the semiconductor device includes a plurality of the memory cells, the semiconductor device is a NAND Flash or a Nor Flash. When a plurality of memory units are connected in parallel, the semiconductor device is Nor Flash; when a plurality of memory cells are connected in series, the semiconductor device is a NAND Flash.
In the embodiments of the present application, some common semiconductor devices are merely exemplified, and the protection scope of the present application is not limited thereto, and any semiconductor device including the pillar transistor provided in the embodiments of the present application belongs to the protection scope of the present application.
In the embodiment of the application, the structure of the transistor of the semiconductor device is designed to be a novel structure with a vertical channel, so that the area of the memory cell is reduced, and the storage density of the memory cell is improved. Meanwhile, in the pillar transistor in the embodiment of the present application, the source and the drain are located at the upper and lower ends of the vertical channel region, so that during the formation of the semiconductor device, the bit lines or other structures may be disposed on the vertical two sides of the channel region respectively. For example, for a DRAM, the bit lines and capacitors of the DRAM memory cells may be disposed on both sides of the same wafer, respectively, so that the circuit arrangement of the word lines, bit lines and capacitors may be simplified, and the difficulty in the manufacturing process of the semiconductor device may be reduced.
An embodiment of the present application provides a method for forming a semiconductor device, and fig. 5 is a schematic structural diagram of an alternative method for forming a semiconductor device provided in an embodiment of the present application, as shown in fig. 5, where the method includes the following steps:
step S501, forming at least one memory cell, where each memory cell includes at least: a pillar transistor; the pillar transistor includes: a gate, a source and a drain.
Step S502, forming a word line, wherein the word line is connected with the grid electrode of the columnar transistor, is used for providing word line voltage, and controls the on or off of the columnar transistor through the word line voltage.
Step S503, forming a bit line, where the bit line is connected to a source or a drain of the pillar transistor, and the bit line is used to perform a read or write operation on the memory cell when the pillar transistor is turned on.
In some embodiments, pillar transistors in the memory cells are formed by:
in step S5011, silicon in a first surface portion of the first wafer is removed by an etching process to a certain thickness (corresponding to the first preset thickness in the above embodiment), grid-shaped trenches (corresponding to the grid-shaped etched trenches in the above embodiment) with silicon pillars in the middle are formed, silicon dioxide (corresponding to the insulating layer in the above embodiment) is filled in the trenches, and then the surface of the silicon pillars is exposed by chemical mechanical polishing, and finally, a portion of the silicon pillars is removed by etching, so that the side walls of the silicon pillars are exposed (corresponding to the process of forming the crystal pillars in the above embodiment).
Step S5012, forming silicon nitride at the bottom of the trench to serve as a bottom isolation (Spacer) structure (corresponding to the formation of the first isolation layer in the above embodiment).
In step S5013, silicon oxide is formed on the sidewall of the trench by in-situ growth to serve as a gate oxide (corresponding to the initial gate oxide formed in the above embodiment).
Step S5014, filling polysilicon in the trench (corresponding to the formation of the polysilicon layer in the above embodiment), removing the polysilicon on the top by etching to a certain depth, and removing the silicon oxide on the top bare drain (corresponding to step S3023 in the above embodiment).
Step S5015, forming silicon nitride on the top of the trench to serve as a top isolation structure (corresponding to the second isolation layer in the above embodiment).
Step S5016, a source terminal is formed in the transistor region reserved in step S5011 (corresponding to the first end of the transistor column in the above embodiment) by ion implantation.
Step S5017, forming a subsequent corresponding structure on the first surface of the first wafer through various processes; the first wafer is then bonded to the second wafer, and finally the silicon on the back side of the first wafer is thinned until the isolation structures on the bottom and the second side of the first wafer (corresponding to the second end of the column of crystals in the above embodiment) are exposed.
Here, the subsequent corresponding structure includes: bit lines, resistors, capacitors, or the like are formed. The second wafer is provided with various logic circuits, sensors and other elements, and the second wafer and the first wafer are bonded to form a memory together.
In some embodiments, the wafer bonding process is performed prior to the backside silicon thinning process, and the second wafer provides support for the first wafer during the thinning process, preventing damage to the first wafer during the thinning process.
In step S5018, a drain is formed on the second surface of the first wafer at a position (corresponding to the second end of the column) opposite to the source in step S5016 by ion implantation.
Step S5019, finally, a subsequent corresponding structure is formed on the second surface of the first wafer.
Here, the subsequent corresponding structure includes: bit lines, resistors, capacitors, or the like are formed.
By the method for forming the semiconductor device, the channel of the columnar transistor is formed in the vertical direction, and the horizontal section of the columnar transistor can be rectangular (square), semicircular, triangular or any polygonal. In the semiconductor device of the embodiment of the application, the source electrode and the drain electrode of the columnar transistor can be interchanged, and the source electrode and the drain electrode can be respectively processed on two surfaces of the same wafer, so that patterns of the source electrode and the drain electrode can be different.
In the embodiment of the application, the word lines and the bit lines are realized by forming the metal lines at the preset word line positions and the preset bit line positions. The metal lines include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof.
In the embodiment of the application, the structure of the transistor of the semiconductor device is designed to be a novel transistor structure with a vertical channel, so that the area of the memory cell is reduced, and the memory density of the memory cell is improved. Meanwhile, in the pillar transistor in the embodiment of the present application, the source and the drain are located at the upper and lower ends of the vertical channel region, so, in the formation process of the semiconductor device, by combining the wafer bonding and the back side silicon thinning technology, the bit line or other structures can be respectively disposed in two opposite faces of the wafer. For example, for a DRAM, the bit lines and capacitors of the DRAM memory cells may be disposed on both sides of the same wafer, respectively, so that the circuit arrangement of the word lines, bit lines and capacitors may be simplified, and the difficulty in the manufacturing process of the semiconductor device may be reduced.
In several embodiments provided herein, it should be understood that the disclosed apparatus and methods may be implemented in a non-targeted manner. The above described device embodiments are only illustrative, e.g. the division of the units is only one logical function division, and there may be other divisions in practice, such as: multiple units or components may be combined or may be integrated into another system, or some features may be omitted, or not performed. In addition, the components shown or discussed are coupled to each other or directly.
The units described as separate units may or may not be physically separate, and units displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units; some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
The features disclosed in the several method or apparatus embodiments provided in the present application may be arbitrarily combined without conflict to obtain new method embodiments or apparatus embodiments.
The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims (13)

1. A method of manufacturing a pillar transistor, the method comprising:
providing a wafer, wherein the wafer is provided with a plurality of transistor forming areas, each transistor forming area is provided with a transistor column, and each transistor column is provided with an exposed side wall;
Forming a grid oxide layer and a grid on the side wall of each crystal column in sequence;
forming a source electrode at a first end of the transistor column;
forming a drain electrode at a second end of the crystal column, wherein the first end and the second end are opposite ends of the crystal column in a first direction, and the first direction is a thickness direction of the wafer; a column of transistors between the source and the drain forms a channel region of the transistor;
before forming the drain, the method further comprises: thinning the wafer from the second surface of the wafer until the second end of the crystal column is exposed; wherein the second end of the crystal string is located between the first end of the crystal string and the second face of the wafer;
the forming a drain at the second end of the transistor string includes: and performing ion implantation on the exposed second end of the crystal column to form the drain electrode.
2. The method of claim 1 wherein the transistor forming region further has an insulating layer surrounding other sidewalls of the transistor string; the transistor forming region is formed by:
Partially etching the wafer along the first direction by taking the first surface of the wafer as an etching starting point to form grid-shaped etching grooves formed by a plurality of silicon columns, wherein each silicon column has a first preset thickness which is smaller than the initial thickness of the wafer; the first surface of the wafer is any surface of the wafer along the first direction; the first face of the wafer is the face opposite to the second face of the wafer;
depositing an insulating material in the grid-shaped etched grooves to form an insulating layer surrounding each silicon column;
and etching the silicon column and the insulating layer to form the transistor column with the exposed side wall, thereby obtaining the transistor forming region.
3. The method of claim 2, wherein said etching said silicon pillars and said insulating layer to form said crystal pillars having a bare said sidewalls, comprises:
taking the edge position of the silicon column as an etching starting point, carrying out partial etching treatment on the silicon column and the insulating layer along the first direction, removing the silicon column and the insulating layer which have preset dimensions in the second direction and have the first preset thickness in the first direction, forming the crystal column with the exposed side wall, and forming an etching groove; wherein the preset dimension is less than an initial dimension of the silicon pillar in the second direction; the second direction is perpendicular to the first direction.
4. The method of claim 3, wherein prior to forming the gate oxide layer and the gate, the method further comprises:
depositing a first isolation layer at the bottom of the etched groove;
correspondingly, the step of sequentially forming a gate oxide layer and a gate on the side wall of each transistor column comprises the steps of:
forming an initial gate oxide layer on the side wall of the crystal string in an in-situ oxidation mode;
depositing a polysilicon material in the etching groove to form a polysilicon layer;
and simultaneously etching the initial gate oxide layer and the polysilicon layer in the first direction, and removing part of the initial gate oxide layer and the polysilicon layer in the first direction to form the gate oxide layer and the gate.
5. The method of claim 4, wherein after forming the gate oxide layer and the gate, the method further comprises:
and depositing a second isolation layer in the etched groove, wherein the second isolation layer is positioned in a projection area of the crystal column in the second direction, and the dimension of the second isolation layer in the third direction is equal to the dimension of the crystal column in the third direction.
6. The method of claim 4, wherein the thinning the wafer from the second side of the wafer comprises:
and carrying out thinning treatment on the wafer until the first isolation layer is exposed.
7. The method of claim 1, wherein the source and drain are the same or different shape;
the shape of the source electrode and the drain electrode includes any one of the following: square, semi-circular, triangular or any polygon.
8. A pillar transistor, characterized in that the pillar transistor is manufactured by the manufacturing method of the pillar transistor provided in any one of the above claims 1 to 7; the transistor includes:
a channel region;
a source electrode positioned at a first end of the channel region;
the drain electrode is positioned at the second end of the channel region, wherein the first end and the second end are respectively opposite ends of the channel region in a first direction, and the first direction is the thickness direction of a wafer forming the channel region;
a gate electrode located on either side of the channel region and corresponding to the channel region;
and the gate oxide layer is positioned between the channel region and the gate.
9. A method of forming a semiconductor device, the method comprising:
forming at least one memory cell, wherein each memory cell comprises at least: a pillar transistor; the pillar transistor includes: a gate, a source and a drain; the pillar transistor is manufactured by the manufacturing method of the pillar transistor provided in any one of the above claims 1 to 7;
forming a word line, wherein the word line is connected with the grid electrode of the columnar transistor, is used for providing word line voltage, and controls the on or off of the columnar transistor through the word line voltage;
a bit line is formed, the bit line being connected to the source or drain of the pillar transistor, the bit line being for performing a read or write operation on the memory cell when the pillar transistor is turned on.
10. A semiconductor device, comprising: at least one memory cell, a word line, and a bit line, each of the memory cells comprising at least: the pillar transistor of claim 8; the pillar transistor includes at least: a gate, a source and a drain;
the word line is connected with the grid electrode of the columnar transistor, is used for providing word line voltage and controls the on or off of the columnar transistor through the word line voltage;
The bit line is connected with a source or a drain of the pillar transistor, and is used for performing read or write operations on the memory cell when the pillar transistor is turned on.
11. The semiconductor device according to claim 10, wherein the memory cell further comprises: a storage capacitor;
one end of the storage capacitor is connected with the drain electrode or the source electrode of the columnar transistor, the other end of the storage capacitor is grounded, and the storage capacitor is used for storing data written into the memory unit.
12. The semiconductor device according to claim 10, wherein the memory cell further comprises: an adjustable resistor;
the adjustable resistor is connected between the bit line and the source of the pillar transistor or between the bit line and the drain of the pillar transistor, and is used for adjusting the state of data stored in the memory cell through the bit line voltage provided by the bit line.
13. The semiconductor device according to claim 10, wherein when the semiconductor device includes a plurality of the memory cells, the plurality of the memory cells are connected in parallel or in series.
CN202110422036.9A 2021-04-20 2021-04-20 Pillar transistor and method of manufacturing the same, semiconductor device and method of manufacturing the same Active CN113506737B (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN202110422036.9A CN113506737B (en) 2021-04-20 2021-04-20 Pillar transistor and method of manufacturing the same, semiconductor device and method of manufacturing the same
PCT/CN2021/111345 WO2022222310A1 (en) 2021-04-20 2021-08-06 Transistor and manufacturing method therefor, and semiconductor device and manufacturing method therefor
KR1020237038547A KR20240008849A (en) 2021-04-20 2021-08-06 Transistor and transistor manufacturing method, semiconductor device and semiconductor device manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110422036.9A CN113506737B (en) 2021-04-20 2021-04-20 Pillar transistor and method of manufacturing the same, semiconductor device and method of manufacturing the same

Publications (2)

Publication Number Publication Date
CN113506737A CN113506737A (en) 2021-10-15
CN113506737B true CN113506737B (en) 2023-07-14

Family

ID=78008406

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110422036.9A Active CN113506737B (en) 2021-04-20 2021-04-20 Pillar transistor and method of manufacturing the same, semiconductor device and method of manufacturing the same

Country Status (1)

Country Link
CN (1) CN113506737B (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101556954A (en) * 2008-04-10 2009-10-14 海力士半导体有限公司 Semiconductor device having vertical pillar transistors and method for manufacturing the same
KR20120048985A (en) * 2010-11-08 2012-05-16 에스케이하이닉스 주식회사 Vertical transistor having buried junction and manufacturing method for the same
CN107845579A (en) * 2016-09-19 2018-03-27 格芯公司 The method that bottom and top source/drain regions are formed in vertical transistor devices

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19943760C1 (en) * 1999-09-13 2001-02-01 Infineon Technologies Ag DRAM cell arrangement comprises a substrate with a recess containing a storage node of a capacitor
US7442976B2 (en) * 2004-09-01 2008-10-28 Micron Technology, Inc. DRAM cells with vertical transistors
KR100956476B1 (en) * 2010-01-14 2010-05-07 심재훈 Structure of dram device and manufaturing method thereof
US8207032B2 (en) * 2010-08-31 2012-06-26 Micron Technology, Inc. Methods of forming pluralities of vertical transistors, and methods of forming memory arrays
US10388658B1 (en) * 2018-04-27 2019-08-20 Micron Technology, Inc. Transistors, arrays of transistors, arrays of memory cells individually comprising a capacitor and an elevationally-extending transistor, and methods of forming an array of transistors

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101556954A (en) * 2008-04-10 2009-10-14 海力士半导体有限公司 Semiconductor device having vertical pillar transistors and method for manufacturing the same
KR20120048985A (en) * 2010-11-08 2012-05-16 에스케이하이닉스 주식회사 Vertical transistor having buried junction and manufacturing method for the same
CN107845579A (en) * 2016-09-19 2018-03-27 格芯公司 The method that bottom and top source/drain regions are formed in vertical transistor devices

Also Published As

Publication number Publication date
CN113506737A (en) 2021-10-15

Similar Documents

Publication Publication Date Title
CN113314422B (en) U-shaped transistor and manufacturing method thereof, semiconductor device and manufacturing method thereof
TWI471981B (en) Method for fabricating memory device with buried digit lines and buried word lines
US7439149B1 (en) Structure and method for forming SOI trench memory with single-sided strap
EP2215658A2 (en) Semiconductor constructions, methods of forming capacitors, and methods of forming dram arrays
CN113506736B (en) L-type transistor and method for manufacturing the same, semiconductor device and method for manufacturing the same
JP7437126B2 (en) Nonvolatile memory device and its manufacturing method
CN114373764A (en) Transistor array and manufacturing method thereof, memory and manufacturing method thereof
CN114220765B (en) Memory and manufacturing method thereof
CN113629054A (en) U-shaped transistor array and forming method thereof, semiconductor device and forming method thereof
US8399319B2 (en) Semiconductor device and method for manufacturing the same
WO2023272880A1 (en) Transistor array and manufacturing method therefor, and semiconductor device and manufacturing method therefor
WO2023272881A1 (en) Transistor array and method for manufacturing same, and semiconductor device and method for manufacturing same
CN113506738A (en) T-type double-channel transistor and manufacturing method thereof, semiconductor device and manufacturing method thereof
CN113506737B (en) Pillar transistor and method of manufacturing the same, semiconductor device and method of manufacturing the same
CN113314421B (en) Double-gate transistor and manufacturing method thereof, semiconductor device and manufacturing method thereof
CN113611666A (en) Transistor array and manufacturing method thereof, semiconductor device and manufacturing method thereof
CN116825838A (en) Semiconductor structure and manufacturing method thereof, memory and manufacturing method thereof
WO2022222310A1 (en) Transistor and manufacturing method therefor, and semiconductor device and manufacturing method therefor
US20110170336A1 (en) DRAM Device and Manufacturing Method Thereof
EP4277448A1 (en) Memory and method for forming same
US20230363148A1 (en) Semiconductor device and method of forming the same
US20230245980A1 (en) Semiconductor devices having shielding element
US20230247819A1 (en) Semiconductor devices having shielding elements
US20230200058A1 (en) Semiconductor device and method of forming the same
US20240090197A1 (en) Apparatus comprising a metal portion in the top portion of capacitor structure, and related methods

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant