CN113611666A

CN113611666A - Transistor array and manufacturing method thereof, semiconductor device and manufacturing method thereof

Info

Publication number: CN113611666A
Application number: CN202110749594.6A
Authority: CN
Inventors: 华文宇; 骆中伟; 张帜
Original assignee: ICLeague Technology Co Ltd
Current assignee: ICLeague Technology Co Ltd
Priority date: 2021-07-02
Filing date: 2021-07-02
Publication date: 2021-11-05

Abstract

The present disclosure provides a transistor array and a method of manufacturing the same, a semiconductor device and a method of manufacturing the same, the method of manufacturing the transistor array including: providing a wafer; forming a plurality of insulating strips extending along a first direction in a wafer; the insulating strips divide part of the wafer into a plurality of transistor strips extending along a first direction; etching the transistor strips from the first surface of the wafer to form a plurality of transistor columns arranged in an array; each transistor column has a side wall attached to the insulating strip and an exposed side wall; forming a gate layer semi-surrounding the transistor pillars on exposed sidewalls of each transistor pillar; forming a source electrode of the transistor at the first end of each transistor column; forming a drain of a transistor at a second end of each transistor column; the first end and the second end are two ends of the transistor column opposite to each other in the second direction respectively, and the transistor column between the source electrode and the drain electrode forms a channel region of the transistor.

Description

Transistor array and manufacturing method thereof, semiconductor device and manufacturing method thereof

Technical Field

The present disclosure relates to the field of semiconductor technology, and relates to, but is not limited to, a transistor array and a method for manufacturing the same, and a semiconductor device and a method for manufacturing the same.

Background

Transistors are widely used as switching devices or driving devices in electronic equipment. For example, the transistor may be used in a Dynamic Random Access Memory (DRAM) for controlling a capacitance in each Memory cell.

In the related art, the transistor mainly includes a planar transistor and a buried channel transistor, however, regardless of whether the planar transistor or the buried channel transistor is used, the Source (Source, S) and the Drain (Drain, D) are both located on two horizontal sides of the Gate (Gate, G), and the Source and the Drain occupy different positions respectively, so that the area of the transistor is large. In addition, in the memory device, the source and the drain of the transistor are connected to different structures after being formed, and when the source and the drain are located on two horizontal sides of the gate, the circuit wiring inside the memory is complex and the manufacturing process is difficult.

Disclosure of Invention

Embodiments of the present disclosure provide a transistor array and a method of manufacturing the same, a semiconductor device and a method of manufacturing the same.

In a first aspect, an embodiment of the present disclosure provides a method for manufacturing a transistor array, including:

providing a wafer;

forming a plurality of insulating strips extending along a first direction in the wafer; the insulating strips divide part of the wafer into a plurality of transistor strips extending along the first direction; the first direction is parallel to the surface of the wafer;

etching the transistor strips from the first surface of the wafer to form a plurality of transistor columns arranged in an array; each transistor column has a side wall attached to the insulating strip and an exposed side wall;

forming a gate layer semi-surrounding each of the transistor columns on exposed sidewalls thereof;

forming a source of each of the transistors at a first end of each of the transistor columns;

forming a drain of said transistor at a second end of each of said transistor columns; the first end and the second end are two opposite ends of the transistor column in a second direction respectively, and the transistor column between the source electrode and the drain electrode forms a channel region of the transistor; the second direction is perpendicular to the surface of the wafer.

In the above solution, the etching of the transistor strips from the first surface of the wafer to form a plurality of transistor columns arranged in an array includes:

etching the transistor strips from the first surface of the wafer along a second direction, and forming first grooves between the adjacent insulating strips; each transistor bar is divided into a plurality of transistor columns by the first grooves; and a plurality of transistor columns corresponding to the polycrystalline tube strips form the plurality of transistor columns arranged in an array.

In the above aspect, the gate layer includes: a gate oxide layer and a gate electrode;

forming a gate layer semi-surrounding each of the transistor pillars at exposed sidewalls of the transistor pillars, comprising:

forming the gate oxide layer half-surrounding the transistor pillars on exposed sidewalls of each transistor pillar;

forming the gate electrode covering the gate oxide layer around the gate oxide layer; the gate electrodes of a plurality of divided transistor columns of each transistor strip are connected with each other, and the connected gate electrodes are used as word lines of the same column of transistors corresponding to the transistor columns.

In the above scheme, the gate oxide layer half-surrounding the transistor pillar is formed on the exposed sidewall of each transistor pillar; the method comprises the following steps:

and carrying out oxidation treatment on the side wall of the transistor column exposed in the first groove in an in-situ oxidation mode to form the gate oxide layer which semi-surrounds the transistor column.

In the above solution, forming the gate electrode covering the gate oxide layer around the gate oxide layer includes:

and depositing a conductive material in the first groove to form the gate electrode covering the gate oxide layer.

In the above solution, the forming a source of the transistor at the first end of each of the transistor columns includes:

and performing ion implantation on the first end of each transistor column close to the first surface of the wafer to form a source electrode of each transistor.

In the above scheme, the forming a drain of the transistor at the second end of each of the transistor columns includes:

thinning the wafer from the second surface of the wafer along a second direction to expose a second end of the transistor column away from the first surface of the wafer; wherein the second surface is opposite the first surface;

and performing ion implantation on the second end of each transistor column to form a drain electrode of each transistor.

In the above scheme, each transistor column is located at one side of the insulating strip;

alternatively, the first and second electrodes may be,

each of the transistor columns is partially embedded in the insulating strip.

In the above solution, a cross-sectional shape of each of the transistors parallel to the predetermined plane includes any one of:

squareness;

an ellipse;

a semicircle;

any polygon;

wherein the predetermined plane is perpendicular to the second direction

In the above scheme, the transistor is cylindrical; the first end and the second end are substantially the same in size in the first direction, and the first end and the second end are substantially the same in size in a third direction; the third direction is parallel to the surface of the wafer and is vertical to the first direction;

alternatively, the first and second electrodes may be,

the transistor is L-shaped; the first end and the second end differ in size in the first direction, and/or the first end and the second end differ in size in a third direction.

In a second aspect, embodiments of the present disclosure provide a transistor array, comprising: a plurality of transistors and a plurality of insulating strips arranged in an array;

the transistor includes:

a channel region;

a source electrode positioned at a first end of the channel region;

the drain electrode is positioned at a second end of the channel region, wherein the first end and the second end are two opposite ends of the channel region in a second direction respectively, and the second direction is vertical to the surface of a wafer for forming the transistor array;

a gate layer semi-surrounding the channel region;

the insulating strip extends along a first direction and is attached to one row of transistors in the transistor array, and the first direction is parallel to the row arrangement direction of the transistor array.

In a third aspect, embodiments of the present disclosure provide a method for forming a semiconductor device, the method including:

forming at least one memory array; wherein each of the memory arrays comprises at least: a transistor array comprising a plurality of transistors arranged in an array; the transistor includes: a gate, a source and a drain; the transistor array is manufactured by the manufacturing method of the transistor array provided by the embodiment of the disclosure;

forming a plurality of bit lines which are arranged in parallel along a third direction; and each bit line is connected with the source electrode or the drain electrode of the transistors which are arranged in parallel along the third direction, and the bit lines are used for executing reading or writing operation on the memory unit when the transistors are conducted.

In a fourth aspect, an embodiment of the present disclosure provides a semiconductor device, including:

at least one memory array and a plurality of bit lines arranged in parallel along a third direction;

each of the memory arrays comprises: an array of transistors as provided by embodiments of the present disclosure; the transistor includes at least: a gate, a source and a drain; the third direction is intersected with the first direction, and a plane where the third direction and the first direction are located is perpendicular to the first direction;

the grid electrodes of the transistors which are arranged in parallel along the first direction are connected and used for receiving word line voltage and controlling the transistors to be switched on or switched off through the word line voltage;

each bit line is connected with the source electrode or the drain electrode of the transistors which are arranged in parallel along the third direction, and the bit lines are used for executing reading or writing operation on the memory units when the transistors are conducted.

In the above solution, the memory array further includes: a plurality of capacitors;

one end of the capacitor is connected with the drain electrode or the source electrode of the transistor, the other end of the capacitor is grounded, and the capacitor is used for storing data written into the memory array.

In the above solution, the memory array further includes: a plurality of resistors;

the resistor is connected between the bit line and the source of the transistor or between the bit line and the drain of the transistor, and the resistor is used for adjusting the state of data stored in the memory array through the bit line voltage provided by the bit line.

According to the transistor array and the manufacturing method thereof, the semiconductor device and the manufacturing method thereof, the source electrode and the drain electrode of the middle transistor extend along the thickness direction of the wafer, so that the occupied area of a single transistor in the horizontal direction is reduced, the number of transistors which can be arranged in a unit area is increased, and the density of the transistors in the transistor array is improved; meanwhile, the grid electrode of the transistor semi-surrounds the transistor channel along the horizontal direction, so that the control capability of the grid electrode can be increased, and the performance of the transistor is improved. The transistor provided by the embodiment of the disclosure can be used for forming a memory, and the drain electrode and the source electrode of the transistor are located on different surfaces of the wafer, so that different structures connected with the source electrode and the drain electrode in the memory can be respectively designed in two surfaces of the wafer, namely in two opposite surfaces of the wafer, thereby simplifying the circuit layout inside the memory and reducing the process difficulty of manufacturing the memory.

Drawings

In the drawings, which are not necessarily drawn to scale, like reference numerals may describe similar components in different views. Like reference numerals having different letter suffixes may represent different examples of similar components. The drawings illustrate generally, by way of example, but not by way of limitation, various embodiments discussed herein.

FIG. 1A is a schematic diagram of a planar transistor in the related art;

FIG. 1B is a schematic diagram of a buried channel transistor in the related art;

FIG. 1C is a schematic diagram of a DRAM memory array formed by using planar transistors in the related art;

FIG. 1D is a schematic diagram of a DRAM memory array formed using buried channel transistors according to the prior art;

fig. 2A is a schematic structural diagram of a transistor array according to an embodiment of the disclosure;

fig. 2B is a schematic structural diagram of another transistor array provided in the embodiments of the present disclosure;

FIG. 3 is a schematic flow chart illustrating a method for fabricating a transistor array according to an embodiment of the present disclosure;

fig. 4A to 4O are schematic process diagrams of a method for manufacturing a pillar-shaped transistor according to an embodiment of the present disclosure;

fig. 5A to 5D are schematic structural diagrams of horizontal cross sections at channels of several transistors according to an embodiment of the present disclosure;

fig. 6A to 6D are schematic perspective views of several single transistors provided in the embodiments of the present disclosure;

fig. 7A to 7F are schematic process diagrams of a method for manufacturing an inverted L-shaped transistor according to an embodiment of the present disclosure;

fig. 8A is a schematic structural diagram of a semiconductor device according to an embodiment of the present disclosure;

fig. 8B is a schematic partial structure diagram of a semiconductor device according to an embodiment of the present disclosure;

FIG. 8C is a schematic structural diagram of a DRAM memory array according to an embodiment of the present disclosure;

FIG. 8D is a schematic diagram illustrating a PCM memory array according to an embodiment of the present disclosure;

fig. 9 is a schematic flow chart of a method for forming a semiconductor device according to an embodiment of the present disclosure.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more clear, specific technical solutions of the present disclosure will be described in further detail below with reference to the accompanying drawings in the embodiments of the present disclosure. The following examples are intended to illustrate the present disclosure, but are not intended to limit the scope of the present disclosure.

In the following description, suffixes such as "module" or "unit" used to denote elements are used only for facilitating the explanation of the present disclosure, and have no specific meaning in itself. Thus, "module" or "unit" may be used mixedly.

In the related art, transistors of mainstream memories include a Planar Transistor (Planar) and a Buried Channel Transistor (BCAT), but in both the Planar Transistor and the Buried Channel Transistor, a source and a drain are located on both horizontal sides of a gate.

Fig. 1A is a schematic structural view of a planar transistor in the related art, and fig. 1B is a schematic structural view of a buried channel transistor in the related art. As shown in fig. 1A and 1B, the source and the drain of the related art transistor are respectively located at both horizontal sides of the gate, and thus, the source and the drain occupy different positions in the horizontal plane, respectively, so that the horizontal area of either the planar transistor or the buried channel transistor is large.

In addition, since a transistor can be manufactured over a silicon substrate, the transistor can be used in various memories, for example, a dynamic random access memory. Generally, a DRAM is composed of a plurality of memory arrays, each of which mainly includes a transistor and a capacitor operated by the transistor, i.e., the DRAM includes 1 transistor and 1 capacitor C (1T 1C).

Fig. 1C is a schematic structural view of a related art DRAM memory array formed using planar transistors, and fig. 1D is a schematic structural view of a related art DRAM memory array formed using buried channel transistors. As shown in fig. 1C and 1D, a source (or drain) 101 of a transistor in a DRAM memory array is connected to a bitline 102, and a drain (or source) 103 is connected to a capacitor 104. For Chips formed by BCAT, Chip On Board (COB) packaging is generally used to form the memory.

Because the source and the drain of the planar transistor and the buried channel transistor are respectively located at two horizontal sides of the gate, the bit line and the capacitor in the DRAM memory array are also located at the same side of the gate, and the connection among the bit line, the transistor and the capacitor, the connection between the Word Line (WL) and the transistor, and the like are also required to be realized in the subsequent process, thereby causing the memory array region of the DRAM memory to have complicated circuit wiring and larger manufacturing process difficulty.

Fig. 2A is a schematic structural diagram of a transistor array 200 according to an embodiment of the disclosure. Referring to fig. 2A, the transistor array 200 includes: a plurality of transistors and a plurality of insulating strips which are arranged in an array; wherein the transistor comprises a pillar shaped transistor 210.

Fig. 2B is a schematic structural diagram of another transistor array 200 according to an embodiment of the disclosure. Referring to fig. 2B, the transistor array 200 includes: a plurality of transistors and a plurality of insulating strips which are arranged in an array; wherein the transistor comprises an L-shaped transistor 220.

For example, the arrangement of the plurality of transistors arranged in an array may include: n transistors are arranged in parallel along the X-axis direction, and M transistors are arranged in parallel along the Y-axis direction, so that a transistor array 200 of N × M transistors is formed. It is understood that N and M are both natural numbers, and the values of N and M are not both 1.

Specifically, fig. 2A is a schematic structural diagram of a pillar-shaped transistor 210 according to an embodiment of the present disclosure. Referring to fig. 2A, the pillar shaped transistor 210 includes:

a channel region 211;

a source 212 at a first end of the channel region 211;

a drain 213 located at a second end of the channel region 211, where the first end and the second end are two opposite ends of the channel region 211 in a second direction, and the second direction is perpendicular to a surface of a wafer for forming the transistor array;

a gate layer 214 semi-surrounding the channel region 211;

the insulating strip 215 extends along a first direction, and is attached to a column of transistors in the transistor array, and the first direction is parallel to a column arrangement direction of the transistor array.

It is understood that the pillar-shaped transistor 210 provided by the embodiment of the present disclosure has a vertical channel (i.e., the channel region 211), and the source electrode 212 and the drain electrode 213 of the pillar-shaped transistor 210 are respectively located at two ends (i.e., the first end and the second end) of the vertical channel, which are oppositely disposed. Here, the positions of the source electrode 212 and the drain electrode 213 may be interchanged.

Illustratively, the first direction may be parallel to the Y-axis direction, the column arrangement direction of the transistor array 200 may be parallel to the Y-axis direction, and the row arrangement direction of the transistor array 200 may be parallel to the X-axis direction.

The second direction is perpendicular to the surface of the wafer used to form the transistor array, and may also be understood as the direction of the wafer thickness. Illustratively, the second direction may be parallel to the Z-axis direction.

In the embodiments of the present disclosure, the gate layer 214 may include a gate oxide layer 2141 and a gate electrode 2142; the gate oxide layer 2141 is used to electrically isolate the channel region 211 from the gate electrode 2142. The gate electrodes of the plurality of transistors located in the same column may be of an integral structure.

In the embodiment of the present disclosure, the source electrode 212 and the drain electrode 213 are respectively located at two opposite ends in the thickness direction of the wafer forming the channel region 211, that is, the source electrode 212 and the drain electrode 213 of the pillar-shaped transistor 210 provided in the embodiment of the present disclosure are located in two opposite faces of the wafer, so that the area of the transistor is greatly reduced.

Fig. 3 is a schematic flow chart illustrating a method for manufacturing a transistor array according to an embodiment of the present disclosure. As shown in fig. 3, a method for manufacturing a transistor array according to an embodiment of the present disclosure includes the following steps:

step S301: providing a wafer;

step S302: forming a plurality of insulating strips extending along a first direction in the wafer; the insulating strips divide part of the wafer into a plurality of transistor strips extending along the first direction; the first direction is parallel to the surface of the wafer;

step S303: etching the transistor strips from the first surface of the wafer to form a plurality of transistor columns arranged in an array; each transistor column has a side wall attached to the insulating strip and an exposed side wall;

step S304: forming a gate layer semi-surrounding each of the transistor columns on exposed sidewalls thereof;

step S305: forming a source of each of the transistors at a first end of each of the transistor columns;

step S306: forming a drain of said transistor at a second end of each of said transistor columns; the first end and the second end are two opposite ends of the transistor column in a second direction respectively, and the transistor column between the source electrode and the drain electrode forms a channel region of the transistor; the second direction is perpendicular to the surface of the wafer.

In some embodiments, the transistor may include a pillar transistor 210, and the method for manufacturing the pillar transistor 210 according to the embodiments of the present disclosure is described in further detail with reference to fig. 4A to 4O.

First, referring to fig. 4A, step S301 is executed to provide a wafer 30. The wafer may include at least one transistor array forming region as described above. The constituent materials of the wafer may include: silicon, germanium, and the like.

In step S302, the first surface of the wafer is any surface perpendicular to the thickness direction of the wafer.

Here, the thickness direction of the wafer or the direction perpendicular to the surface of the wafer is defined as a second direction. A first direction and a third direction intersecting each other are defined in a top surface or a bottom surface of the wafer perpendicular to the second direction, and the top surface or the bottom surface of the wafer perpendicular to the second direction can be determined based on the first direction and the third direction.

In some embodiments, the second direction and the third direction are perpendicular to each other, such that the first direction, the second direction, and the third direction are perpendicular to each other two by two. Here, in practical applications, the first direction may be defined as a Y-axis direction, the second direction may be defined as a Z-axis direction, and the third direction may be defined as an X-axis direction.

In some embodiments, the first direction and the third direction intersect but are not perpendicular, i.e., the angle between the second direction and the third direction may be any angle.

Fig. 4B is a perspective view of the cross arrangement of the insulating strips 301 and the transistor strips 302 on the wafer according to the embodiment of the disclosure. Fig. 4C is a perspective view of a plurality of transistor columns arranged in an array according to an embodiment of the disclosure, and fig. 4D is a cross-sectional view taken along AA' in fig. 4C.

Here, the material of the insulating strip 301 includes, but is not limited to, any one of the following: silicon nitride, silicon oxynitride, silicon carbide or silicon dioxide.

In practical application, a wafer may be etched to obtain a groove extending along the Y-axis direction, and then the groove is filled with an insulating material, so as to obtain the insulating strips 301 and the transistor strips 302 arranged in a crossing manner.

As can be seen from fig. 4C to 4D, in step S303, the transistor bars 302 are partially etched along the Z-axis direction using the first surface 30-1 of the wafer as an etching starting point to form a plurality of transistor columns 3021 arranged in an array. Each transistor pillar 3021 has a sidewall attached to the insulating strip and an exposed sidewall.

It is understood that, taking the horizontal cross section of the transistor as a square as an example, when the transistor is a first type semi-surrounding vertical transistor, each transistor pillar 3021 has one sidewall attached to the insulating strip and three exposed sidewalls (as shown in fig. 4C); when the transistor is a semi-wrap-around vertical transistor of the second type, each transistor pillar 3021 has more sidewalls attached to the insulating strip than one sidewall, while more sidewalls than three are exposed (not shown in fig. 4C), i.e., each transistor pillar 3021 is partially embedded in the insulating strip.

In some embodiments, the etching the transistor bars 302 from the first surface 30-1 of the wafer to form a plurality of transistor pillars 3012 arranged in an array includes:

etching the transistor strips 302 from the first surface 30-1 of the wafer along a second direction to form first grooves 303 between the adjacent insulating strips 301; the first groove 303 divides each transistor bar 302 into a plurality of transistor columns 3021; the plurality of transistor columns 3021 corresponding to the multi-transistor strip 302 form the plurality of transistor columns 3021 arranged in an array.

In practical applications, a dry etching process, such as a plasma etching process or a reactive ion etching process, may be used to etch the wafer.

It should be noted that, referring to fig. 4D, each transistor column 3021 has a first predetermined thickness a in the Z-axis direction, and the first predetermined thickness a is smaller than the initial thickness B of the wafer. The first surface 30-1 of the wafer is any surface of the wafer perpendicular to the Z-axis. The wafer also includes a second surface 30-2 opposite the first surface 30-1. It should be noted that fig. 4B and 4C only show a partial region of the transistor column array, and a part of the wafer under the transistor column that is not etched through is omitted. That is to say, in the embodiment of the present disclosure, the etching of the wafer is a partial etching performed in the thickness direction of the wafer, and the wafer is not etched through in the etching process.

It should be noted that a plurality of transistor arrays 200 may be formed on a wafer, and in the embodiment of the present disclosure, for convenience of illustration, only one transistor array 200 or a local region thereof composed of a limited number of transistors is exemplarily shown.

Fig. 4E is a perspective view of a gate oxide layer formed by a plurality of transistor pillars arranged in an array on a wafer according to an embodiment of the disclosure. FIG. 4F is a cross-sectional view taken at AA' in FIG. 4E. Fig. 4G is a perspective view of a gate oxide layer formed by a plurality of transistor pillars arranged in an array on a wafer according to an embodiment of the disclosure. FIG. 4H is a cross-sectional view taken at AA' in FIG. 4G.

In step S304, a gate layer 214 is formed to half-surround the transistor pillar, mainly on the exposed sidewalls of each transistor 3021 pillar.

In some embodiments, the gate layer comprises: a gate oxide layer and a gate electrode;

and forming the gate electrode covering the gate oxide layer around the gate oxide layer.

In some embodiments, as shown in fig. 4E and 4F, the gate oxide layer 2141 is formed on the exposed sidewall of each of the transistor pillars 3021 to half-surround the transistor pillars; the method comprises the following steps:

the sidewalls of the transistor pillars exposed in the first recess 303 are oxidized by in-situ oxidation to form the gate oxide layer 2141 that semi-surrounds the gate layer of the transistor pillar 3021.

In some embodiments, as shown in fig. 4G and 4H, forming the gate electrode 2142 around the gate oxide layer 2141 to cover the gate oxide layer 2141 includes:

a conductive material is deposited in the first recess 303 to form the gate electrode 2142 covering the gate oxide layer 2041.

It should be noted that, in the embodiment of the present disclosure, the gate oxide layer 2141 and the gate electrode 2142 are formed to half-surround the transistor pillar 3021. Half-wrap here it will be appreciated that since transistor post 3021 has sidewalls attached to the insulating strip that do not form gate oxide 2141 and the gate electrode 2142, gate oxide 2141 and the gate electrode 2142 are formed only on the exposed sidewalls of transistor post 3021.

In practice, the exposed sidewall of the transistor 3031 may be oxidized in situ by heating or pressing to form the gate oxide layer 2142. In some embodiments, a gate oxide layer may also be deposited to cover the exposed sidewalls of the transistor pillar 3031. Note that the gate oxide layer 2142 formed by deposition covers not only the exposed sidewalls of the transistor pillar 3031, but also the remaining regions in the first recess, and the gate oxide layer in the remaining regions can be selectively removed.

In practical applications, the gate electrode may be formed by depositing a conductive material in the etched groove by a Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), or Atomic Layer Deposition (ALD).

Illustratively, the conductive material may include polysilicon, a conductive metal, a conductive alloy, or the like. The conductive metal may include metallic tungsten or metallic copper, etc.

In practical application, as shown in fig. 4H, the formed initial gate oxide layer and the conductive material are partially etched along the Z-axis direction to form a recess, where the remaining initial gate oxide layer is a gate oxide layer 2141, and the remaining conductive material is a gate 2142.

In practical application, the etching process may adopt a dry etching technique.

Fig. 4I is a perspective view of a plurality of transistor pillars arranged in an array on a wafer to form a source according to an embodiment of the disclosure. FIG. 4J is a cross-sectional view taken at AA' in FIG. 4I.

Next, step S305 is executed. Here, the first end of the transistor column 3021 is one end of the transistor column in the Z-axis direction. Source 212 is formed by ion implantation into a first end of the transistor column.

In some embodiments, referring to fig. 4I and 4J, forming the source 212 of the transistor at the first end of each of the transistor pillars 3021 includes:

a first end of each of the transistor columns 3021 adjacent to the first surface 30-1 of the wafer is ion implanted to form a source 212 of each of the transistors.

In some embodiments, before performing step S306, the method for manufacturing a transistor array further includes:

and thinning the wafer from the second surface of the wafer until the second end of the transistor column is exposed.

As shown in fig. 4K, the wafer is inverted such that the first surface 30-2 of the wafer faces upward.

In some embodiments, the first surface of the wafer needs to be fixed on a supporting structure before the second surface 30-2 of the wafer is thinned, so as to prevent the structure of the transistor from being damaged when the second surface 30-2 of the wafer is thinned.

Fig. 4L is a schematic structural diagram of the transistor after thinning the second surface of the wafer according to the embodiment of the disclosure, and as shown in fig. 4I, the second surface 30-2 of the wafer is thinned, and the second end of the transistor column is exposed.

Fig. 4M is a perspective view of a plurality of transistor pillars arranged in an array on a wafer to form a drain according to an embodiment of the disclosure. Fig. 4N is a cross-sectional view corresponding to fig. 4M.

Next, referring to fig. 4M, 4N, step S307 is executed. Specifically, the drain electrode 213 is formed by ion implantation into the second end of the transistor column.

In some embodiments, said forming a drain 213 of said transistor at a second end of each of said transistor columns comprises:

thinning the wafer from the second surface 30-2 of the wafer and along a second direction to expose a second end of the transistor column away from the first surface of the wafer; wherein the second surface is opposite the first surface;

It should be noted that the positions of the source 212 and the drain may be interchanged, and the source 212 may be formed first or the drain may be formed first.

Note that after the wafer inversion, the gate oxide 2141 and the gate electrode 2142 may be etched back to form the gate oxide 2141 and the gate electrode 2142 that only half-surrounds the middle portion (channel region) of the transistor pillar as shown in fig. 4M and 4N. In some embodiments, before step 304 is performed, or after in-situ oxidation is performed, the first recess 303 may be filled with an insulating material, and then etched back to form a remaining thickness of the insulating material, and then a gate oxide layer 2141 and the gate electrode 2142 may be formed on the remaining thickness of the insulating layer. In the embodiment of the present disclosure, after the source electrode 212 and the drain electrode are formed, the transistor column between the source electrode 212 and the drain electrode constitutes the channel region 211 of the pillar-shaped transistor 210.

The pillar-shaped transistor 210 formed by the manufacturing method provided by the embodiment of the present disclosure has the source electrode 212 and the drain electrode respectively located at the first end and the second end of the channel region 211 in the second direction, and the second direction is the thickness direction of the wafer forming the channel region 211, so that the area of the transistor is greatly reduced.

In some embodiments, when the pillar transistor 210 provided by the embodiment of the present disclosure is applied to a memory, since the drain and the source 212 of the pillar transistor 210 are located on different surfaces of a wafer, different structures to which the source 212 and the drain in the memory are connected can be respectively designed in the two surfaces of the wafer, thereby simplifying a circuit layout inside the memory and reducing the process difficulty of manufacturing the memory.

In some embodiments, a cross-sectional shape of each of the transistors parallel to the predetermined plane includes any one of:

squareness;

an ellipse;

a semicircle;

any polygon;

wherein the predetermined plane is parallel to the first direction.

That is, the cross-sectional shape of the channel region, the source electrode, and the drain electrode of the transistor parallel to the predetermined plane is not limited and includes any one of: square, oval, semi-circle, arbitrary polygon.

In some embodiments, each of the transistor pillars is located on one side of the insulating strip;

alternatively, the first and second electrodes may be,

each of the transistor columns is partially embedded in the insulating strip.

Here, each of the transistor columns located at one side of the insulating strip may be understood as a first type of semi-surrounding vertical transistor, and each of the transistor columns partially embedded in the insulating strip may be understood as a second type of semi-surrounding vertical transistor.

Fig. 5A to 5D are schematic structural diagrams of horizontal cross sections (i.e., cross sections parallel to the predetermined plane) at channels of several transistors according to an embodiment of the present disclosure. Wherein, fig. 5A shows a cross-sectional view of a half-wound vertical transistor of a first type having a rectangular horizontal cross-sectional shape; FIG. 5B is a cross-sectional view of a half-wrapped vertical transistor of a first type having a horizontal cross-sectional shape that is semi-circular; FIG. 5C is a cross-sectional view of a second type of half-wrapped vertical transistor having a square horizontal cross-sectional shape; fig. 5D shows a cross-sectional view of a second type of half-wrapped vertical transistor having an elliptical horizontal cross-sectional shape.

In some embodiments, the transistor is cylindrical in shape; the first end and the second end are substantially the same in size in the first direction, and the first end and the second end are substantially the same in size in a third direction; the third direction is parallel to the surface of the wafer and is vertical to the first direction;

alternatively, the first and second electrodes may be,

Here, the cylindrical shape may also be understood as an I-shape, i.e. the dimensions of the first end and the second end in the first direction and the third direction are substantially the same; the L-shape, i.e. the first end and the second end differ in size in at least one of the first direction and the third direction.

Fig. 6A to 6D are schematic perspective views of several single transistors provided in the embodiments of the present disclosure.

Fig. 6A is a perspective view of a pillar-shaped half-surrounded vertical transistor of a first type; FIG. 6B is a perspective view of a pillar-shaped half-wrapped vertical transistor of a first type; FIG. 6C is a perspective view of a second type of L-shaped half-wrapped vertical transistor; fig. 6D shows a perspective view of a second type of L-shaped half-wrapped vertical transistor.

It should be noted that, in the embodiment of the present disclosure, in order to simplify the manufacturing process of the transistor array, for example, to reduce the filling of the insulating substance, the insulating strip is formed by connecting the insulating portions in the individual transistors, and it is understood that, in practical applications, the insulating strip 215 in the transistor array in fig. 4O may also be cut into a plurality of insulating pillars corresponding to each transistor.

Fig. 2B is a schematic structural diagram of an L-shaped transistor 20 according to an embodiment of the disclosure. Referring to fig. 2B, the L-shaped transistor 220 includes:

a channel region 221;

a source 222 located at a first end of the channel region 221;

a drain 223 located at a second end of the channel region 221, where the first end and the second end are two opposite ends of the channel region 221 in a second direction, and the second direction is perpendicular to a surface of a wafer for forming the transistor array;

a gate layer 224 half-surrounding the channel region 221;

the insulating strip 225 extends along a first direction, and is attached to a column of transistors in the transistor array, and the first direction is parallel to a column arrangement direction of the transistor array.

It will be appreciated that the active region of the L-shaped transistor 220 forms an L-shaped structure, i.e., the source, drain and channel regions of the L-shaped transistor 220 together form an L-shaped structure.

It should be noted that the lengths of the first sidewall and the second sidewall of the L-shaped transistor 220 in the second direction are equal to the first predetermined thickness.

As can be seen from fig. 2B, the transistor columns of the L-shaped transistor are in the ZOX plane and in the zy plane, and the dual source 222, the channel region 221, and the drain 223 of the L-shaped transistor all form an L-shaped structure.

In the embodiment of the present disclosure, the source 222 and the drain 223 are respectively located at two opposite ends in the thickness direction of the wafer on which the channel region 221 is formed, that is, the source 222 and the drain 223 of the L-shaped transistor provided in the embodiment of the present disclosure are located in two opposite faces of the wafer, so that the area of the transistor is greatly reduced.

Next, referring to fig. 7A to 7F, a method for manufacturing an L-shaped transistor according to an embodiment of the present disclosure will be described in detail.

First, step S301 is executed to provide a wafer.

Next, step S302 is performed, and it should be noted that, compared to the method for manufacturing the pillar-shaped transistor 210, in step S302 of the method for manufacturing the L-shaped transistor, when the wafer is etched to obtain the groove extending along the Y-axis direction, the groove is not like a regular long strip, but there are some recesses on the basis of the regular long strip, and these recesses are used for accommodating the embedded portion of the transistor pillar. In practical applications, such a recessed groove can be obtained by pattern transfer of a correspondingly shaped mask.

Fig. 7A is a perspective view of another multiple transistor columns arranged in an array according to an embodiment of the disclosure, and fig. 7B is a cross-sectional view taken along AA' in fig. 7A.

It should be noted that the manufacturing method of the pillar-shaped transistor 210 is similar to the forming method of the step S303 in the manufacturing method of the L-shaped transistor, and as can be seen from fig. 7A to 7B, in the step S303, the transistor bar 302 is partially etched along the Z-axis direction with the first surface 30-1 of the wafer as the etching starting point, so as to form a plurality of transistor pillars 3021 arranged in an array. Each transistor pillar 3021 has a sidewall attached to the insulating strip and an exposed sidewall.

It is understood that, taking the horizontal cross section of the transistor as a square as an example, when the transistor is a first type semi-surrounding vertical transistor, each transistor pillar 3021 has one sidewall attached to the insulating strip and three exposed sidewalls (as shown in fig. 4C); when the transistor is a semi-wrap-around vertical transistor of the second type, each transistor pillar 3021 has more sidewalls than one sidewall attached to the insulating strip and more sidewalls than three sidewalls exposed (as shown in fig. 7A), i.e., each transistor pillar 3021 is partially embedded in the insulating strip.

Note that, as shown in fig. 7B, in the method of manufacturing the L-shaped transistor, the depth of the first groove is smaller than the thickness of the insulating stripe 225.

Fig. 7C is a cross-sectional view of a plurality of transistor pillars arranged in an array on a wafer to form a source, according to an embodiment of the disclosure.

Note that the manufacturing method of the pillar-shaped transistor 210 is similar to the forming method of steps S304 and S305 in the manufacturing method of the L-shaped transistor. As seen in fig. 7C, in step S304, a gate oxide layer and a gate are sequentially formed on the sidewall of each transistor pillar. Specifically, S305 may include: forming an initial gate oxide layer on the exposed sidewall of each transistor column by in-situ oxidation; depositing a conductive material in the first groove 303 with the initial gate oxide layer to form a conductive layer; and in the second direction, etching treatment is carried out on the initial gate oxide layer and the conducting layer, and the initial gate oxide layer and the conducting layer with partial thickness in the second direction are removed to form a gate oxide layer 2241 and a gate electrode 2242.

In step S305, specifically, in the second direction, the source 222 may be formed by performing ion implantation on the first end of the transistor column.

the wafer is thinned from the second surface of the wafer until the second end of the transistor column and the insulating layer 301 are exposed.

As shown in fig. 7D, the wafer is inverted such that the first surface 30-2 of the wafer faces upward.

Fig. 7E is a perspective view of a plurality of transistor pillars forming drains arranged in an array on a wafer according to an embodiment of the disclosure. Fig. 7F is a cross-sectional view corresponding to fig. 7E.

Next, referring to fig. 7E and 7F, step S307 is executed. Specifically, the drain electrode 223 is formed by ion implantation into the second end of the transistor column.

In the embodiment of the present disclosure, the finally formed transistor is an L-shaped transistor as a whole, that is, the source 222, the drain and the channel region 221 of the L-shaped transistor collectively form an L-shaped structure.

An embodiment of the present disclosure provides a semiconductor device, fig. 8A is an optional schematic diagram of the semiconductor device provided in the embodiment of the present disclosure, and fig. 8B is a schematic diagram of a partial structure of the semiconductor device provided in the embodiment of the present disclosure. As shown in conjunction with figures 8A and 8B,

the semiconductor device 40 includes: at least one memory array and a plurality of bit lines 403 arranged in parallel along a third direction.

In practice, the gates 2141 connected together per column are used as word lines.

Each memory array includes: a plurality of memory cells arranged in an array; the memory cell includes at least one transistor provided by embodiments of the present disclosure.

In some embodiments, the transistors in the semiconductor device include pillar transistors 210. In some embodiments, the transistors in the semiconductor device may include an L-shaped transistor 220.

It is to be understood that whether the transistor in the semiconductor device is the pillar transistor 210 or the L-shaped transistor 220, the manner of connection of the transistor in the semiconductor device may be the same.

Specifically, the gates of the plurality of transistors arranged in parallel in the first direction may be conductive structures connected to each other, and thus, the gates of the plurality of transistors arranged in parallel in the first direction may serve as a word line for receiving a word line voltage and controlling the transistors to be turned on or off by the word line voltage. Each bit line is connected to the sources or drains of a plurality of transistors arranged in parallel in the third direction. The bit line is used to perform a read or write operation on the memory cell when the transistor is turned on.

It is noted that in some embodiments, the semiconductor device may further include a wiring 402 electrically connected to the gates of the plurality of transistors arranged in parallel in the first direction for receiving the word line voltage and transmitting the received word line voltage to the gate of the transistor electrically connected to the wiring 402.

In some embodiments, when the source of the transistor is connected to bit line 403, the drain of the transistor is grounded; when the drain of the transistor is connected to the bit line, the source of the transistor is grounded.

The semiconductor device provided by the embodiment of the disclosure includes various types of memories. For example, NAND Flash (Flash), Nor Flash, DRAM, Static Random Access Memory (SRAM), and Phase-Change Memory (PCM).

In some embodiments, when the semiconductor device is a DRAM, the memory cell further includes: a storage capacitor.

As shown in fig. 8C, which is an alternative structural diagram of a DRAM memory cell according to an embodiment of the present disclosure, it can be seen that in a DRAM memory array, one end of a storage capacitor 404 is connected to the drain or the source of the pillar transistor 210, and the other end of the storage capacitor 404 is used for receiving an external electrical signal.

It should be noted that the external electrical signal received by the other end of the storage capacitor 404 may include: a ground voltage signal, a test voltage signal, or a control voltage signal, etc. Typically, the test voltage signal and the control voltage signal take on values other than zero.

When the transistor includes an L-shaped transistor, one end of the storage capacitor 404 is connected to the drain or source of the L-shaped transistor 220, and the other end of the storage capacitor 404 is used to receive an external electrical signal.

The storage capacitor 404 is used to store data written to the memory cell. In some embodiments, when the semiconductor device is a PCM, the memory cell further includes: and (4) an adjustable resistor.

Referring to fig. 8D, which is an alternative structural diagram of the PCM memory array according to the embodiment of the present disclosure, it can be seen that in the PCM memory array, the adjustable resistor 405 is connected between the bit line 403 and the source 212 of the pillar shaped transistor 210, or the adjustable resistor 405 is connected between the bit line 403 and the drain 213 of the pillar shaped transistor 210.

When the transistor comprises an L-shaped transistor, the adjustable resistance 405 is connected between the bit line 403 and the source 222 of the L-shaped transistor 220, or the adjustable resistance 405 is connected between the bit line 403 and the drain 223 of the L-shaped transistor 220.

The adjustable resistance 405 is used to adjust the state of the data stored in the memory cell via the bit line voltage provided by the bit line. In some embodiments, when the semiconductor device includes a plurality of memory arrays, the semiconductor device is NAND Flash or Nor Flash. When the plurality of memory arrays are connected in parallel, the semiconductor device is Nor Flash; when a plurality of memory arrays are connected in series, the semiconductor device is NAND Flash.

In some embodiments, when the semiconductor device is a FRAM, the memory cell further comprises: a ferroelectric capacitor;

the ferroelectric capacitor comprises an upper electrode, a lower electrode and a ferroelectric material layer positioned between the upper electrode and the lower electrode; the upper electrode of the ferroelectric capacitor is connected with the drain electrode of the transistor, the lower electrode of the ferroelectric capacitor is connected with the source electrode of the transistor, and the ferroelectric capacitor is used for storing data written into the memory array. The polarity of the ferroelectric material in the ferroelectric material layer is changed by controlling the voltage difference between the upper and lower electrodes of the ferroelectric capacitor, and thus data is stored.

In the embodiments of the present disclosure, some common semiconductor devices are merely exemplified, the scope of the present disclosure is not limited thereto, and any semiconductor device including the pillar-shaped transistor 210 and/or the L-shaped transistor 220 provided by the embodiments of the present disclosure falls within the scope of the present disclosure.

In the embodiment of the disclosure, the transistor structure of the semiconductor device is designed to be a novel structure with a vertical channel, so that the area of the memory array is reduced, and the storage density of the memory array is improved. Meanwhile, in the transistor in the embodiment of the present disclosure, the source and the drain are located at the upper and lower ends of the vertical channel region, so that in the formation process of the semiconductor device, the bit lines or other structures may be respectively disposed on the vertical two sides of the channel region.

For example, for a DRAM, bit lines and capacitors of a DRAM memory array may be disposed on two sides of the same wafer, respectively, so that circuit arrangements of word lines, bit lines, and capacitors may be simplified, and difficulty in manufacturing a semiconductor device may be reduced.

Fig. 9 is a flowchart of a method for forming a semiconductor device according to an embodiment of the present disclosure, where the method includes the following steps:

step S501, forming at least one memory array, wherein the memory array at least comprises: an array of transistors; the transistor array comprises a plurality of transistors which are arranged in an array; the transistor includes: a dual gate, source and drain; the transistor array is manufactured by adopting the method provided by the embodiment of the disclosure;

step S502, forming a plurality of bit lines which are arranged in parallel along a third direction; each bit line is connected with the source electrode or the drain electrode of the transistors which are arranged in parallel along the third direction, and the bit lines are used for executing reading or writing operation on the memory array when the transistors are conducted.

Here, the gate electrodes of a plurality of divided transistor columns of each transistor stripe are connected to each other, and the gate electrodes connected to each other are used as word lines of the same column of transistors corresponding to the plurality of transistor columns; the plurality of word lines are arranged in parallel along a first direction; the first direction and the third direction are intersected, and a plane where the first direction and the third direction are located is perpendicular to the first direction.

Illustratively, the memory array includes: a plurality of memory cells arranged in an array; the memory cell includes at least one transistor provided by embodiments of the present disclosure. It is emphasized that the memory array includes the transistor array provided by the embodiments of the present disclosure.

In the semiconductor device formed by the embodiment of the disclosure, the source electrode position and the drain electrode position of the transistor can be interchanged, and the source electrode and the drain electrode can be respectively processed on two surfaces of the same wafer, so that the patterns of the source electrode and the drain electrode can be different.

In the embodiments of the present disclosure, the bit lines are implemented by forming conductive lines at preset bit line positions. The constituent materials of the conductive line include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof.

In the embodiment of the disclosure, the transistor structure of the semiconductor device is designed to be a novel transistor structure with a vertical channel, so that the area of the memory array is reduced, and the storage density of the memory array is improved.

Meanwhile, in the transistor in the embodiment of the present disclosure, the source and the drain are located at the upper and lower ends of the vertical channel region, so that in the formation process of the semiconductor device, in combination with the wafer bonding and the back silicon thinning technology, the bit lines or other structures may be respectively disposed in two opposite surfaces of the wafer. For example, for a DRAM, bit lines and capacitors of a DRAM memory array may be disposed on two sides of the same wafer, respectively, so that circuit arrangements of word lines, bit lines, and capacitors may be simplified, and difficulty in manufacturing a semiconductor device may be reduced.

In the several embodiments provided in the present disclosure, it should be understood that the disclosed apparatus and method may be implemented in a non-target manner. The above-described device embodiments are merely illustrative, for example, the division of a unit is only one logical function division, and there may be other division ways in actual implementation, such as: multiple units or components may be combined, or may be integrated into another system, or some features may be omitted, or not implemented. Additionally, the various components shown or discussed are coupled or directly coupled to each other.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed on a plurality of network units; some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

The features disclosed in the several method or apparatus embodiments provided in this disclosure may be combined in any combination to arrive at a new method or apparatus embodiment without conflict.

The above description is only for the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present disclosure, and all the changes or substitutions should be covered within the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A method of fabricating a transistor array, the method comprising:

providing a wafer;

2. The method of claim 1, wherein etching the transistor strips from the first surface of the wafer to form a plurality of transistor columns arranged in an array comprises:

3. The method of claim 2, wherein the gate layer comprises: a gate oxide layer and a gate electrode;

4. The method of claim 3, wherein said forming said gate oxide layer semi-surrounding each of said transistor pillars at exposed sidewalls of said transistor pillars; the method comprises the following steps:

5. The method of claim 3, wherein forming the gate electrode overlying the gate oxide layer around the gate oxide layer comprises:

depositing a conductive material in the first groove to form the gate electrode covering the gate oxide layer; the gate electrodes of a plurality of divided transistor columns of each transistor strip are connected with each other, and the connected gate electrodes are used as word lines of the same column of transistors corresponding to the transistor columns.

6. The method of claim 1, wherein said forming a source of said transistor at a first end of each of said transistor columns comprises:

7. The method of claim 1, wherein said forming a drain of said transistor at a second end of each of said transistor columns comprises:

8. The method of claim 1,

each transistor column is positioned on one side of the insulating strip;

alternatively, the first and second electrodes may be,

each of the transistor columns is partially embedded in the insulating strip.

9. The method of claim 1, wherein a cross-sectional shape of each of the transistors parallel to a predetermined plane comprises any one of:

squareness;

an ellipse;

a semicircle;

any polygon;

wherein the predetermined plane is parallel to the first direction.

10. The method of claim 1,

the transistor is cylindrical in shape; the first end and the second end are substantially the same in size in the first direction, and the first end and the second end are substantially the same in size in a third direction; the third direction is parallel to the surface of the wafer and is vertical to the first direction;

alternatively, the first and second electrodes may be,

11. A transistor array, comprising: a plurality of transistors and a plurality of insulating strips arranged in an array;

the transistor includes:

a channel region;

a source electrode positioned at a first end of the channel region;

a gate layer semi-surrounding the channel region;

12. A method of forming a semiconductor device, the method comprising:

forming at least one memory array; wherein each of the memory arrays comprises at least: a transistor array comprising a plurality of transistors arranged in an array; the transistor includes: a gate, a source and a drain; the transistor array is manufactured by a method as provided in any one of claims 1 to 10;

13. A semiconductor device, comprising:

at least one memory array is provided with a plurality of bit lines which are arranged in parallel along a third direction;

each of the memory arrays comprises: the transistor array of claim 11; the transistor includes at least: a gate, a source and a drain; the third direction is intersected with the first direction, and a plane where the third direction and the first direction are located is perpendicular to the first direction;

the grid electrodes of the transistors are arranged in parallel along the first direction and are used for receiving word line voltage and controlling the transistors to be switched on or switched off through the word line voltage;

14. The semiconductor device of claim 13, wherein the memory array further comprises: a plurality of capacitors;

one end of the capacitor is connected with the drain electrode or the source electrode of the transistor, the other end of the capacitor is used for receiving an external electric signal, and the capacitor is used for storing data written into the memory array.

15. The semiconductor device of claim 13, wherein the memory array further comprises: a plurality of resistors;

16. The semiconductor device of claim 13, wherein the memory array further comprises: a ferroelectric capacitor;

the ferroelectric capacitor includes: the ferroelectric material layer is positioned between the upper electrode and the lower electrode; the upper electrode of the ferroelectric capacitor is connected with the drain electrode of the transistor, the lower electrode of the ferroelectric capacitor is connected with the source electrode of the transistor, and the ferroelectric capacitor is used for storing data written into the memory array.