KR20160142803A - Vertical channel transistors and methods for fabricating vertical channel transistors - Google Patents

Abstract

The present invention provides a vertical channel transistor and a method for fabricating the vertical channel transistor. The method includes: forming an active on a substrate; forming multiple vertical channels on the active; forming multiple gate electrodes separated from one another to cover a sidewall of multiple vertical channels; forming an embedded bit line extended along the active between multiple vertical channels; and forming a plug-in among the multiple vertical channels so as to form a word line connected to the multiple gate electrodes by the plug-in. The vertical channel transistor has an excellent electric effect and can secure reproducibility of a channel length in simple processes.

Description

TECHNICAL FIELD [0001] The present invention relates to a vertical channel transistor and a method of manufacturing the same. BACKGROUND ART < RTI ID = 0.0 >

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductors, and more particularly, to a vertical channel transistor and a method of manufacturing the same.

In the semiconductor industry, transistors, bit lines, and the like are formed by various manufacturing techniques. One of such fabrication techniques is to form a MOS field effect transistor having a horizontal channel. 2. Description of the Related Art As the design rule of a semiconductor device is reduced, a manufacturing technique is being developed in a direction of improving the degree of integration of a semiconductor device and improving an operation speed and a yield. A transistor having a vertical channel has been proposed in order to enlarge the integration degree, resistance, current driving ability, and the like of a transistor having a conventional horizontal channel.

It is an object of the present invention to provide a vertical channel transistor having excellent electrical characteristics and a method of manufacturing the same.

A method of manufacturing a channel transistor according to an exemplary embodiment of the present invention includes patterning a substrate to form an active region and patterning the active region to form a plurality of vertical channels protruding in a vertical direction from the substrate, Forming a conductor that exposes an upper portion of the vertical channel, forming a gate spacer over the plurality of vertical channels, and patterning the conductor by etching with the gate spacer as a mask to surround the side walls of the plurality of vertical channels Forming a plurality of gate electrodes in a self-aligned manner, forming a buried bit line extending in a first horizontal direction on the substrate under the plurality of vertical channels, and forming a buried bit line in the first horizontal direction And a plurality of gate electrodes extending in a second horizontal direction perpendicular to the plurality of gate electrodes, It may include forming an in-gyeolhaneun multiple plug.

According to the present invention, since the vertical channel is protruded in a direction perpendicular to the surface of the substrate, an enlarged channel length can be ensured, a short channel effect can be prevented, and the degree of integration can be improved since the vertical channel is arranged in a zigzag form . The gate electrode may have a shape that surrounds the vertical channel along the outer peripheral surface of the vertical channel, so that the current driving capability can be improved. The width of the gate electrode can be formed to have a desired dimension accurately, and the reproducibility of the channel length can be ensured. In addition, it is possible to solve the bridging problem between the gate electrodes (word lines), and the gate electrode can be formed in a self-aligning manner, so that the photo process can be omitted.

1 is a perspective view illustrating a vertical channel transistor according to a first embodiment of the present invention.
2 is a perspective view illustrating a semiconductor device using a vertical channel transistor according to a first embodiment of the present invention.
3 is a perspective view illustrating a vertical channel transistor according to a second embodiment of the present invention.
4 is a perspective view illustrating a vertical channel transistor according to a third embodiment of the present invention.
5 is a perspective view illustrating a vertical channel transistor according to a fourth embodiment of the present invention.
6 is a perspective view illustrating a vertical channel transistor according to a fifth embodiment of the present invention.
7 is a perspective view illustrating a vertical channel transistor according to a sixth embodiment of the present invention.
FIGS. 8A to 17A are plan views illustrating a method of manufacturing a vertical channel transistor according to a first embodiment of the present invention, and FIGS. 8B to 17B are cross-sectional views taken along lines I-I 'of FIGS.
FIGS. 18A, 19A, and 19B are plan views illustrating a method for fabricating a semiconductor device employing a vertical channel transistor according to a first embodiment of the present invention, and FIG. 18B is a cross-sectional view taken along line I-I 'of FIG.
FIGS. 20A to 24A are plan views illustrating a method of manufacturing a vertical channel transistor according to a second embodiment of the present invention, and FIGS. 20B to 24B are cross-sectional views taken along line II-II 'of FIGS.
FIGS. 25A to 27A are plan views illustrating a method of manufacturing a vertical channel transistor according to a third embodiment of the present invention, and FIGS. 25B to 27B are cross-sectional views taken along line III-III 'of FIGS.
FIGS. 28A to 30A are plan views illustrating a method of manufacturing a vertical channel transistor according to a fourth embodiment of the present invention, and FIGS. 28B to 30B are cross-sectional views taken along lines IV-IV 'of FIGS.
FIGS. 31A to 36A are plan views illustrating a method of manufacturing a vertical channel transistor according to a fifth embodiment of the present invention, and FIGS. 31B to 36B are cross-sectional views taken on line V-V 'of FIGS.
FIGS. 37A to 40A are plan views illustrating a method of manufacturing a vertical channel transistor according to a sixth embodiment of the present invention, and FIGS. 37B to 40B are cross-sectional views taken on lines VI-VI 'of FIGS.
41A and 41B are plan views showing pitch differences of buried bit lines in a vertical channel transistor according to a general technology and an embodiment of the present invention.
42A and 42B are block diagrams illustrating an application of a vertical channel transistor according to an embodiment of the present invention.

Hereinafter, a method of manufacturing a vertical channel transistor according to the present invention will be described in detail with reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages of the present invention and its advantages over the prior art will become apparent from the detailed description and claims that follow. In particular, the invention is well pointed out and distinctly claimed in the claims. The invention, however, may best be understood by reference to the following detailed description when taken in conjunction with the accompanying drawings. Like reference numerals in the drawings denote like elements throughout the various views.

(Apparatus Example 1)

1 is a perspective view illustrating a vertical channel transistor according to a first embodiment of the present invention.

1, the vertical channel transistor 1 of the first embodiment includes a plurality of active elements 110 formed on a semiconductor substrate 100, a plurality of vertical channels 115 protruded from the active element 110, A plurality of word lines 190 including a plurality of word line plug-ins 180 connecting a plurality of gate electrodes 165 formed on sidewalls of the vertical channels 115, a plurality of word lines 190, And may include a plurality of buried bit lines 170 extending in a substantially orthogonal direction. The vertical channel transistor 1 has a gate insulating film 150 surrounding the vertical channel 115 between the vertical channel 115 and the gate electrode 165 and a gate insulating film 150 between upper and lower junction regions .

The active 110 extends in the Y direction and a plurality of vertical channels 115 are arranged in the Y direction on one active 110 and arranged in a staggered manner. Vertical channels 115 may protrude in the Z direction from the edge of active 110. The X, Y, and Z directions may intersect, for example, 90 degrees. The buried bit line 170 may be formed by an impurity doping or silicide reaction to the active 110 adjacent the bottom of the vertical channel 115. Thus, the buried bit line 170 may have the same shape as the active 110, e.g., extending in the Y direction. The buried bit line 170 may overlap with the vertical channels 115 arranged in the Y direction.

According to this embodiment, the vertical channel 115 protrudes in the Z direction perpendicular to the surface of the substrate 100, so that an enlarged channel length can be secured, thereby preventing a short channel effect. The gate electrode 165 may be formed to surround the vertical channel 115 along the outer circumferential surface of the vertical channel 115 so that the current driving capability can be improved. The gate electrode 165 can be formed so as to have a desired dimension accurately in its width (length in the Z direction), thereby ensuring the reproducibility of the channel length. Since the vertical channels 115 are arranged in a zigzag shape, the degree of integration can be improved and the bridging problem between the gate electrodes 165 and / or the word lines 190 can be solved. The gate electrode 165 may be formed in a self-aligning manner, so that the photolithography process can be omitted. These features will be understood with reference to the method of manufacturing the vertical channel transistor 1 of this embodiment described later with reference to Figs. 8A / B to 17A / B. However, it is needless to say that the method of implementing the vertical channel transistor 1 of the present embodiment is not limited to the manufacturing method described in Figs. 8A / B to 17A / B, and various modifications are possible.

(Example of semiconductor device)

2 is a perspective view illustrating a semiconductor device using a vertical channel transistor according to a first embodiment of the present invention.

Referring to FIG. 2, a capacitor 90 is connected to the vertical channel transistor 1, so that a semiconductor device 1a such as a DRAM can be realized. The capacitor 90 may be electrically connected to the vertical channel 115. A contact plug 80 may further be included between the capacitor 90 and the vertical channel 115. The vertical channel transistor 1 can be utilized for a non-memory such as a central processing unit (CPU) as well as the above-mentioned memory.

(Apparatus Embodiment 2)

3 is a perspective view illustrating a vertical channel transistor according to a second embodiment of the present invention.

3, the vertical channel transistor 2 of the second embodiment is formed by connecting an active 210, a vertical channel 215, a gate insulating film 250, and a gate electrode 265 on a semiconductor substrate 400 The word line 290 including the word line plug-in 280 may be configured similarly to the vertical channel transistor 1 of the first embodiment. Characteristics such as current drive capability, gate length reproducibility, wordline bridge, etc. will be understood with reference to the method of manufacturing the vertical channel transistor 2 of this embodiment described later with reference to Figs. 20a / b to 24a / b.

Unlike the vertical channel transistor 1 of the first embodiment, the buried bit line 270 may be formed of a conductor that occupies the top edge of the active 210 in a zigzag fashion. Thus, the buried bit line 270 may extend in the Y direction in a form different from the active 210, e.g., a zigzag form. The buried bit line 270 may be offset with the vertical channels 215 arranged in zigzag in the Y direction.

(Apparatus Embodiment 3)

4 is a perspective view illustrating a vertical channel transistor according to a third embodiment of the present invention.

4, the vertical channel transistor 3 of the third embodiment includes a word line plug-in 380 connecting the active 310, the gate insulating film 350, and the gate electrode 365 on the semiconductor substrate 300 ) And the buried bit line 370 may be configured to be similar to the vertical channel transistor 1 of the first embodiment. Unlike the vertical channel transistor 1 of the first embodiment, the vertical channels 315 may be arranged in a straight line in the Y direction along the edge of the active 210. The vertical channel transistor 3 of the present embodiment can be implemented by the manufacturing method described in Figs. 25A / B to 27A / B or a similar method.

(Apparatus Embodiment 4)

5 is a perspective view illustrating a vertical channel transistor according to a fourth embodiment of the present invention.

5, the vertical channel transistor 4 of the fourth embodiment is different from the vertical channel transistor 3 of the third embodiment in that the vertical channels 415 are arranged in a straight line in the Y direction along the center of the active 310 Lt; / RTI > Other than this, the vertical channel transistor 3 of the third embodiment can be similarly configured. The implementation of the vertical channel transistor 4 of this embodiment will be understood with reference to the fabrication method described in Figs. 28a / b-30a / b.

(Apparatus Example 5)

6 is a perspective view illustrating a vertical channel transistor according to a fifth embodiment of the present invention.

6, the vertical channel transistor 5 of the fifth embodiment includes a plurality of first active portions 511 extending in the A direction and a plurality of second active portions 512 extending in the B direction on the semiconductor substrate 500 (Hereinafter referred to as a honeycomb pattern) crossing almost 90 degrees and having the same pattern as rhombus or honeycomb. The A and B directions may intersect the X direction at an angle of less than 90 degrees. For example, the angle? 1 formed by the direction A with respect to the X direction and the angle? 1 formed by the direction B and the direction X may be approximately 45 degrees.

A plurality of vertical channels 515 projecting vertically in the Z direction are disposed on the active 510. Vertical channels 515 may occupy the intersection of first active 511 and second active 512. Thus, the vertical channels 515 may appear to be arranged in a staggered fashion on the semiconductor substrate 500. The shape of the active 510 and the location of the vertical channels 515 will be more clearly understood with reference to Figures 31A and 32A.

Word lines 590 extend in the X direction, and buried bit lines 570 extend in the Y direction. The word line 590 may include gate electrodes 565 surrounding the vertical channels 515 and word line plug-ins 580 connecting the gate electrodes 565. The buried bit line 570 may be formed of a conductor that occupies the upper end of the active 510. One buried bit line 570 may be electrically connected to two sets of vertical channels 515 arranged in the Y direction. The vertical channel transistor 5 of the present embodiment can be implemented by the manufacturing method described in Figs. 31A / B to 36A / B or a similar method.

According to the present embodiment, the widths of the buried bit lines 570 can be further enlarged by arranging the vertical channels 515 in a honeycomb pattern rather than a general square pattern, so that the buried bit lines 570 ) Can be reduced. This will be described in more detail with reference to FIGS. 41A and 41B.

41A and 41B are plan views showing pitch differences of buried bit lines in a vertical channel transistor according to a general technology and an embodiment of the present invention.

41A, when the size of each of the vertical channels 15 forming the square pattern is 1.0 F (for example, 50 nm) and the pitch is 2.7 F (for example, 135 nm), the width and pitch of the word line 19 (E.g., 67.5 nm) and the width and pitch of the buried bit line 17 can be designed to be 1.35F, respectively. The active may be in the form of a line which extends in the same pattern as the buried bit line 17, for example the longitudinal direction of the buried bit line 17, and which overlaps or is offset from the buried bit line 17. [ According to this example, there is a limitation that the width of the buried bit line 17 can be increased, so that there is an issue that the resistance of the buried bit line 17 increases as the degree of integration increases.

41B, if the width of the active 510 forming the honeycomb pattern is designed to be 1.35F and the size and pitch of the vertical channel 515 are designed to be 1.0F and 2.7F, respectively, Pitch and spacing can be formed to be 1.3 F, 1.9 F, and 0.6 F, respectively, and the buried bit line 570 can be formed to have a width, a pitch, and a perforation of 2.9 F, 3.8 F, and 0.9 F, respectively have. 41A, if the active 510 is formed into a honeycomb pattern, even if the vertical channel 515 of the honeycomb pattern and the vertical channel 15 of the square pattern are the same in size and pitch, Can be increased from 1.35F to 2.9F, allowing a lower resistance.

(Apparatus Example 6)

7 is a perspective view illustrating a vertical channel transistor according to a sixth embodiment of the present invention.

Referring to FIG. 7, the vertical channel transistor 6 of the sixth embodiment differs from the vertical channel transistor 5 of the fifth embodiment in that the upper end of the active layer 610 may be a buried bit line 670. Thus, the buried bit line 670 may be a honeycomb pattern similar to the shape of the active 610. For example, the buried bit line 670 may be implemented by impurity ion implantation at the top of the active 610. The vertical channel transistor 5 of the fifth embodiment may be configured similarly to the vertical channel transistor 5 of the fifth embodiment. The vertical channel transistor 6 of the present embodiment can be implemented by the manufacturing method described in Figs. 37A / B to 40A / B or a similar method.

(Method Example 1)

FIGS. 8A to 17A are plan views illustrating a method of manufacturing a vertical channel transistor according to a first embodiment of the present invention, and FIGS. 8B to 17B are cross-sectional views taken along lines I-I 'of FIGS.

Referring to FIGS. 8A and 8B, a plurality of active elements 110 are formed on a semiconductor substrate 100. The active element 110 may be formed to protrude from the semiconductor substrate 100 in the vertical direction (Z direction in FIG. 1A). The active element 110 may extend in a direction substantially perpendicular to the line I-I '(Y direction in FIG. 1A) and may be formed in the form of a line aligned in the longitudinal direction of the line I-I' (X direction in FIG. 1A) . The active 110 may be defined by forming a trench 119 in the semiconductor substrate 100 and filling the trench 119 with the insulating film 120. For example, a hard mask 130 extending in a direction perpendicular to the line I-I 'is formed on the semiconductor substrate 100, and a part of the semiconductor substrate 100 is removed by dry etching using the hard mask 130 The trench 119 can be formed. The hard mask 130 may be formed by depositing a silicon nitride film (e.g., SiN). The semiconductor substrate 100 may be a single crystal silicon wafer or a SOI substrate. The active 110 may be composed of monocrystalline silicon. The semiconductor substrate 100 and the active 110 may be doped with a first conductive type, such as a P-type impurity. An insulating film 120 is a silicon oxide film can be formed by flattening and then depositing: (SiON example) or a combination thereof (e.g.,:: SiO _2), silicon nitride (e.g., SiN, Si ₃ N _4), silicon oxynitride film. In this specification, the insulating film 120 is referred to as an element isolation film. The planarization of the device isolation film 120 may utilize a chemical mechanical process (CMP).

A photoresist mask 132 may be formed to define the damascene pattern 140. [ The photoresist mask 132 may be in the form of an island arranged in a zigzag manner on any one active 110.

Referring to FIGS. 9A and 9B, the active 110 is patterned to form the vertical channel 115. For example, a damascene pattern 140 having a shallower depth than the isolation film 120 can be formed by etching using the photoresist mask 132. The damascene pattern 140 may be formed by dry etching the active layer 110 and the device isolation layer 120 without any selection. A vertical channel 115 composed of a portion of the active 110 may be formed along with the formation of the damascene pattern 140. Vertical channels 115 may be arranged in zigzag form on active 110. The vertical channel 115 may be in the shape of a cylinder that is adjacent to the edge of the active 110 and protruded vertically. As another example, the vertical channel 115 may have any shape, such as an elliptical column, a square column, and the like. The photoresist mask 132 may be removed by an ashing process.

10A and 10B, a gate insulating film 150 surrounding the side wall of the vertical channel 115 is formed, and the damascene pattern 140 is buried with the gate conductive film 160. The gate insulating layer 150 may be formed by a deposition process of a silicon oxide layer (e.g., SiO ₂ ) or a thermal oxidation process of a sidewall of the vertical channel 110 exposed through the damascene pattern 140. The gate insulating layer 150 may be formed on the upper surface of the active layer 110 in addition to the sidewalls of the vertical channel 115. The gate conductive layer 160 may be formed by depositing doped polysilicon or a metal (e.g., TiN, W, WSi _x ). A planarization process (e.g., CMP) may be performed to expose the hard mask 130 after the deposition of the gate conductive film 160.

Referring to FIGS. 11A and 11B, a recessed gate conductive film 162 is formed to expose the top of the vertical channel 115 and form a gate spacer 134 at the top sidewall of the vertical channel 115. For example, the recessed gate conductive layer 162 may be formed by an etch back process of the gate conductive layer 160. The length (vertical height) of the recess gate conductive film 162 can be precisely controlled by the etch back process of the gate conductive film 160. The gate spacer 134 can be formed by deposition and patterning of a silicon oxide film or a silicon nitride film. The gate spacer 134 may also be formed on the side wall of the hard mask 130.

The recessed gate conductive film 162 exposed by the damascene pattern 140 may be removed and gate separation etching may be performed to form the gate separation pattern 142. [ In the gate separation etching, the hard mask 130 and the gate spacer 134 can be used as masks, so that the mask forming process can be skipped. The gate separation etching process may use dry etching.

12A and 12B, according to the gate separation etching, the recessed gate conductive film 162 covered by the gate spacer 134 is formed of the gate electrode 165 surrounding the side wall of the vertical channel 115 . The gate electrodes 165 may be separated from each other by the gate separation pattern 142. According to the present embodiment, the gate electrode 165 can be formed in a self-aligned manner by the gate separation etching. Further, the length (vertical height) of the gate electrode 165 can be precisely controlled, and the reproducibility of the gate electrode 165 can be ensured. In addition, since the gate electrodes 165 are separated from each other by the gate separation pattern 142, a bridge between the gate electrodes 165 can be avoided. During the gate separation etching process, the portion 151 exposed by the gate separation pattern 142 in the gate insulation layer 150 may be overetched and the active 110 may be exposed.

Impurities may be implanted into the active region 110 under the gate separation pattern 142 to form the lower junction region 102. [ The lower junction region 102 may be doped with a second conductivity type, such as an N-type impurity.

Referring to FIGS. 13A and 13B, a buried bit line pattern 144 is formed below the gate separation pattern 142. As shown in FIG. The buried bit line pattern 144 may be formed by removing at least the active 110 of the active device 110 and the device isolation film 120 exposed by the gate separation pattern 142. [ According to the present embodiment, the active bit line pattern 144 can be formed by dry-etching the active layer 110 and the isolation layer 120 exposed by the gate isolation pattern 142 without any selection ratio. The buried bit line pattern 144 may be formed shallower or deeper than the lower junction region 102. [ Hereinafter, a blank region constituted by the gate isolation pattern 142 and the buried bit line pattern 144 will be referred to as a gap 146 for convenience.

The buried bit line 170 can be formed by implanting N-type impurity into the active 110 exposed by the buried bit line pattern 144. [ The buried bit line 170 may have an impurity concentration different from that of the lower junction region 102. For example, the buried bit line 170 may have a higher impurity concentration than the lower junction region 102. As another example, the active 110 exposed by the buried bit line pattern 144 may be silicided to form a buried bit line 170 comprised of a metal (e.g., CoSi _x ). According to the present embodiment, a plurality of buried bit lines 170 of the same type as the active 110 can be formed. The width of the buried bit line 170 (left and right length in FIG. 13B) may be equal to or less than the width of the active 110. An insulating film such as a silicon oxide film or a silicon nitride film may be deposited before the buried bit line 170 is formed to further form the protective film 136. [ The passivation layer 136 may prevent dopants (e.g., N-type impurities or metals) from being further doped in the lower junction region 102 and the gate electrode 165 exposed by the buried bit line pattern 144. As another example, doped polysilicon may be grown (SEG) from the active 110 exposed by the buried bit line pattern 144, as described below with reference to FIGS. 21A and 21B, May be deposited to fill the buried bit line pattern 144 with a conductor to form a buried bit line (not shown). According to the SEG or conductor deposition process, a buried bit line may be formed which is filled with all or part of the buried bit line pattern 144 and bypasses the vertical channel 115 differently from the shape of the active 110.

An insulating film (not shown) may be further formed on the sidewall of the gate electrode 146 before the buried bit line pattern 144 is formed. This insulating film can be formed by depositing an insulator such as a silicon oxide film or a silicon nitride film so as to have a liner shape covering the gate electrode 165 and the gate spacer 134. As another example, after the lower junction region 102 is formed at a low concentration in the steps of FIGS. 12A and 12B, the lower junction region 102 may be implemented with an LDD structure by high concentration doping.

14A and 14B, the gap 146 between the vertical channels 115 is filled with an insulator. In one example, after the liner 137 is formed in the gap 146, the gap 146 may be completely filled with the gap fill insulating film 138. The liner 137 and the gap fill insulating film 138 may be formed of the same material or different materials among the insulators such as a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a combination thereof. The liner 137 may be formed to conformally cover the inner wall of the gap 146. The gap fill insulating film 138 may be formed by depositing an insulator such that the gap 146 is completely filled, and then planarizing by CMP or etch-back. 13A and 13B, the protective film 136 may be further included in the gap 144, but the protective film 136 is omitted for the sake of brevity of illustration.

Referring to FIGS. 15A and 15B, a word line contact pattern 148 is formed. The word line contact pattern 148 may be formed by recessing the liner 137 and the gap fill insulating film 138. For example, after forming the photoresist mask 133 on the vertical channel 115, the liner 137 and the gap fill insulating film 138 may be partially removed by dry etching using the photoresist mask 133. By the dry etching, the liner 137 and the gap fill insulating film 138 may partially remain in the lower portion of the gap 146. A part of the gap-filling insulating film 138 may be left on the side surface of the gate spacer 134. The word line contact pattern 146 may be formed in a damascene shape extending discontinuously along the line I-I '. The side wall of the gate electrode 164 can be exposed by the word line contact pattern 148. [ The photoresist mask 133 may be removed by an ashing process.

16A and 16B, a word line plug-in 180 is formed and a capping insulating film 139 is formed to cover the word line plug-in 180. As shown in FIG. In one example, the wordline contact pattern 148 may be filled with a conductor and then planarized, and the conductor may be etched back to form the wordline plug-in 180. The word line plug-in 180 may be composed of a conductor that is the same as or different from the gate electrode 165. For example, the word line plug-in 180 may be doped polysilicon or metal (e.g., TiN, W, WSi _x ), or the like. The word line plug-in 180 may have a vertical height that is the same as or different from the gate electrode 165. For example, the word line plug-in 180 may have a lower vertical height than the gate electrode 165. The gate electrode 165 and the word line plug-in 180 are connected to each other, so that a plurality of word lines 190 having a line shape extending along the line I-I 'can be realized. The capping insulating film 139 may be formed by depositing a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a combination thereof, and then planarizing.

17A and 17B, the hard mask 130 is removed. For example, the hard mask 130 may be removed until the vertical channel 115 is exposed in a planarization process using etch back or CMP. The gate spacer 136 and the capping insulating film 139 may be partly removed by the planarization process. Type impurity is implanted into the upper portion of the vertical channel 115 to form the upper junction region 104. [ According to this embodiment, since the vertical channel 115 is exposed in the island shape surrounded by the capping insulating film 139 and the gate spacer 134 by the planarization process, the impurity ion implantation can proceed in a self-aligned manner. The upper junction region 104 can be formed with an LDD structure by low concentration doping and high concentration doping. According to the above series of processes, the vertical channels 115 arranged in a zigzag form and the gate electrodes 165 formed in a self-aligning manner surrounding the vertical channel 115 are connected to each other by the word line plug-in 180 The vertical channel transistor 1 of FIG. 1 including a word line 190 in the form of a line and a buried bit line 170 extending along the active 110 can be implemented.

(Application example of vertical channel transistor)

FIGS. 18A, 19A, and 19B are plan views illustrating a method for fabricating a semiconductor device employing a vertical channel transistor according to a first embodiment of the present invention, and FIG. 18B is a cross-sectional view taken along line I-I 'of FIG. The following description can be applied to other embodiments.

Referring to FIGS. 18A and 18B, the semiconductor device 1a shown in FIG. 2, for example, dynamic RAM can be implemented by forming a capacitor 90 electrically connected to the vertical channel transistor 1. For example, an interlayer insulating film 70 is formed on the vertical channel transistor 1, and a capacitor 90 electrically connected to the upper junction region 104 is formed through the interlayer insulating film 70. The capacitor 90 may be formed to have a cylindrical or cylindrical structure in which the dielectric film 94 is sandwiched between the lower electrode 92 and the upper electrode 96. A contact plug 80 may be further formed between the lower electrode 92 and the upper junction region 104. Alternatively, the gate insulating film 150 may be replaced with an oxide-nitride-oxide film capable of trapping carriers, or a phase change material film may be formed between the word line 190 and the buried bit line 170 The vertical channel transistor 1 can be utilized as a nonvolatile memory element.

19A, a word line contact plug 192 is formed in each of a plurality of word lines 190, and a bit line contact plug 172 is formed in each of a plurality of buried bit lines 170. The word line 190 may be electrically coupled to a peripheral circuit such as a word line driver circuit through a word line contact plug 192 and the bit line contact plug 172 may be electrically coupled to a bit line drive circuit And the like.

The word line contact plugs 192 may be formed to be arranged alternately in the left and right direction. For example, the odd-numbered column word lines 190 may be formed on the left side thereof, and the even-numbered column word lines 190 may be formed with word line contact plugs 192 on the right sides thereof. Similarly, the bit line contact plugs 172 can be formed to be arranged in an alternating up and down direction. For example, the bit lines contact plugs 172 may be formed at the lower ends of the buried bit lines 170 of the odd-numbered rows and at the upper ends of the buried bit lines 170 of the even-numbered rows.

Referring to FIG. 19B, word line contact plugs 192 and bit line contact plugs 172, respectively, may be formed on either side, unlike FIG. 19A. For example, word line contact plugs 192 may be formed at the right ends of the word lines 190 and bit line contact plugs 172 may be formed at the lower ends of the buried bit lines 170 have. As another example, the word line contact plugs 192 may be formed to be arranged laterally alternately as shown in FIG. 19A and the bit line contact plugs 172 may be formed to be arranged on either side as shown in FIG. 19B, The reverse is also possible.

(Method Example 2)

FIGS. 20A to 24A are plan views illustrating a method of manufacturing a vertical channel transistor according to a second embodiment of the present invention, and FIGS. 20B to 24B are cross-sectional views taken along line II-II 'of FIGS. For the sake of brevity of description, the description overlapping with Embodiment 1 will be avoided, and this is also true in the following other embodiments.

20A and 20B, an active layer 210 is formed on a semiconductor substrate 200 by an isolation layer 220, and an active layer 210 is patterned to form vertical channels 215 arranged in a zigzag pattern do. Next, a gate insulating film 250 and a gate electrode 265 are formed to surround the side wall of the vertical channel 215. The gate electrode 265 can self-align the gate electrode 265 by depositing and recessing the gate conductive film and dry etching using the gate spacer 234 in a process similar to that described in FIGS. 11B and 12B.

Subsequently, a protective film 236 is formed on the inner wall of the gate separation pattern 242. The protective film 236 may be formed in a liner shape by depositing a silicon oxide film or a silicon nitride film, for example, in a conformal manner. A buried bit line pattern 244 is formed below the gate isolation pattern 242. [ The buried bit line 244 may be formed by selectively dry etching the active 210 forming the bottom surface of the gate isolation pattern 242. The gate insulating layer 250 exposed by the gate isolation pattern 242 can be removed during dry etching for forming the buried bit line pattern 244. [ Alternatively, the buried bit line pattern 244 may be formed by dry etching the active layer 210 and the device insulating layer 220 to have the same shape as the buried bit line pattern 144 of FIG. 13B.

The lower junction region 202 can be formed by impurity ion implantation before the buried bit line pattern 244 is formed. The lower junction region 202 can be formed with an LDD structure by low-concentration impurity doping and high-concentration impurity doping. In this case, the buried bit line pattern 244 can be formed deeper than the lower junction region 202. Alternatively, the lower junction region 202 may be formed in the next step.

Referring to FIGS. 21A and 21B, an embedded bit line 270 is formed. The buried bit line 270 may be formed using a selective epitaxial growth technique. According to the SEG, the buried bit line 270 may be formed in a curved shape that fills all or part of the buried bit line pattern 244 and bypasses the vertical channel 215 differently from the shape of the active 210. As another example, the buried bit line 270 can be formed by deposition of a conductor and etch back. For example, impurity-doped silicon may be deposited in the buried bit line pattern 244 and subjected to a silicide reaction (e.g., CoSi _x ) to form a silicided buried bit line 270. During the silicide reaction, impurities doped into the silicon may be transferred to the active region 210 so that the buried bit line 270 and the lower junction region 202 may be simultaneously formed. As another example, the active 210 exposed by the buried bit line pattern 244 may be silicided to form a buried bit line 270 comprised of a metal (e.g., CoSi _x ). According to this embodiment, the protective film 236 can prevent damage or impurity doping of the gate electrode 265 during an etch-back or silicide process.

Then, a gap-filling insulating film 238 for filling the gate separation pattern 242 is formed. The gap fill insulating film 238 can be formed by depositing a silicon oxide film, a silicon nitride film, or a combination thereof and carbonizing it. If the buried bit line 270 is not filled with all of the buried bit line pattern 244, the remaining part thereof may be filled with the gap fill insulating film 238. As another example, an insulating film similar to the liner 137 of FIG. 14B may be further formed before the gap fill insulating film 238 is formed.

Referring to Figures 22A and 22B, a word line contact pattern 248 is formed that exposes the sidewalls of the gate electrode 265. The word line contact pattern 248 can be formed by recessing the protective film 236 and the gap fill insulating film 238 by dry etching. The word line contact pattern 248 may be formed in the form of a line extending discontinuously along the line II-II '.

23A and 23B, a word line plug-in 280 connected to the gate electrode 265 by filling the word line contact pattern 248 with a conductor, and a capping insulating film 239 covering the word line plug- ). As a result, the two left and right gate electrodes 265 are connected to each other by the word line plug-in 280 formed therebetween, so that the word line 290 can be realized.

Referring to FIGS. 24A and 24B, the hard mask 230 is removed and an upper junction region 204 is formed at the upper end of the vertical channel 215. As a result, vertical channels 215 arranged in a zigzag pattern and gate electrodes 265 formed in a self-aligning manner surrounding vertical channels 215 are connected to word lines (not shown) connected to each other by word line plug- 3 and the buried bit line 270 extending in a curved shape along the edge of the active 210. The vertical channel transistor 2 of FIG.

(Method Example 3)

FIGS. 25A to 27A are plan views illustrating a method of manufacturing a vertical channel transistor according to a third embodiment of the present invention, and FIGS. 25B to 27B are cross-sectional views taken along line III-III 'of FIGS.

25A and 25B, an active 310 separated by a device isolation layer 320 is formed on a semiconductor substrate 300, and the active 310 is patterned to form a straight line along the longitudinal direction of the active 310 To form an arrayed vertical channel 315. The vertical channel 315 may be formed to be adjacent to one edge of the active 310. A gate insulating film 350 is formed surrounding the sidewalls of the vertical channel 315 and the gate electrode 365 is formed in a self-aligned manner by deposition and recessing of the gate conductive film and dry etching using the gate spacer 334. [ The gate electrodes 365 can be separated from each other by the gate separation pattern 342. [

The active 310 forming the bottom surface of the gate isolation pattern 342 is dry etched with the isolation layer 320 without any selection to form the buried bit line pattern 344. [ Alternatively, the buried bit line pattern 344 may be selectively dry etched the active 310 to have the same shape as the buried bit line pattern 244 of FIG. 20B. The lower junction region 302 can be formed by impurity ion implantation before the buried bit line pattern 344 is formed.

And causes the active 310 exposed by the buried bit line pattern 344 to be silicided by impurity ion implantation or active 310. According to this embodiment, a buried bit line 370 that extends in the longitudinal direction of the active 310 and is equal to or smaller than the width of the active 310 can be formed.

26A and 26B, a word line plug-in 380 connecting the gate electrode 365 to the etch back and the deposition and recessing of the liner 337 and the gap fill insulation film 338, . The word line plug-in 380 implements the word line 390 by connecting the gate electrodes 365 formed on both sides thereof. A capping insulating film 339 is formed to cover the word line plug-in 380.

Referring to FIGS. 27A and 27B, the hard mask 330 is removed in the planarization process and the upper junction region 304 is formed by impurity ion implantation at the upper end of the vertical channel 315. Thereby a vertical channel 315 arranged in a straight line and a gate electrode 365 formed in a self-aligning manner surrounding the vertical channel 315 are connected to a word line (line type) connected to each other by a word line plug- The vertical channel transistor 3 of FIG. 4 may be implemented that includes a buried bit line 370 extending along the active 310 and a buried bit line 370 extending along the active 310.

(Method Example 4)

FIGS. 28A to 30A are plan views illustrating a method of manufacturing a vertical channel transistor according to a fourth embodiment of the present invention, and FIGS. 28B to 30B are cross-sectional views taken along lines IV-IV 'of FIGS. For the sake of brevity of the description, the description overlapping with Embodiment 1 will be avoided.

Referring to FIGS. 28A and 28B, a vertical channel 315 is aligned on the semiconductor substrate 400 along the active 410. And may occupy the center of the active 410 of the vertical channel 315. A gate insulating film 450 and a gate electrode 465 surrounding the side wall of the vertical channel 315 are formed. The gate electrode 465 is formed in a self-aligning manner by dry etching using a gate spacer 434 and can be separated from each other by a gate separation pattern 442. [ Impurities are ion-implanted into the active region 410 forming the bottom surface of the gate isolation pattern 442 to form a lower junction region 402.

A buried bit line pattern 444 is formed below the gate isolation pattern 442 and an embedded bit line 470 is formed in the active 410 exposed by the buried bit line pattern 444 by an impurity ion implantation or silicide process. . The buried bit line pattern 444 may be formed by dry etching the active layer 410 and the device isolation layer 420 without selection, or by selectively dry etching the active layer 410. According to this embodiment, the buried bit line 470 may be formed in a form extending along the active 410 below the vertical channel 415. [

29A and 29B, the lower part of the gate separation pattern 442 is filled with the liner 437 and the gap fill insulating film 438, and the word line contact 480 connecting the gate electrode 465 thereon is disposed Thereby forming a word line 490. The word line contact 480 is capped with a capping insulating film 439.

30A and 30B, the removal of the hard mask 430 and the formation of the upper junction region 404 provide a vertical channel 415 arranged in a straight line, a vertical channel 415 surrounding the vertical channel 415, 5, which includes a word line 490 in the form of a line connected to the gate electrode 465 formed by the word line contact 480 and a buried bit line 470 extending along the active line 410, 4) may be implemented.

(Method Example 5)

FIGS. 31A to 36A are plan views illustrating a method of manufacturing a vertical channel transistor according to a fifth embodiment of the present invention, and FIGS. 31B to 36B are cross-sectional views taken on line V-V 'of FIGS.

Referring to FIGS. 31A and 31B, an active 510 defined by a device isolation layer 520 is formed on a semiconductor substrate 500. The active layer 510 may be formed to have a honeycomb pattern formed by intersecting a plurality of obliquely crossed lines. For example, a plurality of first active portions 511 extending from the lower left to upper right and a plurality of second active portions 512 extending upward from the lower right to the upper left may be sequentially formed to realize the honeycomb pattern active 510 have. As another example, the semiconductor substrate 500 may be partially removed by dry etching using a hard mask 530 having a honeycomb pattern to simultaneously form the first active 511 and the second active 512 to form an active 510 ) Can be implemented.

A photoresist mask 532 may be formed to define a damascene pattern 540. [ The damascene pattern 540 may be formed by removing a portion of the active 510 and the isolation layer 520. A photoresist mask 532 may be formed on the active 510. In one example, a photoresist mask 532 may be formed at the intersection of the first active 511 and the second active 512 and arranged in a zigzag form on the semiconductor substrate 500.

Referring to FIGS. 32A and 32B, vertical channels 515 arranged in a zigzag form on the semiconductor substrate 500 are formed. For example, the active 510 and the isolation layer 520 are removed by dry etching using a photoresist mask 532 to form a damascene pattern 540. A plurality of vertical channels 515 that are part of the active 510 and that are vertically protruding on the semiconductor substrate 500 can be defined by the formation of the damascene pattern 540. [ The photoresist mask 532 may be removed by an ashing process.

A gate insulating film 515 and a gate electrode 565 surrounding the side wall of the vertical channel 515 are formed. A plurality of gate electrodes 565 separated from each other by the gate separation pattern 542 by the gate separation etching as described with reference to FIGS. 10B to 12B can be formed in a self-aligning manner.

The active 510 between the vertical channels 515 is doped with an impurity to form a lower junction region 502. The protective layer 536 may be formed by depositing an insulator on the sidewall of the gate electrode 565. [ The protective film 536 can prevent impurities from being doped into the gate electrode 565 in the impurity doping process.

Referring to FIGS. 33A and 33B, a buried bit line pattern 544 extending in one direction on a semiconductor substrate 500 is formed. The embedded bit line pattern 544 can be formed by recessing the active layer 510 and the isolation layer 520 by dry etching the active layer 510 and the isolation layer 520 without any selection. Etch damage of the gate electrode 565, which may be generated in the dry etching, may be prevented by the protective film 536. [ In one embedded bit line pattern 544, vertical channels 515 arranged in a zigzag form along the longitudinal direction of the embedded bit line pattern 544 may be included.

Referring to FIGS. 34A and 34B, buried bit line 570 is formed in buried bit line pattern 444. In one example, a buried bit line 570 can be formed that fills the buried bit line pattern 544 with a conductor deposit and etch back in a gap 546 between the vertical channels 515. As another example, impurity-doped silicon may be deposited in the buried bit line pattern 444 and subjected to a silicide reaction to form a silicided buried bit line 570. During the silicide reaction, impurities doped into silicon may be transferred to the active region 510 so that the buried bit line 570 and the lower junction region 502 may be simultaneously formed. According to the present embodiment, the buried bit line 570 extends in a straight line at the bottom of the zigzag arranged vertical channels 515 and intersects the first active 511 or the second active 512 in an oblique direction May be formed in a line shape.

35A and 35B, a word line plug-in 580 is formed by depositing and recessing a gap fill insulating film 538, depositing a conductor, and connecting the gate electrode 565 to the etch-back to form a word line 590 ). And a capping insulating film 539 covering the word line plug-in 580 is formed. The word line 590 may be formed in a line shape that crosses the first active line 511 or the second active line 512 in an oblique direction.

Referring to FIGS. 36A and 36B, the hard mask 530 is removed in the planarization process, and the upper junction region 504 is formed by impurity ion implantation at the upper end of the vertical channel 515. Thereby a vertical channel 515 arranged in zigzag form on the honeycomb patterned active 510 and a gate electrode 565 formed in a self-aligning manner surrounding the vertical channel 515 are connected to the word line plug-in 580 The vertical channel transistor 5 of FIG. 6, including a word line 590 in the form of a line connected to each other by an active line 510 and an embedded bit line 570 in the form of a line extending in an oblique direction to the active line 510, .

(Method Example 6)

FIGS. 37A to 40A are plan views illustrating a method of manufacturing a vertical channel transistor according to a sixth embodiment of the present invention, and FIGS. 37B to 40B are cross-sectional views taken on lines VI-VI 'of FIGS.

37A and 37B, an active layer 610 separated by a device isolation layer 620 is formed on a semiconductor substrate 600, a part of the active layer 610 and the device isolation layer 620 are removed, And a gate insulating film 650 and a gate electrode 665 surrounding the vertical channel 615 are formed. The active layer 610 may be formed to have a honeycomb pattern by dry etching using a hard mask 630 and a plurality of vertical channels 615 may be arranged in a zigzag form on the active layer 610. The gate electrode 665 may be formed in a self-aligned manner by forming a gate isolation pattern 642 by dry etching using a gate spacer 634. [ A protective film 636 surrounding the gate electrode 665 is formed and then an impurity is ion-implanted into the active region 610 to form a lower junction region 602.

Referring to FIGS. 38A and 38B, the active layer 610 and the device isolation layer 620 are dry-etched without any selection to recess the active layer 610 and the device isolation layer 620. According to the recess process, a buried bit line pattern 644 extending in one direction on the semiconductor substrate 600 and providing a region in which the vertical channels 615 are arranged in a zigzag pattern is formed. The active 610 exposed by the buried bit line pattern 644 is doped with an impurity or the active 610 is silicided to form a buried bit line 670. [ 34A and 34B, the buried bit line 670 is formed to be confined to the active region 610 and extends in one direction on the semiconductor substrate 600, with the arrangement of the vertical channels 615 And can be formed so as to have a zigzag shape in the same manner.

39A and 39B, a word line plug-in 680 is formed by depositing and recessing a gap fill insulating film 638, depositing a conductor, and connecting the gate electrode 665 to the etch-back to form a word line 690 ). And a capping insulating film 639 covering the word line plug-in 680 is formed. The buried bit line pattern 644 is formed on the buried bit line 670 because the buried bit line 670 is formed by doping or siliciding the active 610 exposed by the buried bit line pattern 644. [ ). ≪ / RTI > Accordingly, the gap fill insulating film 638 may be filled with the gap fill insulating film 638 in the unfilled region of the buried bit line pattern 644.

Referring to FIGS. 40A and 40B, the hard mask 630 is removed in the planarization process and the upper junction region 604 is formed by impurity ion implantation at the upper end of the vertical channel 615. As a result, a vertical channel 615 arranged in zigzag form on the honeycomb pattern active 610 and a gate electrode 665 formed in a self-aligning manner surrounding the vertical channel 615 are connected to the word line plug-in 680 The vertical channel transistor 6 of FIG. 7 may be implemented that includes a word line 690 in the form of a line connected to each other by an impurity and an embedded bit line 670 extending in a zigzag form provided with impurities in the active 610 have.

(Application example)

42A and 42B are block diagrams illustrating an application of a vertical channel transistor according to an embodiment of the present invention. Hereinafter, an example in which the vertical channel transistor of the present embodiment is used in a memory has been described. However, the present invention is not limited thereto and can be applied to a non-memory such as a central processing unit.

Referring to Figure 42A, an electronic device 1300 including a vertical channel transistor in accordance with embodiments of the present invention is described. The electronic device 1300 may be a wireless communication device such as a PDA, a laptop computer, a portable computer, a web tablet, a cordless telephone, a cellular phone, a digital music player, Lt; RTI ID = 0.0 > and / or < / RTI > The electronic device 1300 may include an input and output device 1320 such as a controller 1310, a keypad, a keyboard, a display, a memory 1330, and a wireless interface 1340 coupled together via a bus 1350. Controller 1310 may include, for example, one or more microprocessors, digital signal processors, microcontrollers, or the like. Memory 1330 may be used to store instructions executed by controller 1310, for example. Memory 1330 may be used to store user data. Memory 1330 includes a vertical channel transistor in accordance with embodiments of the present invention. The electronic device 1300 may use the wireless interface 1340 to transmit data to or receive data from a wireless communication network that communicates with an RF signal. For example, the wireless interface 1340 may include an antenna, a wireless transceiver, and the like. Electronic device 1300 may be used in communication interface protocols such as third generation communication systems such as CDMA, GSM, NADC, E-TDMA, WCDAM, CDMA2000.

Referring to Figure 42B, a memory system including a semiconductor memory configured with vertical channel transistors in accordance with embodiments of the present invention is described. Memory system 1400 may include memory 1410 and memory controller 1420 for storing large amounts of data. The memory controller 1420 controls the memory device 1410 to read or write the stored data from the memory 1410 in response to a read / write request of the host 1430. Memory controller 1420 may configure an address mapping table for mapping addresses provided by host 1430, e.g., a mobile device or computer system, to the physical address of memory 1410. The memory 1410 may include a vertical channel transistor according to an embodiment of the present invention.

It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and it will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit of the invention. The appended claims should be construed to include other embodiments.

Claims (8)

Patterning the substrate to form an active;
Patterning the active to form a plurality of vertical channels protruding vertically from the substrate;
Forming a conductor between the plurality of vertical channels to expose an upper portion of the vertical channel;
Forming gate spacers on top of the plurality of vertical channels;
Patterning the conductor by etching with the gate spacer as a mask to form a plurality of gate electrodes self-aligning surrounding the sidewalls of the plurality of vertical channels;
Forming a buried bit line extending in a first horizontal direction on the substrate beneath the plurality of vertical channels; And
Forming a plurality of plug-ins extending between the plurality of vertical channels in a second horizontal direction perpendicular to the first horizontal direction to connect the plurality of gate electrodes;
/ RTI > A method of manufacturing a vertical channel transistor comprising: The method according to claim 1,
The active is formed by:
And patterning the substrate to form a line-shaped active extending in one direction on the substrate. 3. The method of claim 2,
Forming the plurality of vertical channels comprises:
And patterning the active to form the plurality of channels in a line in one direction,
Wherein the plurality of vertical channels are arranged in a line along the center or one edge of the active or zigzag along the edges of the active. The method according to claim 1,
Forming the buried bit line comprises:
Recessing the active between the plurality of vertical channels to form a buried bit line pattern; And
Implanting impurities into the active exposed by the buried bit line pattern or filling the buried bit line pattern with a conductor to form the buried bit line;
/ RTI > A method of manufacturing a vertical channel transistor comprising: The method according to claim 1,
The conductor is formed by:
Depositing a gate conductive layer between the plurality of vertical channels; And
Etching the gate conductive film to form a recessed gate conductive film exposing an upper portion of the vertical channel;
/ RTI > A method of manufacturing a vertical channel transistor comprising: 6. The method of claim 5,
Forming the gate spacer comprises:
Depositing an insulating material on the recessed gate conductive film; And
Patterning the insulator to form the gate spacer surrounding the upper peripheral surface of the vertical channel;
/ RTI > A method of manufacturing a vertical channel transistor comprising: The method according to claim 6,
Forming the plurality of gate electrodes comprises:
Forming a gate isolation pattern by partially removing the recessed gate conductive film by dry etching using the gate spacer as a mask,
And the plurality of gate electrodes are separated from each other by the plurality of vertical channels by the gate separation pattern. 8. The method of claim 7,
And implanting impurities into the active under the gate isolation pattern to form a lower junction region.

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