CN113506737A - Pillar transistor and method of manufacturing the same, and semiconductor device and method of manufacturing the same - Google Patents

Pillar transistor and method of manufacturing the same, and semiconductor device and method of manufacturing the same Download PDF

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Publication number
CN113506737A
CN113506737A CN202110422036.9A CN202110422036A CN113506737A CN 113506737 A CN113506737 A CN 113506737A CN 202110422036 A CN202110422036 A CN 202110422036A CN 113506737 A CN113506737 A CN 113506737A
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transistor
forming
column
wafer
pillar
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CN202110422036.9A
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CN113506737B (en
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华文宇
王喜龙
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ICLeague Technology Co Ltd
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ICLeague Technology Co Ltd
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Priority to CN202110422036.9A priority Critical patent/CN113506737B/en
Priority to KR1020237038547A priority patent/KR20240008849A/en
Priority to PCT/CN2021/111345 priority patent/WO2022222310A1/en
Publication of CN113506737A publication Critical patent/CN113506737A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/488—Word lines

Abstract

The embodiment of the application provides a column transistor and a manufacturing method thereof, a semiconductor device and a manufacturing method thereof, wherein the manufacturing method of the column transistor comprises the following steps: providing a wafer, wherein the wafer is provided with a plurality of transistor forming areas, each transistor forming area is provided with a transistor column, and each transistor column is provided with an exposed side wall; sequentially forming a grid oxide layer and a grid on the side wall of each transistor column; forming a source electrode at a first end of the transistor column; forming a drain electrode at a second end of the transistor column, wherein the first end and the second end are two opposite ends of the transistor column in a first direction, and the first direction is the thickness direction of the wafer; the transistor column between the source and the drain constitutes a channel region of the transistor.

Description

Pillar transistor and method of manufacturing the same, and semiconductor device and method of manufacturing the same
Technical Field
The present application relates to the field of semiconductor technology, and relates to, but is not limited to, a pillar transistor and a method for manufacturing the same, and a semiconductor device and a method for manufacturing the same.
Background
Transistors are widely used as switching devices or driving devices in electronic equipment. For example, the transistor may be used in a Dynamic Random Access Memory (DRAM) for controlling a capacitance in each Memory cell.
In the related art, the transistor mainly includes a planar transistor and a buried channel transistor, however, regardless of whether the planar transistor or the buried channel transistor is used, the Source (Source, S) and the Drain (Drain, D) are both located on two horizontal sides of the Gate (Gate, G), and the Source and the Drain occupy different positions respectively, so that the area of the transistor is large. In addition, in the memory device, the source and the drain of the transistor are connected to different structures after being formed, and when the source and the drain are located on two horizontal sides of the gate, the circuit wiring inside the memory is complex and the manufacturing process is difficult.
Disclosure of Invention
Embodiments of the present application provide a pillar transistor and a method of manufacturing the same, and a semiconductor device and a method of manufacturing the same.
In a first aspect, an embodiment of the present application provides a method for manufacturing a pillar transistor, including:
providing a wafer, wherein the wafer is provided with a plurality of transistor forming areas, each transistor forming area is provided with a transistor column, and each transistor column is provided with an exposed side wall;
sequentially forming a grid oxide layer and a grid on the side wall of each transistor column;
forming a source electrode at a first end of the transistor column;
forming a drain electrode at a second end of the transistor column, wherein the first end and the second end are two opposite ends of the transistor column in a first direction, and the first direction is the thickness direction of the wafer; the transistor column between the source and the drain constitutes the channel region of the transistor.
In some embodiments, the transistor forming region further has an insulating layer wrapping other sidewalls of the transistor pillar; the transistor forming region is formed by:
partially etching the wafer by taking the first surface of the wafer as an etching starting point along the first direction to form a grid-shaped etching groove consisting of a plurality of silicon columns, wherein each silicon column has a first preset thickness, and the first preset thickness is smaller than the initial thickness of the wafer; the first surface of the wafer is any one surface of the wafer along the first direction;
depositing an insulating material in the grid-shaped etching groove to form an insulating layer surrounding each silicon pillar;
and etching the silicon column and the insulating layer to form the transistor column with an exposed side wall, and obtaining the transistor forming area.
In some embodiments, the etching the silicon pillar and the insulating layer to form the transistor pillar with an exposed sidewall includes:
taking the edge position of the silicon column as an etching starting point, carrying out partial etching treatment on the silicon column and the insulating layer along the first direction, removing the silicon column and the insulating layer which have preset sizes in the second direction and have the first preset thickness in the first direction, forming the transistor column with an exposed side wall, and forming an etching groove; wherein the preset dimension is smaller than the initial dimension of the silicon pillar in the second direction; the second direction is perpendicular to the first direction.
In some embodiments, prior to forming the gate oxide layer and the gate, the method further comprises:
depositing and forming a first isolating layer at the bottom of the etching groove;
correspondingly, the forming a gate oxide layer and a gate on the sidewall of each transistor column in turn includes:
forming an initial gate oxide layer on the sidewall of the transistor column by in-situ oxidation;
depositing a polysilicon material in the etching groove to form a polysilicon layer;
and simultaneously etching the initial grid oxide layer and the polycrystalline silicon layer in the first direction, and removing the initial grid oxide layer and the polycrystalline silicon layer with partial thickness in the first direction to form the grid oxide layer and the grid.
In some embodiments, after forming the gate oxide layer and the gate, the method further comprises:
and depositing to form a second isolation layer in the etching groove, wherein the second isolation layer is positioned in a projection area of the transistor column in the second direction, and the size of the second isolation layer in the third direction is equal to that of the transistor column in the third direction.
In some embodiments, prior to forming the drain, the method further comprises:
thinning the wafer from the second surface of the wafer until the first isolation layer and the second end of the transistor column are exposed; wherein the second side of the wafer is a side opposite to the first side of the wafer.
In some embodiments, the source and the drain are the same or different in shape;
the shape of the source electrode and the drain electrode includes any one of: square, semi-circular, triangular or any polygon.
In a second aspect, embodiments of the present application provide a pillar-shaped transistor, including:
a channel region;
a source electrode positioned at a first end of the channel region;
the drain electrode is positioned at a second end of the channel region, wherein the first end and the second end are two opposite ends of the channel region in a first direction respectively, and the first direction is the thickness direction of a wafer forming the channel region;
a gate electrode positioned at either side of the channel region and corresponding to the channel region;
and the grid oxide layer is positioned between the channel region and the grid.
In a third aspect, an embodiment of the present application provides a method for forming a semiconductor device, where the method includes:
forming at least one memory cell, wherein each of the memory cells comprises at least: a pillar-shaped transistor; the pillar-shaped transistor includes: a gate, a source and a drain; the pillar-shaped transistor is manufactured by the manufacturing method of the pillar-shaped transistor;
forming a word line, wherein the word line is connected with the grid electrode of the cylindrical transistor, and is used for providing a word line voltage and controlling the cylindrical transistor to be switched on or switched off through the word line voltage;
and forming a bit line connected with the source electrode or the drain electrode of the cylindrical transistor, wherein the bit line is used for performing reading or writing operation on the memory cell when the cylindrical transistor is conducted.
In a fourth aspect, embodiments of the present application provide a semiconductor device, including: at least one memory cell, a word line, and a bit line, each of the memory cells comprising at least: the above-described pillar-shaped transistor; the pillar-shaped transistor includes at least: a gate, a source and a drain;
the word line is connected with the grid electrode of the cylindrical transistor and used for providing a word line voltage and controlling the cylindrical transistor to be switched on or switched off through the word line voltage;
the bit line is connected with the source electrode or the drain electrode of the cylindrical transistor, and the bit line is used for performing reading or writing operation on the memory cell when the cylindrical transistor is conducted.
In some embodiments, the memory cell further comprises: a storage capacitor;
one end of the storage capacitor is connected with the drain electrode or the source electrode of the cylindrical transistor, the other end of the storage capacitor is grounded, and the storage capacitor is used for storing data written into the memory unit.
In some embodiments, the memory cell further comprises: an adjustable resistor;
the adjustable resistor is connected between the bit line and the source of the pillar-shaped transistor, or between the bit line and the drain of the pillar-shaped transistor, and the adjustable resistor is used for adjusting the state of data stored in the memory cell through a bit line voltage provided by the bit line.
In some embodiments, when the semiconductor device includes a plurality of the memory cells, the plurality of the memory cells are connected in parallel or in series.
According to the pillar-shaped transistor and the manufacturing method thereof, and the semiconductor device and the manufacturing method thereof, the source and the drain of the formed pillar-shaped transistor are respectively located at the first end and the second end of the channel region in the first direction, and the first direction is the thickness direction of the wafer for forming the channel region, so that the area of the transistor is greatly reduced. The column-shaped transistor provided by the embodiment of the application can be used for forming a memory, and the drain electrode and the source electrode of the transistor are positioned on different surfaces of the wafer, so that different structures connected with the source electrode and the drain electrode in the memory can be respectively designed in two surfaces of the wafer, namely in two opposite surfaces of the wafer, thereby simplifying the circuit layout in the memory and reducing the process difficulty of manufacturing the memory.
Drawings
In the drawings, which are not necessarily drawn to scale, like reference numerals may describe similar components in different views. Like reference numerals having different letter suffixes may represent different examples of similar components. The drawings illustrate generally, by way of example, but not by way of limitation, various embodiments discussed herein.
FIG. 1A is a schematic diagram of a planar transistor in the related art;
FIG. 1B is a schematic diagram of a buried channel transistor in the related art;
FIG. 1C is a schematic diagram of a DRAM memory cell formed by planar transistors according to the related art;
FIG. 1D is a schematic diagram of a DRAM memory cell formed using a buried channel transistor in accordance with the prior art;
fig. 2 is an alternative structural diagram of a pillar transistor provided in an embodiment of the present application;
fig. 3A is a schematic flow chart illustrating an alternative method for manufacturing a pillar transistor according to an embodiment of the present disclosure;
FIG. 3B is a cross-sectional view of a grid-like etched trench taken along a first direction according to an embodiment of the present disclosure;
fig. 3C is a top view of a grid-shaped etched trench provided in the present embodiment;
FIG. 3D is a top view of an embodiment of the present disclosure showing the formation of an insulating layer in a grid-like etched trench;
fig. 3E is a top view of a transistor column provided in an embodiment of the present application;
fig. 3F is a schematic structural diagram of forming a first isolation layer according to an embodiment of the present disclosure;
fig. 3G is a schematic structural diagram illustrating the formation of an initial gate oxide layer according to an embodiment of the present disclosure;
fig. 3H is a schematic structural diagram of forming a gate oxide layer and a gate according to an embodiment of the present disclosure;
fig. 3I is a schematic structural diagram of forming a second isolation layer according to an embodiment of the present disclosure;
fig. 3J is a schematic structural diagram of forming a source according to an embodiment of the present disclosure;
fig. 3K is a schematic structural diagram of a transistor after thinning a second surface of a wafer according to an embodiment of the present disclosure;
fig. 3L is a schematic structural diagram of forming a drain according to an embodiment of the present disclosure;
fig. 3M is a schematic diagram of an alternative structure of a pillar transistor according to an embodiment of the present disclosure;
fig. 3N is a schematic diagram of an alternative structure of a pillar transistor according to an embodiment of the present disclosure;
fig. 4A is a schematic structural diagram of an alternative semiconductor device provided in an embodiment of the present application;
FIG. 4B is a schematic diagram of an alternative structure of a DRAM cell according to an embodiment of the present application;
FIG. 4C is a schematic diagram of an alternative structure of a PCM memory cell according to an embodiment of the present application;
fig. 5 is an alternative structure diagram of a method for forming a semiconductor device according to an embodiment of the present disclosure.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, specific technical solutions of the present invention will be described in further detail below with reference to the accompanying drawings in the embodiments of the present application. The following examples are intended to illustrate the present application but are not intended to limit the scope of the present application.
In the following description, suffixes such as "module" or "unit" used to denote elements are used only for facilitating the explanation of the present application, and have no specific meaning in themselves. Thus, "module" or "unit" may be used mixedly.
In the related art, transistors of mainstream memories include a Planar Transistor (Planar) and a Buried Channel Transistor (BCAT), but in both the Planar Transistor and the Buried Channel Transistor, a source and a drain are located on both horizontal sides of a gate. Fig. 1A is a schematic structural view of a planar transistor in the related art, and fig. 1B is a schematic structural view of a buried channel transistor in the related art, as shown in fig. 1A and 1B, a source S and a drain D of the transistor in the related art are respectively located at two horizontal sides of a gate G. Under the structure, the source electrode and the drain electrode respectively occupy different positions, so that the area of the transistor is larger in both a planar transistor and a buried channel transistor.
In addition, since a transistor can be manufactured over a silicon substrate, the transistor can be used in various memories, for example, a DRAM. Generally, a DRAM is composed of a plurality of memory cells, each memory cell is mainly composed of a transistor and a capacitor operated by the transistor, that is, the DRAM is a memory cell with 1 transistor and 1 capacitor C (1T 1C). Fig. 1C is a schematic diagram showing a structure of a DRAM memory cell formed by using a planar transistor in the related art, and fig. 1D is a schematic diagram showing a structure of a DRAM memory cell formed by using a buried channel transistor in the related art, as shown in fig. 1C and 1D, a source (or drain) 101 of a transistor in the DRAM memory cell is connected to a bit line 102, and a drain (or source) 103 is connected to a capacitor 104. For Chips formed by BCAT, Chip On Board (COB) packaging is generally used to form the memory. Because the source and the drain of the planar transistor and the buried channel transistor are respectively located at two horizontal sides of the gate, the bit line and the capacitor in the DRAM memory cell are also located at the same side of the gate, and the connection among the bit line, the transistor and the capacitor, the connection between the Word Line (WL) and the transistor, and the like are also required to be realized in the subsequent process, thereby causing the circuit wiring to be complicated and the manufacturing process difficulty to be large in the memory array region of the DRAM memory.
Based on the above problems in the related art, embodiments of the present application provide a pillar transistor and a method for manufacturing the pillar transistor, a semiconductor device and a method for manufacturing the semiconductor device, which can provide a transistor structure with a smaller area.
Fig. 2 is an alternative structural schematic diagram of a pillar transistor provided in an embodiment of the present application, and as shown in fig. 2, the pillar transistor 20 includes: channel region 201, source 202, drain 203, gate 204, and gate oxide 205.
Wherein the channel region 201 has a vertical structure, and the source 202 is located at a first end of the channel region 201; the drain 203 is located at a second end of the channel region 201, where the first end and the second end are two opposite ends of the channel region in a first direction, and the first direction is a thickness direction (e.g., a Z-axis direction in fig. 2) of a wafer forming the channel region. In the embodiment of the present application, the positions of the source 202 and the drain 203 can be interchanged.
The gate 204 is located on either side of the channel region 201 and corresponds to the channel region 204, and the gate oxide 205 is located between the channel region 201 and the gate 204.
In the embodiment of the present application, the source and the drain are respectively located at two opposite ends in the thickness direction of the wafer on which the channel region is formed, that is, the source and the drain of the pillar-shaped transistor provided in the embodiment of the present application are located in two opposite faces of the wafer, so that the area of the transistor is greatly reduced.
The pillar-shaped transistor provided in the embodiments of the present application can be formed by the method for manufacturing a pillar-shaped transistor provided in the embodiments described below.
Fig. 3A is an alternative flow chart of a method for manufacturing a pillar transistor according to an embodiment of the present application, and as shown in fig. 3A, the method for manufacturing a pillar transistor includes the following steps:
step S301, a wafer is provided, where the wafer has a plurality of transistor forming regions, each transistor forming region has a transistor column, and each transistor column has an exposed sidewall.
Step S302, sequentially forming a gate oxide layer and a gate on the sidewall of each transistor column.
Step S303, forming a source at the first end of the transistor column.
And step S304, forming a drain electrode at the second end of the transistor column.
The first end and the second end are two opposite ends of the transistor column in a first direction respectively, and the first direction is the thickness direction of the wafer; the transistor column between the source and the drain constitutes the channel region of the transistor.
Referring to fig. 3B to fig. 3L, a method for manufacturing a pillar transistor according to an embodiment of the present disclosure will be described in further detail.
In the embodiment of the application, the transistor forming areas are areas used for forming transistors on a wafer, each transistor forming area is provided with a transistor column, and each transistor column is provided with an exposed side wall. The transistor forming region also has an insulating layer wrapping other sidewalls of the transistor column.
First, referring to fig. 3B to fig. 3E, step S301 is executed to provide a wafer having a plurality of transistor forming regions, each transistor forming region having a transistor pillar, and each transistor pillar having an exposed sidewall. In some embodiments, the transistor forming region is formed by:
and S3011, partially etching the wafer along the first direction by taking the first surface of the wafer as an etching starting point to form a grid-shaped etching groove consisting of a plurality of silicon columns.
Each silicon column is provided with a first preset thickness, and the first preset thickness is smaller than the initial thickness of the wafer; the first surface of the wafer is any one surface of the wafer along the first direction.
Here, the thickness direction of the wafer is defined as a first direction. And defining a second direction and a third direction which intersect with each other in the top surface or the bottom surface of the wafer perpendicular to the first direction, wherein the top surface or the bottom surface of the wafer perpendicular to the first direction can be determined based on the second direction and the third direction. For example, the second direction and the third direction are perpendicular to each other, and thus, the first direction, the second direction and the third direction are perpendicular to each other two by two. Here, it may be defined that the first direction is a Z-axis direction, the second direction is an X-axis direction, and the third direction is a Y-axis direction.
Fig. 3B is a cross-sectional view of the grid-shaped etched trench provided in the embodiment of the present application along the first direction, and fig. 3C is a top view of the grid-shaped etched trench provided in the embodiment of the present application, and it can be seen from fig. 3B and 3C that, along the Z-axis direction, the wafer 30 is partially etched with the first surface 30-1 of the wafer as an etching starting point, so as to form a grid-shaped etched trench 31 composed of a plurality of silicon pillars 301, where each silicon pillar 301 is located at an intersection point in the grid, and an equal gap exists between any two adjacent silicon pillars. In the embodiment of the present application, each of the silicon pillars 301 has a first predetermined thickness a in the Z-axis direction, and the first predetermined thickness is smaller than the initial thickness B of the wafer; the first surface 30-1 of the wafer is any surface of the wafer along the Z-axis direction. The wafer also includes a second side 30-2 opposite the first side 30-1.
Here, the wafer may be etched using a dry etching process, for example, a plasma etching process or a reactive ion etching process. It should be noted that, in the embodiment of the present application, the etching on the wafer is a partial etching performed in the thickness direction of the wafer, that is, the wafer is not etched through in the etching process.
And S3012, depositing an insulating material in the grid-shaped etched grooves to form an insulating layer surrounding each silicon pillar.
In the embodiment of the present application, the insulating material may be a silicon dioxide material or other insulating materials. FIG. 3D is a top view of an embodiment of the present invention, showing an insulating layer formed in a grid-like etched trench 31, and an insulating material SiO is deposited in the grid-like etched trench 312The periphery of each silicon pillar 301 is filled with an insulating material SiO2 An insulating layer 32 is formed.
It should be noted that during the actual deposition of the insulating material, the insulating material SiO is2The silicon pillars 301 are covered with a layer of silicon oxide (SiO), which is a Chemical Mechanical Polishing (CMP) process used to polish and remove the excess SiO after deposition2To expose the surface of the silicon pillar 301.
And S3013, etching the silicon column and the insulating layer to form the transistor column with the exposed side wall, and obtaining the transistor forming area.
In some embodiments, the etching the silicon pillar and the insulating layer to form the transistor pillar with an exposed sidewall includes: and taking the edge position of the silicon column as an etching starting point, carrying out partial etching treatment on the silicon column and the insulating layer along a first direction, removing the silicon column and the insulating layer which have preset sizes in a second direction and have a first preset thickness in the first direction, forming the transistor column with an exposed side wall, and forming an etching groove.
Fig. 3E is a top view of the transistor column provided in the embodiment of the present application, as shown in fig. 3E, with the edge position of the silicon column as an etching starting point, along the X-axis direction, it is right that the silicon column and the insulating layer are etched to remove the silicon column and the insulating layer which have the predetermined size C in the X-axis direction and have the first predetermined thickness a in the Z-axis direction, thereby forming the transistor column 302 and an etching groove 303, and further forming the transistor forming region 30', wherein the transistor column has an exposed sidewall 302-1. In this embodiment, the predetermined dimension C is smaller than the initial dimension D of the silicon pillar 301 in the X-axis direction.
It should be noted that many transistors are formed on one wafer, and therefore, there are a plurality of transistor forming regions in one wafer, and in the embodiment of the present application, for convenience of description, only a limited number of transistor forming regions are exemplarily shown.
Referring to fig. 3F and 3G, step S302 is performed to sequentially form a gate oxide layer and a gate on the sidewall of each transistor pillar.
In some embodiments, before performing step S302, the method for manufacturing a transistor further includes:
and step S10, depositing a first isolation layer at the bottom of the etched groove.
Here, the material of the first isolation layer includes, but is not limited to, any one of the following: silicon nitride, silicon oxynitride, silicon carbide or silicon dioxide.
Next, a subsequent forming process will be described by taking a transistor column on a wafer as an example. Fig. 3F is a schematic structural diagram of forming a first isolation layer according to an embodiment of the present disclosure, and as shown in fig. 3F, a first isolation layer 304 is deposited at the bottom of the etched groove (not shown in fig. 3F). Here, the first isolation layer may be deposited by any suitable deposition process.
In some embodiments, after forming the first isolation layer, the above-mentioned process of forming a gate oxide layer and a gate electrode is performed, and the process of forming a gate oxide layer and a gate electrode on the sidewall of each of the transistor pillars in turn includes the following steps:
step S3021, forming an initial gate oxide layer on the sidewall of the transistor column by in-situ oxidation.
Fig. 3G is a schematic structural diagram of forming an initial gate oxide layer according to an embodiment of the present invention, as shown in fig. 3G and fig. 3F, where the exposed sidewall 302-1 'of the transistor pillar 301 may be oxidized in situ by heating or pressing to form an initial gate oxide layer 305'.
And S3022, depositing a polysilicon material in the etching groove to form a polysilicon layer.
Here, the polysilicon Layer may be formed by depositing a polysilicon material in the etched groove after the first isolation Layer 304 is deposited by a process of Chemical Vapor Deposition (PVD), Physical Vapor Deposition (PVD), or Atomic Layer Deposition (ALD).
Step S3023, in the first direction, simultaneously performing etching processing on the initial gate oxide layer and the polysilicon layer, and removing a part of the initial gate oxide layer and the polysilicon layer in thickness in the first direction to form the gate oxide layer and the gate.
Fig. 3H is a schematic structural diagram of forming a gate oxide layer and a gate according to an embodiment of the present disclosure, and as shown in fig. 3H, the formed initial gate oxide layer and the polysilicon layer are partially etched along the Z-axis direction at the same time, so as to obtain a gate oxide layer 305 and a gate 306. In the embodiment of the present application, a dry etching technique may be adopted to etch the initial gate oxide layer and the polysilicon layer.
In some embodiments, after forming the gate oxide layer and the gate, the method of manufacturing the transistor further includes:
step S11, depositing a second isolation layer in the etching groove, wherein the second isolation layer is located in a projection area of the transistor column in the second direction, and the dimension of the second isolation layer in the third direction is equal to the dimension of the transistor column in the third direction.
In an embodiment of the present application, the third direction is perpendicular to the second direction and the first direction in pairs. It should be noted that, in other embodiments, the third direction may not be perpendicular to the second direction, and an included angle between the third direction and the second direction may be any angle.
Here, the material of the second isolation layer includes, but is not limited to, any one of the following: silicon nitride, silicon oxynitride, silicon carbide, or silicon dioxide; the second isolation layer is the same or different in material from the first isolation layer.
Fig. 3I is a schematic structural diagram of forming a second isolation layer according to an embodiment of the present disclosure, as shown in fig. 3I, the second isolation layer 307 is located in a projection region of the wafer column 302 in the X-axis direction, and a dimension of the second isolation layer in the Y-axis direction is equal to a dimension of the transistor column in the Y-axis direction.
Referring next to fig. 3J, step S303 is performed to form a source at the first end of the transistor pillar.
Here, the first end of the transistor column is an end of the transistor column in the Z-axis direction. Fig. 3J is a schematic structural diagram of forming a source according to an embodiment of the present disclosure, and as shown in fig. 3J, a source 308 is formed by performing ion implantation on a first end of a transistor column.
In some embodiments, the shape of the source electrode comprises any one of: square, semi-circular, triangular or any polygon.
In some embodiments, before performing step S304, the method for manufacturing a transistor further includes:
and step S12, thinning the wafer from the second surface of the wafer until the first isolation layer and the second end of the transistor column are exposed.
With continued reference to fig. 3J, the second side 30-2 of the wafer is opposite the first side 30-1 of the wafer. In the embodiment of the present application, before thinning the second surface of the wafer, the first surface of the wafer needs to be fixed on a supporting structure, so as to prevent the structure of the transistor from being damaged when thinning the second surface 30-2 of the wafer.
The first end and the second end are two ends of the transistor column opposite to each other in the first direction. Fig. 3K is a schematic structural diagram of the transistor after thinning the second surface of the wafer according to the embodiment of the present application, and as shown in fig. 3K, the second surface of the wafer is thinned to expose the first isolation layer 304 and the second end 309' of the transistor column.
Next, referring to fig. 3L, step S304 is performed to form a drain at the second end of the transistor pillar.
Fig. 3L is a schematic structural diagram of forming a drain according to an embodiment of the present disclosure, and as shown in fig. 3L, the drain 309 is formed by performing ion implantation on the second end 309' of the transistor column.
In some embodiments, the shape of the drain electrode comprises any one of: square, semi-circular, triangular or any polygon.
Fig. 3M and 3N are schematic structural diagrams of an alternative pillar-shaped transistor provided in an embodiment of the present application, where, as shown in fig. 3M, the cross-sectional shapes of the source and the drain of the pillar-shaped transistor are both semi-circular, and as shown in fig. 3N, the cross-sectional shapes of the source and the drain of the pillar-shaped transistor are both triangular.
In the embodiments of the present application, the positions of the source and the drain may be interchanged, and the shapes of the source and the drain of the pillar-shaped transistor formed in the embodiments of the present application may be the same or different.
With continued reference to fig. 3L, in the present embodiment, after forming the source and the drain, the transistor pillar between the source and the drain forms a channel region 310 of the transistor.
According to the column-shaped transistor formed by the column-shaped transistor manufacturing method provided by the embodiment of the application, the source electrode and the drain electrode are respectively positioned at the first end and the second end of the channel region in the first direction, and the first direction is the thickness direction of a wafer for forming the channel region, so that the area of the transistor is greatly reduced.
In some embodiments, when the pillar-shaped transistor provided in the embodiments of the present application is applied to a memory, since the drain and the source of the pillar-shaped transistor are located on different surfaces of a wafer, different structures to which the source and the drain of the memory are connected can be respectively designed in two surfaces of the wafer, thereby simplifying a circuit layout inside the memory and reducing the process difficulty of manufacturing the memory.
An embodiment of the present application provides a semiconductor device, and fig. 4A is an alternative schematic structural diagram of the semiconductor device provided in the embodiment of the present application, and as shown in fig. 4A, the semiconductor device 40 includes: at least one memory cell, a word line 402, and a bit line 403.
Wherein each memory cell comprises at least one pillar shaped transistor 401, the pillar shaped transistor 401 comprising at least a gate G, a source S and a drain D.
The pillar transistors 401 further include channel regions, and the source of each pillar transistor is located at a first end of the channel region; the drain electrode of each cylindrical transistor is positioned at the second end of the channel region; the first end and the second end are two ends of the channel region opposite to each other in a first direction, and the first direction is a thickness direction of a wafer forming the channel region. That is, the pillar-shaped transistor 401 in the embodiment of the present application has a vertical channel, and the source and the drain of the pillar-shaped transistor 401 are located at both ends of the vertical channel, respectively.
In this embodiment, the word line 402 is connected to the gate G of the pillar transistor 401, and the word line is used to provide a word line voltage and control the pillar transistor 401 to turn on or off through the word line voltage.
The bit line 403 is connected to the source S or the drain D of the pillar transistor 401, and is used to perform a read or write operation on the memory cell when the pillar transistor is turned on.
In some embodiments, when the source S of the pillar transistor 401 is connected to the bit line 403, the drain of the pillar transistor is grounded; when the drain of the pillar transistor 401 is connected to a bit line 403, the source of the pillar transistor is grounded.
The semiconductor device provided by the embodiment of the application comprises various types of memories. For example, NAND Flash (Flash), Nor Flash, DRAM, Static Random Access Memory (SRAM), and Phase-Change Memory (PCM).
In some embodiments, when the semiconductor device is a DRAM, the memory cell further includes: a storage capacitor.
As shown in fig. 4B, which is an alternative structural diagram of the DRAM memory cell provided in the embodiment of the present application, it can be seen that in the DRAM memory cell 40', one end of a storage capacitor 404 is connected to the drain or the source of the pillar transistor 401, the other end of the storage capacitor 404 is grounded, and the storage capacitor 404 is used for storing data written into the memory cell.
In some embodiments, when the semiconductor device is a PCM, the memory cell further includes: and (4) an adjustable resistor.
As shown in fig. 4C, which is an alternative structural diagram of the PCM memory cell according to the embodiment of the present application, it can be seen that in the PCM memory cell 40 ", an adjustable resistor 405 is connected between the bit line 403 and the source of the pillar transistor 401, or the adjustable resistor 405 is connected between the bit line 403 and the drain of the pillar transistor 401, and the adjustable resistor 405 is used for adjusting the state of data stored in the memory cell through a bit line voltage provided by the bit line.
In some embodiments, when the semiconductor device includes a plurality of the memory cells, the semiconductor device is NAND Flash or Nor Flash. When the memory units are connected in parallel, the semiconductor device is Nor Flash; when a plurality of memory units are connected in series, the semiconductor device is NAND Flash.
In the embodiments of the present application, some common semiconductor devices are only exemplified, the scope of protection of the present application is not limited thereto, and any semiconductor device including the pillar-shaped transistor provided in the embodiments of the present application falls within the scope of protection of the present application.
In the embodiment of the application, the transistor structure of the semiconductor device is designed into a novel structure with a vertical channel, so that the area of the memory cell is reduced, and the storage density of the memory cell is improved. Meanwhile, in the column-shaped transistor in the embodiment of the present application, the source and the drain are located at the upper and lower ends of the vertical channel region, so that in the formation process of the semiconductor device, bit lines or other structures may be respectively disposed on the vertical two sides of the channel region. For example, for a DRAM, bit lines and capacitors of a DRAM memory cell may be disposed on two sides of the same wafer, respectively, so that circuit arrangements of word lines, bit lines, and capacitors may be simplified, and difficulty in manufacturing a semiconductor device may be reduced.
An embodiment of the present application provides a method for forming a semiconductor device, and fig. 5 is an optional schematic structural diagram of the method for forming a semiconductor device provided in the embodiment of the present application, as shown in fig. 5, the method includes the following steps:
step S501, forming at least one memory unit, wherein each memory unit at least comprises: a pillar-shaped transistor; the pillar-shaped transistor includes: a gate, a source and a drain.
And step S502, forming a word line, wherein the word line is connected with the grid electrode of the cylindrical transistor and is used for providing word line voltage and controlling the cylindrical transistor to be switched on or switched off through the word line voltage.
And S503, forming a bit line, wherein the bit line is connected with the source electrode or the drain electrode of the cylindrical transistor, and the bit line is used for performing reading or writing operation on the memory unit when the cylindrical transistor is conducted.
In some embodiments, the pillar shaped transistors in the memory cells are formed by:
step S5011, removing silicon in the first surface partial region of the first wafer by a certain thickness (corresponding to the first predetermined thickness in the above embodiment) through an etching process, forming a grid-shaped trench (corresponding to the grid-shaped etched trench in the above embodiment) with a silicon pillar in the middle, filling silicon dioxide (corresponding to the insulating layer in the above embodiment) in the trench, exposing the surface of the silicon pillar through chemical mechanical polishing, and finally removing the silicon pillar by etching to expose the sidewall of the silicon pillar (corresponding to the process of forming the transistor pillar in the above embodiment).
In step S5012, silicon nitride is formed at the bottom of the trench to serve as a bottom isolation (Spacer) structure (corresponding to the formation of the first isolation layer in the above embodiment).
In step S5013, silicon oxide is formed on the sidewall of the trench by in-situ growth to serve as a gate oxide layer (corresponding to the initial gate oxide layer formed in the above embodiment).
Step S5014, filling polysilicon in the trench (corresponding to the formation of the polysilicon layer in the above embodiment), removing the polysilicon on the top by a certain depth through etching, and then removing the silicon oxide on the top without a leak (corresponding to step S3023 in the above embodiment).
In step S5015, silicon nitride is formed on the top of the trench to serve as a top isolation structure (corresponding to the formation of the second isolation layer in the above-mentioned embodiment).
Step S5016, forming a source terminal in the transistor region (corresponding to the first end of the transistor column in the above embodiment) reserved in step S5011 by ion implantation.
Step S5017, forming a subsequent corresponding structure on the first surface of the first wafer through various processes; then, the first wafer is bonded to the second wafer, and finally, the silicon on the back surface of the first wafer is thinned until the bottom isolation structure and the second surface of the first wafer (corresponding to the second end of the transistor pillar in the above embodiment) are exposed.
Here, the subsequent corresponding structure includes: forming bit lines, forming resistors, or forming capacitors. Various logic circuits, sensors and other elements are arranged in the second wafer, and the second wafer and the first wafer are bonded to form a memory together.
In some embodiments, the wafer bonding process is performed before the back side silicon thinning process, and the second wafer provides a supporting function for the first wafer during the thinning process, so as to prevent the first wafer from being damaged during the thinning process.
In step S5018, a drain is formed on the second surface of the first wafer at a position opposite to the source (corresponding to the second end of the transistor column) in step S5016 by ion implantation.
Step S5019, finally, a subsequent corresponding structure is formed on the second surface of the first wafer.
Here, the subsequent corresponding structure includes: forming bit lines, forming resistors, or forming capacitors.
According to the method for forming the semiconductor device, the channel of the formed columnar transistor is in the vertical direction, and the horizontal section of the columnar transistor can be rectangular (square), semicircular, triangular and any polygon. In the semiconductor device in the embodiment of the application, the source electrode and the drain electrode of the cylindrical transistor can be interchanged, and the source electrode and the drain electrode can be processed on two surfaces of the same wafer respectively, so that the patterns of the source electrode and the drain electrode can be different.
In the embodiment of the application, the word lines and the bit lines are realized by forming metal lines at preset word line positions and preset bit line positions. The metal line includes, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof.
In the embodiment of the application, the structure of the transistor of the semiconductor device is designed into a novel transistor structure with a vertical channel, so that the area of the memory cell is reduced, and the storage density of the memory cell is improved. Meanwhile, in the cylindrical transistor in the embodiment of the application, the source electrode and the drain electrode are positioned at the upper end and the lower end of the vertical channel region, so that in the forming process of the semiconductor device, the bit line or other structures can be respectively arranged in two opposite surfaces of the wafer by combining the wafer bonding and the back silicon thinning technology. For example, for a DRAM, bit lines and capacitors of a DRAM memory cell may be disposed on two sides of the same wafer, respectively, so that circuit arrangements of word lines, bit lines, and capacitors may be simplified, and difficulty in manufacturing a semiconductor device may be reduced.
In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in a non-target manner. The above-described device embodiments are merely illustrative, for example, the division of the unit is only a logical functional division, and there may be other division ways in actual implementation, such as: multiple units or components may be combined, or may be integrated into another system, or some features may be omitted, or not implemented. Additionally, the various components shown or discussed are coupled or directly coupled to each other.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed on a plurality of network units; some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
The features disclosed in the several method or apparatus embodiments provided in the present application may be combined arbitrarily, without conflict, to arrive at new method embodiments or apparatus embodiments.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.

Claims (13)

1. A method of fabricating a pillar shaped transistor, the method comprising:
providing a wafer, wherein the wafer is provided with a plurality of transistor forming areas, each transistor forming area is provided with a transistor column, and each transistor column is provided with an exposed side wall;
sequentially forming a grid oxide layer and a grid on the side wall of each transistor column;
forming a source electrode at a first end of the transistor column;
forming a drain electrode at a second end of the transistor column, wherein the first end and the second end are two opposite ends of the transistor column in a first direction, and the first direction is the thickness direction of the wafer; the transistor column between the source and the drain constitutes a channel region of the transistor.
2. The method of claim 1, wherein the transistor forming region further has an insulating layer surrounding other sidewalls of the transistor column; the transistor forming region is formed by:
partially etching the wafer by taking the first surface of the wafer as an etching starting point along the first direction to form a grid-shaped etching groove consisting of a plurality of silicon columns, wherein each silicon column has a first preset thickness, and the first preset thickness is smaller than the initial thickness of the wafer; the first surface of the wafer is any one surface of the wafer along the first direction;
depositing an insulating material in the grid-shaped etching groove to form an insulating layer surrounding each silicon pillar;
and etching the silicon column and the insulating layer to form the transistor column with an exposed side wall, and obtaining the transistor forming area.
3. The method of claim 2, wherein said etching said silicon pillar and said insulating layer to form said transistor pillar with an exposed said sidewall comprises:
taking the edge position of the silicon column as an etching starting point, carrying out partial etching treatment on the silicon column and the insulating layer along the first direction, removing the silicon column and the insulating layer which have preset sizes in the second direction and have the first preset thickness in the first direction, forming the transistor column with an exposed side wall, and forming an etching groove; wherein the preset dimension is smaller than the initial dimension of the silicon pillar in the second direction; the second direction is perpendicular to the first direction.
4. The method of claim 3, wherein prior to forming the gate oxide layer and the gate, the method further comprises:
depositing and forming a first isolating layer at the bottom of the etching groove;
correspondingly, the forming a gate oxide layer and a gate on the sidewall of each transistor column in turn includes:
forming an initial gate oxide layer on the sidewall of the transistor column by in-situ oxidation;
depositing a polysilicon material in the etching groove to form a polysilicon layer;
and simultaneously etching the initial grid oxide layer and the polycrystalline silicon layer in the first direction, and removing the initial grid oxide layer and the polycrystalline silicon layer with partial thickness in the first direction to form the grid oxide layer and the grid.
5. The method of claim 4, wherein after forming the gate oxide layer and the gate, the method further comprises:
and depositing to form a second isolation layer in the etching groove, wherein the second isolation layer is positioned in a projection area of the transistor column in the second direction, and the size of the second isolation layer in the third direction is equal to that of the transistor column in the third direction.
6. The method of claim 2, wherein prior to forming the drain, the method further comprises:
thinning the wafer from the second surface of the wafer until the first isolation layer and the second end of the transistor column are exposed; wherein the second side of the wafer is a side opposite to the first side of the wafer.
7. The method of claim 1, wherein the source and the drain are the same or different in shape;
the shape of the source electrode and the drain electrode includes any one of: square, semi-circular, triangular or any polygon.
8. A pillar shaped transistor, characterized in that the transistor comprises:
a channel region;
a source electrode positioned at a first end of the channel region;
the drain electrode is positioned at a second end of the channel region, wherein the first end and the second end are two opposite ends of the channel region in a first direction respectively, and the first direction is the thickness direction of a wafer forming the channel region;
a gate electrode positioned at either side of the channel region and corresponding to the channel region;
and the grid oxide layer is positioned between the channel region and the grid.
9. A method of forming a semiconductor device, the method comprising:
forming at least one memory cell, wherein each of the memory cells comprises at least: a pillar-shaped transistor; the pillar-shaped transistor includes: a gate, a source and a drain; the pillar-shaped transistor is manufactured by the manufacturing method of the pillar-shaped transistor provided in any one of the above claims 1 to 7;
forming a word line, wherein the word line is connected with the grid electrode of the cylindrical transistor, and is used for providing a word line voltage and controlling the cylindrical transistor to be switched on or switched off through the word line voltage;
and forming a bit line connected with the source electrode or the drain electrode of the cylindrical transistor, wherein the bit line is used for performing reading or writing operation on the memory cell when the cylindrical transistor is conducted.
10. A semiconductor device, comprising: at least one memory cell, a word line, and a bit line, each of the memory cells comprising at least: the pillar shaped transistor of claim 8; the pillar-shaped transistor includes at least: a gate, a source and a drain;
the word line is connected with the grid electrode of the cylindrical transistor and used for providing a word line voltage and controlling the cylindrical transistor to be switched on or switched off through the word line voltage;
the bit line is connected with the source electrode or the drain electrode of the cylindrical transistor, and the bit line is used for performing reading or writing operation on the memory cell when the cylindrical transistor is conducted.
11. The semiconductor device of claim 10, wherein the memory cell further comprises: a storage capacitor;
one end of the storage capacitor is connected with the drain electrode or the source electrode of the cylindrical transistor, the other end of the storage capacitor is grounded, and the storage capacitor is used for storing data written into the memory unit.
12. The semiconductor device of claim 10, wherein the memory cell further comprises: an adjustable resistor;
the adjustable resistor is connected between the bit line and the source of the pillar-shaped transistor, or between the bit line and the drain of the pillar-shaped transistor, and the adjustable resistor is used for adjusting the state of data stored in the memory cell through a bit line voltage provided by the bit line.
13. The semiconductor device according to claim 10, wherein when the semiconductor device includes a plurality of the memory cells, the plurality of the memory cells are connected in parallel or in series.
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