CN110931558A - Double vertical channel transistor, integrated circuit memory and preparation method thereof - Google Patents
Double vertical channel transistor, integrated circuit memory and preparation method thereof Download PDFInfo
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- 230000015654 memory Effects 0.000 title claims abstract description 53
- 238000002360 preparation method Methods 0.000 title abstract description 13
- 238000002955 isolation Methods 0.000 claims abstract description 187
- 238000000034 method Methods 0.000 claims abstract description 129
- 230000008569 process Effects 0.000 claims abstract description 104
- 239000000758 substrate Substances 0.000 claims description 95
- 239000004065 semiconductor Substances 0.000 claims description 81
- 230000009977 dual effect Effects 0.000 claims description 60
- 150000002500 ions Chemical class 0.000 claims description 31
- 238000004519 manufacturing process Methods 0.000 claims description 30
- 238000005530 etching Methods 0.000 claims description 23
- 238000011049 filling Methods 0.000 claims description 19
- 238000005468 ion implantation Methods 0.000 claims description 19
- 238000000151 deposition Methods 0.000 claims description 5
- 239000007943 implant Substances 0.000 claims description 3
- 230000008878 coupling Effects 0.000 claims 1
- 238000010168 coupling process Methods 0.000 claims 1
- 238000005859 coupling reaction Methods 0.000 claims 1
- 230000000694 effects Effects 0.000 abstract description 6
- 230000009286 beneficial effect Effects 0.000 abstract description 5
- 239000010410 layer Substances 0.000 description 225
- 238000005229 chemical vapour deposition Methods 0.000 description 21
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 17
- 229920005591 polysilicon Polymers 0.000 description 17
- 229910052751 metal Inorganic materials 0.000 description 16
- 239000002184 metal Substances 0.000 description 16
- 239000000463 material Substances 0.000 description 15
- 230000003647 oxidation Effects 0.000 description 11
- 238000007254 oxidation reaction Methods 0.000 description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 238000000231 atomic layer deposition Methods 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- 238000005240 physical vapour deposition Methods 0.000 description 8
- 229910052721 tungsten Inorganic materials 0.000 description 8
- 239000010937 tungsten Substances 0.000 description 8
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- 230000006870 function Effects 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- 239000004020 conductor Substances 0.000 description 5
- 230000007547 defect Effects 0.000 description 5
- 238000001312 dry etching Methods 0.000 description 5
- 238000009713 electroplating Methods 0.000 description 5
- 238000011065 in-situ storage Methods 0.000 description 5
- 238000003860 storage Methods 0.000 description 5
- 239000000126 substance Substances 0.000 description 5
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 5
- 238000009279 wet oxidation reaction Methods 0.000 description 5
- 244000126211 Hericium coralloides Species 0.000 description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- WTEOIRVLGSZEPR-UHFFFAOYSA-N boron trifluoride Chemical compound FB(F)F WTEOIRVLGSZEPR-UHFFFAOYSA-N 0.000 description 4
- 239000012212 insulator Substances 0.000 description 4
- 230000010354 integration Effects 0.000 description 4
- 150000004767 nitrides Chemical class 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 229910052709 silver Inorganic materials 0.000 description 3
- 239000004332 silver Substances 0.000 description 3
- 239000002356 single layer Substances 0.000 description 3
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 3
- -1 tungsten nitride Chemical class 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- 229910015900 BF3 Inorganic materials 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910010038 TiAl Inorganic materials 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 229910052787 antimony Inorganic materials 0.000 description 2
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 230000002349 favourable effect Effects 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 229910003481 amorphous carbon Inorganic materials 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7853—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
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- H—ELECTRICITY
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/36—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being a FinFET
Abstract
The invention provides a double vertical channel transistor, an integrated circuit memory and a preparation method thereof, wherein a vertical fin is provided with a first groove extending along a first direction, a first source/drain region is formed in the fin at the top of two sides of the first groove, a second source/drain region is formed in the fin at the bottom of the first groove, a first grid structure is filled in the first groove and extends along the first direction, and an embedded lead is filled in a second groove at the side wall of the vertical fin extending along a second direction, so that the first source/drain regions at two sides of the first groove and the second source/drain region at the bottom of the first groove form double vertical L-shaped channels respectively, thereby being beneficial to increasing the effective channel length and overcoming the short channel effect; and because the second source/drain region and the electric connection embedded type lead thereof are positioned at the bottom of the transistor and do not need to be directly led out from the upper surface, the isolation at the periphery of the transistor is easier to form, thereby being beneficial to reducing the area of the device, simplifying the process and improving the performance.
Description
Technical Field
The invention relates to the technical field of integrated circuit manufacturing, in particular to a double-vertical-channel transistor, an integrated circuit memory and a preparation method thereof.
Background
A Vertical gate-around transistor (SGT) with embedded bit lines uses an increased isolation rule to reduce the difficulty of manufacturing shallow trench isolation, and the process includes a long and redundant embedded bit line process step, a dielectric layer (SOD) spin-coating process step, and a process step of defining the gate length of the transistor by metal and N-type doped polysilicon, which results in a significant reduction in the threshold voltage stability of the memory array, and a reduction in the threshold voltage (Vth) change with a longer channel length cannot be implemented due to the limitation of the Vertical dimension.
Therefore, a new dual vertical channel transistor, an integrated circuit memory and a method for fabricating the same are needed, which can simplify the process and improve the electrical performance and memory density of the device.
Disclosure of Invention
The invention aims to provide a double vertical channel transistor, an integrated circuit memory and a preparation method thereof, which can simplify the process and improve the electrical property and the storage density of a device.
In order to achieve the above object, the present invention provides a dual vertical channel transistor comprising:
the semiconductor substrate is provided with a vertical fin extending along a second direction, the vertical fin is provided with a first groove extending along a first direction, a second source/drain region is formed in the fin at the bottom of the first groove, and a first source/drain region is formed in the fin at the top of the side wall of the first groove; and
and the first gate structure is filled in the first trench and extends along the first direction, the first gate structure is positioned above the second source/drain region, and the side wall of the first gate structure and the exposed side wall of the first source/drain region of the first trench are at least partially overlapped in space in height.
Optionally, the semiconductor substrate further has an isolation trench, the isolation trench extends along the first direction and exposes a sidewall of the vertical fin along the first direction, so as to implement device isolation between the dual vertical channel transistor and an adjacent element, and a second gate structure is filled on an inner surface of the isolation trench and used for accessing a substrate voltage to the dual vertical channel transistor.
Optionally, an isolation region is further disposed in the bottom of the vertical fin, the isolation region extends along the second direction, a portion of the isolation region extending at the bottom of the first trench is located below the second source/drain region, and portions of the isolation region extending at two sides of the first trench are at least partially overlapped with the second source/drain region in height.
Optionally, the first gate structure includes a gate dielectric layer, a gate electrode layer and a gate isolation layer, the gate dielectric layer covers the side wall and the bottom surface of the first trench, the gate electrode layer is filled in the first trench with the gate dielectric layer, the top surface of the gate electrode layer is lower than the top surface of the first source/drain region, and the gate isolation layer fills the first trench above the gate electrode layer.
Optionally, the semiconductor substrate further has a second trench, the second trench extends along the second direction and exposes the sidewall of the vertical fin, an end of the first trench along the first direction extends to the second trench so that the first trench and the second trench are connected on the sidewall of the second trench, and a bottom surface of the first trench is higher than a bottom surface of the second trench so that the sidewall of the fin at the bottom of the first trench including the second source/drain region is exposed in the second trench, the second trench has a buried conductive line embedded therein, and an end of the first trench in the first direction extends to the sidewall of the buried conductive line so that the buried conductive line and the second source/drain region are electrically connected.
Optionally, the dual vertical channel transistor further includes a first dielectric layer, the first dielectric layer is located in the second trench, the buried conductive line is located on the first dielectric layer, and a portion of the first dielectric layer on the bottom surface of the buried conductive line extends to a boundary with the second source/drain region and makes the bottom surface of the buried conductive line not lower than the bottom surface of the second source/drain region.
Optionally, the dual vertical channel transistor further includes a second dielectric layer covering the second trench above the buried conductive line and exposing a portion of the first gate structure extending from the first trench into the second trench.
Optionally, the dual vertical channel transistor further comprises a conductive contact structure formed in the second trench and disposed between the buried conductive line and the second source/drain region, one sidewall of the conductive contact structure is in surface contact with a sidewall of the second source/drain region, the other sidewall of the conductive contact structure is in surface contact with a sidewall of the buried conductive line, and a bottom surface of the conductive contact structure is insulated and isolated from the surface of the semiconductor substrate at the bottom of the second trench.
The invention also provides a preparation method of the double vertical channel transistor, which comprises the following steps:
providing a semiconductor substrate, and etching the semiconductor substrate along a first direction and a second direction respectively to form a vertical fin extending along the second direction and a second groove, wherein the second groove exposes a side wall of the vertical fin extending along the second direction, a first groove extending along the first direction is arranged in the vertical fin, an end part of the first groove along the first direction extends to the second groove, so that the first groove and the second groove are communicated on the side wall of the second groove, and the bottom surface of the first groove is higher than the bottom surface of the second groove;
forming an embedded conductive line in the second trench, the embedded conductive line extending along a second direction and electrically connected to the fins at the bottom of the first trench;
forming a first source/drain region and a second source/drain region in one step by adopting the same ion implantation process, wherein the first source/drain region is formed in the fin at the top of the side wall of the first groove, and the second source/drain region is formed in the fin at the bottom of the first groove; and the number of the first and second groups,
and filling a first gate structure in the first groove above the second source/drain region.
Optionally, before forming the first source/drain region and the second source/drain region, a trap ion implantation process is first used to implant ions of an inverse type to the second source/drain region into the bottom of the vertical fin to form an isolation region, the isolation region extends along the second direction, a portion of the isolation region extending at the bottom of the first trench is located below the second source/drain region, and portions of the isolation region extending at two sides of the first trench are at least partially overlapped with the second source/drain region in height in space.
Optionally, before forming the embedded conductive line, a first dielectric layer is filled in the second trench, the embedded conductive line is located on the first dielectric layer, and the embedded conductive line is insulated and isolated from the semiconductor substrate by the first dielectric layer.
Optionally, the step of forming the first gate structure includes: depositing a second dielectric layer on the surface of the semiconductor substrate with the first source/drain region and the second source/drain region, wherein the second dielectric layer fills the second groove above the embedded type conducting wire; etching the second dielectric layer to expose the side wall and the bottom surface of the first groove above the second source/drain region, and forming a gate dielectric layer on the side wall and the bottom surface of the first groove; filling a gate electrode layer in the first groove with the gate dielectric layer, wherein the side wall of the gate electrode layer is at least partially overlapped with the side wall of the first source/drain region in space in height; and; and filling a gate isolation layer in the first groove above the gate electrode layer, wherein the gate isolation layer fills the first groove above the gate electrode layer.
Optionally, while the semiconductor substrate is etched along a first direction to form the first trench, an isolation trench is further formed in the semiconductor substrate, the isolation trench extends along the first direction and exposes a sidewall of the vertical fin along the first direction, so as to achieve device isolation between the dual vertical channel transistor and an adjacent element; and filling a first gate structure in the first trench above the second source/drain region, and simultaneously filling a second gate structure in the isolation trench.
The present invention also provides an integrated circuit memory comprising: a plurality of double vertical channel transistors according to the present invention, all of which are arranged in a cell row and a cell column in an array along a first direction and a second direction; a second trench extending along the second direction is arranged between two adjacent cell columns, the second trench exposes sidewalls of vertical fins of all the double vertical channel transistors on the two adjacent cell columns extending along the second direction, a bit line of the integrated circuit memory is filled in the second trench, and the bit line is electrically connected with second source/drain regions of all the double vertical channel transistors on the cell column on one side of the second trench; the end of the first groove of all the double vertical channel transistors on each unit row along the first direction extends to the second groove and is communicated with the second groove on the side wall of the second groove, so that the first gate structures of all the double vertical channel transistors on each unit row are connected into a whole to be used as a word line of the integrated circuit memory; the isolation groove is used for exposing all the vertical fins of the double vertical channel transistors on the adjacent two unit rows along the outer side wall of the first direction and is used for realizing isolation between the double vertical channel transistors on the adjacent two unit rows, the isolation groove and the first groove are formed by adopting the same process, the isolation groove is filled with the second grid structures of the double vertical channel transistors on the corresponding side, the second grid structures of the double vertical channel transistors on the corresponding same side in the isolation groove are connected into a whole and used as a virtual word line of the integrated circuit memory, and the virtual word line and the word line are formed in the same process.
The invention also provides a preparation method of the integrated circuit memory, which comprises the following steps: preparing a plurality of double vertical channel transistors by adopting the preparation method of the double vertical channel transistors, wherein all the double vertical channel transistors are arranged in an array along a first direction and a second direction according to unit rows and unit columns, and an isolation groove is formed in the semiconductor substrate while the first groove is formed, so that the isolation between the double vertical channel transistors on two adjacent unit rows is realized, and a first grid structure is filled in the first groove above the second source/drain region, and a second grid structure is also filled in the isolation groove; a second trench extending along the second direction is arranged between two adjacent cell columns, the second trench exposes sidewalls of all vertical fins of the dual vertical channel transistors on the two adjacent cell columns extending along the second direction, a bit line of the integrated circuit memory is filled in the second trench, and the bit line is electrically connected with second source/drain regions of all the dual vertical channel transistors on the cell column on one side of the second trench; the end of the first trench of all the double vertical channel transistors on each cell row along the first direction extends to the second trench and is communicated with the second trench on the side wall of the second trench, so that the first gate structures of all the double vertical channel transistors on each cell row are connected into a whole to be used as a word line of the integrated circuit memory; the isolation trench exposes the outer side wall of the vertical fin along the first direction of all the double vertical channel transistors on the two adjacent unit rows, and the second gate structures of the double vertical channel transistors corresponding to the same side in the isolation trench are connected into a whole to be used as a virtual word line of the integrated circuit memory.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
1. the double vertical channel transistor of the invention has a vertical fin extending along a second direction, wherein the vertical fin has a first trench extending along the first direction, a first source/drain region thereof is formed in the fin at the top of two sides of the first trench, a second source/drain region thereof is formed in the fin at the bottom of the first trench, a first gate structure thereof is filled in the first trench and extends along the first direction, a buried conductive line thereof is filled in the second trench at the side wall of the vertical fin extending along the second direction, thereby an L-shaped channel is formed between the first source/drain region at two sides of the first trench and the second source/drain region at the bottom of the first trench respectively, i.e. a double vertical L-shaped channel is formed, and relative to a planar transistor, the double vertical L-shaped channels occupy the same substrate area, the effective channel length can be increased by increasing the height of the semiconductor column between the first source/drain region and the second source/drain region, so that the short channel effect is overcome, and the realization of smaller characteristic size is facilitated; and because the second source/drain region of the double vertical L-shaped channel is positioned at the bottom of the transistor, the second source/drain region does not need to be directly led out from the surface of the transistor, so that the isolation at the periphery of the transistor is easier to form, the area of the device is reduced under the condition of the same size, and further higher integration level of the device can be provided in a given space amount. Furthermore, an isolation groove is formed outside the outer side wall of the vertical fin along the first direction, a second grid structure (namely a virtual grid structure) is formed in the isolation groove, and therefore a double-grid double-vertical-channel transistor is formed.
2. The invention relates to a preparation method of a double vertical channel transistor, which comprises the steps of firstly etching a semiconductor substrate along a first direction and a second direction respectively to form a vertical fin with a first groove extending along the second direction and a second groove extending along the second direction and exposing the side wall of the vertical fin, wherein the depth of the first groove is less than that of the second groove; then, forming an embedded conductive line in the second trench, wherein the embedded conductive line extends along a second direction and is electrically connected with the fin at the bottom of the first trench; and then forming a first source/drain region in the fin at the top of the side wall of the first groove, a second source/drain region in the fin at the bottom of the side wall of the first groove and a first gate structure filled in the first groove, thereby forming the double-vertical L-shaped channel transistor with simple process. The method for manufacturing the double-vertical-channel transistor can form the first source/drain region and the second source/drain region together through the same ion implantation process without forming the first source/drain region and the second source/drain region step by step, so that on one hand, the ion implantation process for forming the first source/drain region and the second source/drain region in one step is simple, the process flow is simplified, the production cost is saved, on the other hand, the ion implantation process is not limited by the depth of the groove, the difficulty in manufacturing the ion implantation process is greatly reduced, meanwhile, the manufacturing process of the ion implantation process is not required to be changed while the depth of the groove is changed, and the method is favorable for adapting to the change of the size of a product. In addition, according to the preparation method of the double-vertical-channel transistor, the first groove is formed, the isolation groove which is positioned on the outer side of the vertical fin and parallel to the first groove is also formed, the first groove is filled with the first grid structure, and the isolation groove is also filled with the second grid structure, so that the isolation between the double-vertical-L-shaped-channel transistor and an adjacent device is realized, the increased shallow groove isolation rule can be avoided, the difficulty in manufacturing the shallow groove isolation and the process defects of the isolation structure are greatly reduced, and the further miniaturization of the product size and the improvement of the device performance are facilitated.
3. The integrated circuit memory comprises a plurality of double vertical channel transistors arranged in an array, and because the second source/drain region of each double vertical channel transistor is positioned at the bottom of the transistor without being directly led out from the surface of the transistor, the isolation among the transistors in the array is easier to form, the area of a memory cell can be reduced under the condition of the same size, and the cell area can be 4F2The hexagonal close-packed storage array improves the integration level of devices. Further, separateThe dummy word line in the off-trench can be connected to a substrate voltage to make the electrical properties of the transistors in the corresponding cell row in the array more optimal, thereby making the integrated circuit memory have better electrical properties.
4. According to the preparation method of the integrated circuit memory, the plurality of double vertical channel transistors which are arranged in an array are prepared by adopting the preparation method of the double vertical channel transistors, the process is simplified, the isolation between adjacent memory cells and between the memory array and a peripheral circuit can be avoided by using an increased shallow trench isolation rule, and the difficulty and process defects in manufacturing the shallow trench isolation are greatly reduced.
Drawings
Fig. 1 is a schematic perspective view of a dual vertical channel transistor according to an embodiment of the invention.
Fig. 2A is a schematic cross-sectional view taken along line XX' in fig. 1.
Fig. 2B is a schematic cross-sectional view taken along line MM' in fig. 1.
Fig. 2C is a schematic sectional view along the YY' line in fig. 1.
Fig. 2D is a schematic cross-sectional view along the NN' line in fig. 1.
Fig. 3 is a schematic perspective view of a dual vertical channel transistor according to another embodiment of the present invention.
Fig. 4 is a flow chart of a method of fabricating a dual vertical channel transistor in accordance with an embodiment of the present invention.
Fig. 5A to 5F are schematic top views of devices in the method for manufacturing the double vertical channel transistor shown in fig. 4.
Fig. 6A to 6F correspond to schematic cross-sectional structures at line XX' in fig. 5A to 5F, respectively.
Fig. 7A to 7E correspond to schematic cross-sectional structures at the MM' line in fig. 5A to 5F, respectively.
Fig. 8A to 8G correspond to the schematic cross-sectional structures at the YY' line in fig. 5A to 5F, respectively.
Fig. 9A to 9G correspond to schematic cross-sectional structures at NN' line in fig. 5A to 5F, respectively.
Wherein the reference numbers are as follows:
100-a semiconductor substrate; 1001-vertical fins; 101-fins on the sidewalls of the first trench (101 a); 102-fins at the bottom of the first trench (101 a); 101 a-a first trench; 101 b-a second trench; 101 c-a wire trench; 101 d-contact trench; 101 e-an isolation trench; 103-isolation regions; 103 b-the portion of the isolation region at the bottom of the first trench; 103 a-the portion of the isolation region other than 103 b; 104-a first dielectric layer; 105-buried conductive lines; 105 a-a comb substrate of buried conductive lines; 105 b-comb teeth of a buried wire; 106-conductive contact structures; 107 a-second source/drain region; 107 b-first source/drain regions; 108-a second dielectric layer; 109-a gate dielectric layer; 110-gate electrode layer; 111-a gate isolation layer; 112-first gate structure, word line; 113-second gate structure, dummy word line; h-initial thickness of semiconductor substrate 100; h1 — depth of first trench 101a in vertical fin 1001; h1+ H2 — the depth of the second trench 101b (including the depth where the second trench 101b intersects the first trench 101 a); h2 — height of fin at the bottom of the first trench 101a (i.e. the difference in depth between the depth of the first trench 101a and the depth of the second trench 101b in the vertical fin 1001).
Detailed Description
The present invention will be described in detail with reference to the accompanying drawings in order to make the objects and features of the present invention more comprehensible, however, the present invention may be realized in various forms and should not be limited to the embodiments described above. Note that, the "semiconductor substrate on both sides of the first trench" herein refers to a semiconductor substrate on both sides of a region where the first trench does not intersect with the second trench (i.e., a region of the first trench excluding a region where the first trench intersects with the second trench); the "semiconductor substrate at the bottom of the first trench" herein refers to a semiconductor substrate at the bottom of a region where the first trench does not intersect with the second trench. Further, it should be readily understood that the meaning of "on …" and "on …" herein should be interpreted in the broadest sense such that the meaning of "on …" and "on …" is not only "directly on something" without an intervening feature or layer, but also includes the meaning of "on something" with an intervening feature or layer.
FIG. 1 is a schematic perspective view of a dual vertical channel transistor according to an embodiment of the present invention; fig. 2A to 2D are schematic cross-sectional views along the line XX ', the line MM', the line YY ', and the line NN' in fig. 1, respectively. In fig. 1, in order to clearly show the structure in which the gate electrode layer, the second source/drain region, the buried conductive line, the conductive contact structure, and the like in the first gate structure of the dual vertical channel transistor are buried, the film layer structures such as the gate dielectric layer, the second dielectric layer, the gate isolation layer, and the like in the first gate structure are omitted, so that the gate electrode layer, the second source/drain region, the buried conductive line, the conductive contact structure, and the like in the first gate structure are shown, and the film layer structures such as the gate dielectric layer, the second dielectric layer, the gate isolation layer, and the like are shown in the cross-sectional structures of fig. 2A to 2D.
Referring to fig. 1 and fig. 2A to 2D, an embodiment of the invention provides a dual vertical channel transistor including a semiconductor substrate 100 having a vertical fin 1001, a first source/drain region 107b, a second source/drain region 107a, a buried conductive line 105, a conductive contact structure 106 and a first gate structure 112.
The material of the semiconductor substrate 100 may be any suitable material known to those skilled in the art, such as silicon-on-insulator (SOI), bulk silicon (bulk silicon), germanium, silicon germanium, gallium arsenide, or germanium-on-insulator (ge), etc. The vertical fin 1001 has a U shape and has a first groove 101a extending in a first direction. The semiconductor substrate further has a second trench 101b extending in the second direction and exposing sidewalls of the vertical fin 1001 extending in the second direction, an end of the first trench 101a along the first direction extends to the second trench 101b to communicate the first trench 101a and the second trench 101b on the sidewalls of the second trench 101b, and a bottom surface of the first trench 101a is higher than a bottom surface of the second trench 101b to expose sidewalls of the fin 102 at the bottom of the first trench 101a including the second source/drain region 107a in the second trench 101b, and the buried conductive line 105 is buried in the second trench 101b and extends in the second direction. That is, the first trench 101a communicates with the second trench 101b at the intersection, and the depth of all regions of the second trench 101b including the intersection is the same, i.e., the sum of H1 in fig. 6A and H2 in fig. 9A, and the depth H1 of the region of the first trench 101a other than the intersection is smaller than the depth H1+ H2 of the intersection, i.e., the depth of the first trench 101a is smaller than the depth of the second trench 101 b.
When the dual vertical channel transistor is a dual vertical channel transistor of an integrated circuit memory, the first direction is a word line direction/row direction of the integrated circuit memory, and the second direction is a bit line direction/column direction of the integrated circuit memory, i.e., the first direction and the second direction are perpendicular.
The vertical fin 1001 has two fins 101 with respect to the first trench 101a in the first direction, and the vertical fin 1001 as a whole forms a U-shaped fin having the first trench 101 with respect to the second trench 101b in the second direction. First source/drain regions 107b are formed in the fin 101 at the top of the two sides of the first trench 101a, and the top surface of the first source/drain regions 107b is the top surface of the fin 101 at the top of the two sides of the first trench 101 a; the second source/drain region 107a is formed in the fin 102 at the bottom of the first trench 101a, i.e., the top surface of the second source/drain region 107a is the bottom surface of the first trench 100a of the vertical fin 1001, and the first source/drain region 107b and the second source/drain region 107a can be formed in one step by the same ion implantation process. Furthermore, according to the transistor structures with different conductivity types, the first and second source/ drain regions 107b and 107a are doped with ions of corresponding conductivity types, for example, when the transistor structure is an N-type transistor, the doped ions in the first and second source/ drain regions 107b and 107a are N-type doped ions, such As phosphorus (P) ions, arsenic (As) ions, and antimony (Sb) ions; when the transistor structure is a P-type transistor, the doped ions in the first and second source/ drain regions 107b and 107a are P-type doped ions, such as boron(B) Ionic Boron Fluoride (BF)2 +) Ions, gallium (Ga) ions, and indium (In) ions. In this embodiment, the first source/drain region 107b may be a source region, and the second source/drain region 107a may be a drain region.
The embedded conductive line 105 may be linear, and is filled at the bottom of the second trench 101b and extends along the second direction to the entire length of the second trench 101b, and the embedded conductive line 105 is insulated and isolated from the semiconductor substrate 100 by the first dielectric layer 104 and is electrically connected to the second source/drain region 107a by the conductive contact structure 106. Wherein the buried conductive line 105, the second source/drain region 107a, the top surface of the conductive contact structure 106, and the top surface of the portion of the first dielectric layer 104 surrounding the buried conductive line 105 are flush. The first dielectric layer 104 is filled at the bottom of the second trench 101b and has a certain thickness, the first dielectric layer 104 may be L-shaped or U-shaped to surround the buried conductive line 105, and a portion of the first dielectric layer 104 on the bottom surface of the buried conductive line 105 extends to the boundary between the second source/drain region 107a and the second trench 101b, and the bottom surface of the buried conductive line 105 is not lower than the bottom surface of the second source/drain region 107a, thereby avoiding electrical connection with the semiconductor substrate 100 under the second source/drain region 107 a. Specifically, a linear conductive trench 101c is formed between the first dielectric layer 104 and the vertical fin 1001, the buried conductive line 105 and the conductive contact structure 106 are sequentially disposed in the conductive trench 101c from far to near along the first direction and close to the second source/drain region 107a, that is, after the buried conductive line 105 is filled in the conductive trench 101c, the buried conductive line 105 and the second source/drain region 107a form a contact trench 101d because the line width of the buried conductive line 105 is smaller than the opening size of the conductive trench 101c, the conductive contact structure 106 only fills the portion of the contact trench 101d corresponding to the second source/drain region 107a, and the other portion of the contact trench 101d is filled with the subsequent second dielectric layer 108. It can also be understood that the first dielectric layer 104 in an L shape continuously extends from the sidewall surface of the buried conductive line 105 facing away from the second source/drain region 107a to the bottom surface of the buried conductive line 105, until the sidewall surface of the second source/drain region 107a exposed by the second trench 101b, the conductive contact structure 106 is used for electrically connecting the buried conductive line 105 and the second source/drain region 107a, the conductive contact structure 106 is located in the second trench 101b and between the second source/drain region 107a and the buried conductive line 105, one sidewall of the conductive contact structure 106 is in contact with the sidewall surface of the second source/drain region 107a, the other sidewall of the conductive contact structure 106 is in contact with the sidewall surface of the buried conductive line 105, and the bottom surface of the conductive contact structure 106 is in contact with the surface of the semiconductor substrate 100 at the bottom of the second trench 101b through the gap The first dielectric layer 104 is insulated and isolated. In addition, the embedded conductive line 105 may be formed by evaporation, plating, chemical vapor deposition, atomic layer deposition, or the like, and may be a single-layer structure or a stacked structure, where the stacked structure includes two layers: a metal bottom layer and a polysilicon top layer, wherein the metal bottom layer may include at least one of tungsten, nickel, tungsten nitride, titanium nitride, tantalum nitride, copper, aluminum, silver, gold, and the like, but is not limited thereto; the polysilicon top layer may be a heavily doped polysilicon layer, such as an N-type doped polysilicon layer, or a metal silicide layer formed by reaction with polysilicon. The material of the first dielectric layer 104 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. The material of the conductive contact structure 106 may include at least one of tungsten, nickel, tungsten nitride, titanium nitride, tantalum nitride, copper, aluminum, silver, gold, and the like.
In other embodiments of the present invention, the first dielectric layer 104 filled in the second trench 101b may also be a linear structure (not shown), the top surfaces of the first dielectric layer 104 and the second trench 101 between the top surface of the first dielectric layer 104 and the top surface of the second source/drain region 107a are all located below the embedded conductive line 105, the linear conductive line trench for filling the embedded conductive line 105 and the conductive contact structure 106 is defined as the second trench 101, the embedded conductive line 105 and the conductive contact structure 106 are sequentially disposed in the linear conductive line trench from far to near to the second source/drain region 107a along the first direction, and the remaining space of the linear conductive line trench is filled with the subsequent second dielectric layer 108.
It should be noted that, in another embodiment of the present invention, the conductive contact structure 106 can be omitted, and the embedded conductive line 105 is replaced by a comb-shaped structure, specifically, referring to fig. 3, the linear conductive line groove 101c in the first dielectric layer 104 is adapted to be a comb-shaped conductive line groove 101c, the comb-base opening portion of the comb-shaped conductive line groove 101c extends along the second direction to the entire length of the second groove 101b, the comb-tooth opening portion of the conductive line groove 101c extends from the comb-base opening portion of the conductive line groove 101c to the sidewall of the second source/drain region 107a, so that the embedded conductive line 105 is in a comb-shaped structure, that is, the embedded conductive line 105 includes a comb base 105a and comb teeth 105b, the comb base 105a is located in the second groove 101b and extends along the second direction, that is, the comb base 105a is filled in the comb base opening portion of the comb-shaped wire groove 101c, and the comb teeth 105b extend from the comb base 105a to the sidewall surface of the second source/drain region 107a in the first direction, that is, the comb teeth 105b are filled in the comb tooth opening portion of the wire groove 101 c. Therefore, the buried conductive line 105 can be directly electrically contacted with the second source/drain region 107a through the comb-shaped teeth 105b, thereby saving the manufacturing process of the conductive contact structure 106, further simplifying the process and reducing the process defects.
The first gate structure includes a gate dielectric layer 109, a gate electrode layer 110 and a gate isolation layer 111, wherein the gate dielectric layer 109 covers an inner surface of the first trench 101a, and is used for realizing insulation and isolation between the gate electrode layer 110 and the vertical fin 1001 including the first source/drain region 107b and the second source/drain region 107 a. The gate electrode layer 110 is filled in the first trench 101a and extends to the entire length of the first trench 101a along the first direction, and at this time, the surface of the gate electrode layer 110 facing the first trench 101a is covered by the gate dielectric layer 109, that is, the gate dielectric layer 109 surrounds the bottom surface of the gate electrode layer 110 and the surface of the sidewall facing the vertical fin 1001. And the gate electrode layer 110 may extend from the first trench 101a of the vertical fin 1001 into the second trench 101b along the first direction to form a gate line (i.e., a word line of the integrated memory). In this embodiment, the top surface of the gate electrode layer 110 is lower than the top surface of the fin 101 (i.e., the top surface of the first source/drain region 107 b) of the sidewall of the first trench 101a, especially, the sidewall of the gate electrode layer 110 overlaps with the first source/drain region 107b only in a partial space in height, in order to avoid leakage between the first source/drain region 107b and the gate electrode layer 110, a gate isolation layer 111 is stacked above the gate electrode layer 110, and the gate isolation layer 111 fills the first trench 101a above the gate electrode layer 110 and the isolation trench 101e outside the sidewall of the vertical fin 1001 extending in the first direction. The gate dielectric layer 109 may be formed by a thermal oxidation (dry oxygen or wet oxygen) process, a chemical vapor deposition, an atomic layer deposition, or the like, the gate electrode layer 110 may be formed by a physical vapor deposition or a chemical vapor deposition, the gate electrode layer 110 may be a polysilicon gate, or may be a metal gate material, and when the gate electrode layer 110 is made of a polysilicon gate, the gate dielectric layer 109 may be made of silicon dioxide; when the gate electrode layer 110 is a metal gate material, the gate dielectric layer 109 may be a high-K dielectric having a dielectric constant K greater than 7. When the gate electrode layer 110 is a metal gate material, the gate electrode layer 110 includes a metal barrier layer (TiN, etc.), a work function layer (TiAl, TiN, etc.), and a metal electrode layer (for example, a metal such as tungsten W) sequentially stacked on a surface (including a bottom surface and a sidewall) of the gate dielectric layer 109. The gate isolation layer 111 may be formed by using a physical vapor deposition, a chemical vapor deposition, an atomic layer deposition, or the like, and the material of the gate isolation layer 111 includes, but is not limited to, silicon oxide, silicon nitride, and silicon oxynitride.
The first trenches 101a may be all rounded U-shaped grooves or rectangular U-shaped grooves, so that an L-shaped vertical conductive channel may be formed along a current conducting direction (i.e., a current flowing direction from one first source/drain region 107b on each side of the gate electrode layer 110 to the second source/drain region 107a at the bottom of the gate electrode layer 110), and on the premise that the vertical L-shaped channel occupies the same substrate area as a planar transistor, the vertical L-shaped channel may increase an effective channel length by increasing a height of a semiconductor pillar (i.e., a fin) between the first source/drain region 107b and the second source/drain region 107a, thereby overcoming a short channel effect and facilitating implementation of a smaller feature size. As such, even though the absolute distance between the first source/drain region 107b on one side of the gate electrode layer 110 and the second source/drain region 107a at the bottom of the gate electrode layer 110 is reduced as the device size is reduced, the short channel effect of the transistor can be effectively improved because the formed conductive channel is an L-shaped vertical conductive channel. In addition, since two L-type vertical conductive channels are simultaneously formed on both sides of the gate electrode layer 110, which corresponds to two common-drain and common-gate transistors, the device density can be increased in the same area.
Further, the top surface of the work function layer in the gate electrode layer 110 is lower than the top surface of the first source/drain region 107b, so that the distance between the work function layer and the first source/drain region 107b is increased, which is beneficial to preventing gate-to-drain doped drain (GIDL) of the work function layer between the first source/drain regions 107 b.
Further, an isolation region 103 may be further formed in the semiconductor substrate 300, the isolation region 103 is located in the semiconductor substrate 100 at the sidewall of the second trench 101b, a portion 103b of the isolation region 103 at the bottom of the first trench 101a is located below the second source/drain region 107a, and a portion of the isolation region 103 at the bottom of the isolation trench 101e is flush with a portion below the second source/drain region 107 a. The isolation region 103 and the second source/drain region 107a may form a PN junction, i.e., isolation between the dual vertical channel transistor and the peripherally adjacent elements is achieved by PN junction isolation. For example, in the present embodiment, if the doped ions in the formed second source/drain region 107a are N-type, the doped ions in the isolation region 103 are P-type. The doping depth of the isolation region 103 can be adjusted according to actual conditions, and the following conditions must be satisfied: the portion 103b of the isolation region 103 extending at the bottom of the first trench 101a needs to be located below the second source/drain region 107 a. In addition, the portion of the isolation region other than 103b is labeled 103 a.
The dual vertical channel transistor further includes a second dielectric layer 108, the second dielectric layer 108 covers an inner surface of the second trench 101b above the buried conductive line 105, and exposes an inner surface of the first trench 101a (including a region intersecting the second trench 101 b) above the second source/drain region 107a and an inner surface of the isolation trench 101e (including a region intersecting the second trench 101 b) above the second source/drain region 107a, and the gate dielectric layer 109 covers the inner surfaces of the first trench 101a and the isolation trench 101e above the second source/drain region 107 a. The top surface of the second dielectric layer 108 is also flush with the top surface of the first source/drain regions 107b to facilitate formation of subsequent structures (interconnect structures, etc.).
In addition, in other embodiments of the present invention, an isolation trench 100e extending along the first direction may be further formed outside the sidewall of the vertical fin 1001 extending along the first direction, the isolation trench 100e is filled with the second gate structure 113 to form a dummy gate structure of the dual vertical channel transistor, the dual vertical channel transistor is changed into the dual gate dual vertical channel transistor by the first gate structure 112 and the second gate structure 113, and the substrate voltage is applied through the second gate structure 113 in the isolation trench 100e, so that the electrical performance of the transistor may be improved. Specifically, referring to fig. 3, another embodiment of the present invention may further provide a dual-gate dual vertical channel transistor, which includes a semiconductor substrate 100 having a vertical fin 1001, a first source/drain region 107b, a second source/drain region 107a, a buried conductive line 105, a conductive contact structure 106, a first gate structure 112, and a second gate structure 113. The double-gate double vertical channel transistor may further omit the conductive contact structure 106, and may further include an isolation region 103 and a second dielectric layer 108 as shown in fig. 2A. The first gate structure 112 and the second gate structure 113 are formed by the same process, and also include a gate dielectric layer 109, a gate electrode layer 110, and a gate isolation layer 111.
The vertical fin 1001 of the dual-gate dual vertical channel transistor of this embodiment is U-shaped and has a first trench 101a extending along a first direction, an isolation trench 101e extending along the first direction is disposed outside an outer sidewall of the vertical fin 1001 extending along the first direction, and the isolation trench 101e exposes a sidewall of the vertical fin 1001 along the first direction. The first trench 101a and the isolation trench 101e are parallel to each other and formed by the same process, and have the same depth and width. The semiconductor substrate further has a second trench 101b, the second trench 101b extending in the second direction and exposing sidewalls of the vertical fin 1001, an end of the first trench 101a in the first direction extending to the second trench 101b to communicate the first trench 101a and the second trench 101b on the sidewalls of the second trench 101b, and a bottom surface of the first trench 101a being higher than a bottom surface of the second trench 101b to expose sidewalls of the fin 102 at a bottom of the first trench 101a including the second source/drain region 107a in the second trench 101b, the buried conductive line 105 being buried in the second trench 101b and extending in the second direction. That is, the first trench 101a and the isolation trench 101e communicate with the second trench 101b at the intersection, respectively, and the depth of all regions of the second trench 101b including the intersection is the same, i.e., the sum of H1 in fig. 6A and H2 in fig. 9A, and the depth H1 of the region of the first trench 101a other than the intersection is smaller than the depth H1+ H2 of the intersection, i.e., the depth of the first trench 101a is smaller than the depth of the second trench 101 b. The isolation trench 101e extending along the first direction and the second trench 101b extending along the second direction define a position of the vertical fin 1001 in the semiconductor substrate 100, the first trench 101a makes the vertical fin 1001U-shaped, i.e., the vertical fin 1001 has two fins 101 with respect to the first trench 101a along the first direction, and the vertical fin 1001 as a whole forms a U-shaped fin having the first trench 101 with respect to the second trench 101b along the second direction. The first gate structure 112 filled in the first trench 101a is formed, and simultaneously the second gate structure 113 is filled in the isolation trench 101e as a dummy gate structure, and other structures of the transistor of the present embodiment are the same as those of the transistor shown in fig. 1, and are not described herein again.
The second gate structure 113 in the dual-gate dual-vertical-channel transistor of this embodiment serves as a dummy gate structure, and can be connected to a substrate voltage (connected to a negative potential) for the dual-gate dual-vertical-channel transistor, so as to improve the electrical performance of the transistor. In addition, the dual-gate dual-vertical channel transistor of the embodiment can realize device isolation from adjacent elements through the isolation trench 101e, thereby avoiding using an increased shallow trench isolation rule, greatly reducing the difficulty of shallow trench isolation manufacturing and the process defects of an isolation structure, and being beneficial to further shrinking the product size and improving the device performance.
In summary, the double vertical channel transistor of the present invention has the double vertical L-shaped channels, and compared to the planar transistor, the double vertical L-shaped channels can increase the effective channel length by increasing the height of the semiconductor pillar between the first source/drain region and the second source/drain region on the premise that the double vertical L-shaped channels occupy the same substrate area, thereby overcoming the short channel effect and facilitating the realization of smaller feature size; and because the second source/drain region of the double vertical L-shaped channel is positioned at the bottom of the transistor, the second source/drain region does not need to be directly led out from the surface of the transistor, so that the isolation of the periphery of the transistor is easier to form, the area of the device is reduced under the condition of the same size, and higher integration level of the device can be provided in a given space amount. Furthermore, an isolation groove is arranged outside the outer side wall of the vertical fin along the first direction, a second grid structure (namely a virtual grid structure) is formed in the isolation groove, and therefore a double-grid double-vertical-channel transistor is formed.
The double vertical channel transistor is suitable for integrated circuit memories such as dynamic random access memories with higher storage density. The following will take an example of a process for forming a plurality of double vertical channel transistors (having a conductive contact structure 106) according to the present invention in a dynamic random access memory, and a method for fabricating the double vertical channel transistors according to the present invention will be described in detail with reference to fig. 4, fig. 5A to 5F, fig. 6A to 6F, fig. 7A to 7E, fig. 8A to 8G, and fig. 9A to 9G. The first direction is the word line direction/row direction, and the second direction is the bit line direction/column direction.
Referring to fig. 4, an embodiment of the invention provides a method for manufacturing a dual vertical channel transistor, including the following steps:
s1, providing a semiconductor substrate, and etching the semiconductor substrate along a first direction and a second direction respectively to form a vertical fin extending along the second direction and a second trench, wherein the second trench exposes a sidewall of the vertical fin extending along the second direction, the vertical fin has a first trench extending along the first direction, an end of the first trench along the first direction extends to the second trench, so that the first trench and the second trench communicate on the sidewall of the second trench, and a bottom surface of the first trench is higher than a bottom surface of the second trench;
s2, forming a buried conductive line in the second trench, the buried conductive line extending along a second direction and electrically connected to the fin at the bottom of the first trench;
s3, forming a first source/drain region and a second source/drain region in one step by adopting the same ion implantation process, wherein the first source/drain region is formed in the fin at the top of the side wall of the first groove, and the second source/drain region is formed in the fin at the bottom of the first groove; and the number of the first and second groups,
and S4, filling the first gate structure in the first trench above the second source/drain region.
Fig. 5A is a schematic top view illustrating a method for manufacturing a double vertical channel transistor according to an embodiment of the invention when step S1 is performed, and fig. 6A and 6B are schematic cross-sectional views along line XX' in fig. 5A during step S1 is performed; fig. 7A is a schematic cross-sectional view taken along the line MM' in fig. 5A during execution of step S1; fig. 8A and 8B are schematic sectional views along the YY' line in fig. 5A during the execution of step S1; fig. 9A and 9B are schematic cross-sectional views along the NN' line in fig. 5A during execution of step S1.
Referring to fig. 5A, fig. 6A, fig. 7A, fig. 8A and fig. 9A, in step S1, a semiconductor substrate 100 with a flat surface is provided, and the semiconductor substrate 100 provides an operation platform for subsequent processes, which may be any substrate known to those skilled in the art for carrying semiconductor integrated circuit components, such as a die, or a wafer processed by an epitaxial growth process, and has an initial thickness H, i.e., a height difference between the upper and lower surfaces of the semiconductor substrate 100. The semiconductor substrate 100 is, for example, a silicon-on-insulator (SOI) substrate, a bulk silicon (bulk silicon) substrate, a germanium-silicon substrate, an indium phosphide (InP) substrate, a gallium arsenide (GaAs) substrate, a germanium-on-insulator (ge) substrate, or the like; then, the semiconductor substrate 100 is etched along a first direction and a second direction perpendicular to each other, respectively, to form a vertical fin 1001 and a second trench 101b extending along the second direction in the semiconductor substrate 100, wherein the vertical fin 1001 has a first trench 101a extending along the first direction therein, and the vertical fin 1001 has an isolation trench 101e extending along the first direction outside a sidewall extending along the first direction (i.e., the isolation trench 101e is parallel to the first trench 101 a). In this embodiment, the isolation trench 101e is equivalent to one first trench 101a, and may be referred to as a virtual first trench 101a, and the depth of the first trench 101a is smaller than that of the second trench 101b, so that the semiconductor substrate 100 may be etched along the second direction to form a plurality of vertical fins 1001 extending along the second direction and arranged side by side, and then the vertical fins 1001 may be etched along the first direction to form a plurality of linear first trenches 101a extending along the first direction and arranged side by side, and a middle one of every three adjacent first trenches 101a is used as the isolation trench 101e, which includes the following specific processes:
step one, forming a first hard mask pattern (not shown) for defining a plurality of parallel second trenches 101b on the semiconductor substrate 100, so that the first hard mask pattern can cover and protect the semiconductor substrate 100 region corresponding to the first trenches 101a including the isolation trench 101e and both sides and cover and expose the semiconductor substrate 100 region corresponding to the second trenches 101b, and the first hard mask pattern can be a stacked structure having an oxide layer (not shown) and a nitride layer (not shown). More specifically, the oxide layer and the nitride layer may be sequentially formed on the semiconductor substrate 100 using a deposition process or the like; further, a surface of the nitride layer may be coated with a photoresist (not shown), and an exposure process and a development process may be performed to form a photoresist pattern (not shown), which may expose an area on the semiconductor substrate 100 where the second trench 101b is to be formed, and the exposed portions may have a line shape arranged side by side, e.g., the exposed portions may be parallel to each other; then, the nitride layer and the oxide layer may be sequentially etched by an etching process using the photoresist pattern as an etching mask to form a first hard mask pattern. Thereafter, the photoresist pattern is removed.
Step two, etching the semiconductor substrate 100 by using the first hard mask pattern as an etching mask to form a plurality of second trenches 101b with a depth of H1+ H2, wherein a complete fin (equivalent to a plurality of vertical fins 1001 connected together) extending along the second direction is formed on the semiconductor substrate 100 between two adjacent second trenches 101b, that is, the second trenches expose sidewalls of the complete fin extending along the second direction.
Step three, a sacrificial layer can be formed on the whole structure to fill the second trench 101b, wherein the material of the sacrificial layer is different from that of the semiconductor substrate 100, so as to facilitate subsequent removal, such as silicon oxide, silicon nitride, silicon oxynitride, or the like; subsequently, a chemical mechanical planarization process may be employed to remove the first hard mask pattern and the sacrificial layer thereon to provide a planar process surface for subsequent processes.
Step four, a second hard mask pattern (not shown) may be formed on the remaining sacrificial layer and the semiconductor substrate 100. The second hard mask pattern is used to define a plurality of line-shaped first trenches 101a extending in the first direction and arranged side by side, so that the second hard mask pattern can expose the regions of the semiconductor substrate 100 and the sacrificial layer corresponding to the first trenches 101a and the isolation trenches 101e and cover and protect other regions, for example, the exposed portions can be parallel to each other, and the forming process of the second hard mask pattern may refer to the forming process of the first hard mask pattern, which is not described herein again.
And fifthly, etching the semiconductor substrate 100 and the exposed sacrificial layer by an etching process using the second hard mask pattern as an etching mask, wherein the etching depth is H1, so as to form a plurality of first trenches 100a with the depth of H1, that is, the end parts of the first trenches 101a along the first direction extend to the second trenches 101b, so that the first trenches 101a and the second trenches 101b are communicated on the side walls of the second trenches 101b, and the bottom surfaces of the first trenches 101a are higher than the bottom surfaces of the second trenches 101 b. Taking the middle one of every three adjacent first trenches 101a as an isolation trench 101e, at this time, the vertical fin 1001 surrounded by the isolation trench 101e and the second trench 101b is an active region of a dual vertical channel transistor to be formed, and the vertical fin 1001 corresponding to each dual vertical channel transistor becomes a U-shaped structure having the first trench 101a, and the height of the fin 1001 at the bottom of the first trench 101a relative to the bottom surface of the second trench 101b is H2. This step is equivalent to cutting each complete fin extending in the second direction simultaneously to form each U-shaped vertical fin 1001 having the first trench 101a
Step six, the second hard mask pattern and the remaining sacrificial layer may be removed to expose the surface of the semiconductor substrate 100. The process of removing the sacrificial layer may be a wet etching process, and the process of removing the second hard mask pattern may be a chemical mechanical planarization process or a wet etching process.
It should be noted that, in the above steps, the second trench 101b is formed first, and then the first trench 101a and the isolation trench 101e are formed, but the technical solution of the present invention is not limited thereto, and the first trench 101a, the isolation trench 101e may be formed first, and then the second trench 101b is formed.
Referring to fig. 5A, fig. 6B, fig. 7B, fig. 8B and fig. 9B, in step S1, a trap ion implantation process may be employed to implant ions inverse to the second source/drain region 107a to be formed subsequently into the bottom of the vertical fin 1001 to form the isolation region 103, and the isolation region 103 and the subsequent second source/drain region 107a may form a PN junction, that is, isolation between the double vertical channel transistor and the peripheral adjacent device is achieved by PN junction isolation. For example, in the present embodiment, if the doped ions in the formed second source/drain region 107a are N-type, the doped ions in the isolation region 103 are P-type. The doping depth of the isolation region 103 can be adjusted according to actual conditions, and the following conditions must be satisfied: the portion 103b of the isolation region 103 extending at the bottom of the first trench 101a needs to be located below the second source/drain region 107a to be formed later. In addition, the portion of the isolation region other than 103b is labeled 103 a.
Fig. 5B is a schematic top view of the manufacturing method of the double vertical channel transistor in the embodiment of the invention when step S2 is performed, and fig. 6B, 7B, 8C and 9C are schematic cross-sectional structures along the XX ', MM', YY 'and NN' lines in fig. 5B during step S2. Referring to fig. 5B, fig. 6B, fig. 7B, fig. 8C and fig. 9C, in step S2, the specific process of forming the embedded conductive line 105 in the second trench 101B is as follows:
step one, a thermal oxidation (wet oxidation or dry oxidation) process, an in-situ steam generation process (ISSG), a Chemical Vapor Deposition (CVD) process, an atomic layer deposition process, or the like may be employed to form a first dielectric layer 104 over the entire semiconductor substrate 100 structure having the U-shaped vertical fin 1001, the isolation trench 101e, and the second trench 101b, the thickness of the first dielectric layer 104 on the bottom of the second trench 101b is less than H2 and not less than the height of the bottom surface of the subsequently formed second source/drain region 107a, so that the bottom surface of the subsequently formed buried conductive line 105 is not lower than the bottom surface of the second source/drain region 107a and is isolated from the semiconductor substrate 100 under the second source/drain region 107a, and the top surface of the subsequently formed buried conductive line 105 is not higher than the top surface of the second source/drain region 107a, for example, is flush with the top surface of the second source/drain region 107a, to provide a globally planar trench bottom surface for subsequent formation of the first and second gate structures 112 and 113. The first dielectric layer 104 may be made of a material having a high etching selectivity with respect to the semiconductor substrate 100, such as silicon oxide, silicon nitride, or silicon oxynitride.
Step two, the first dielectric layer 104 may be etched by using an anisotropic dry etching process to expose the first trench 101a of the vertical fin 1001 and the inner surface (including the sidewall and the bottom surface) of the isolation trench 101e outside the vertical fin 1001 (i.e. the region where the first trench 101a and the isolation trench 101e do not intersect with the second trench 101 b), so that the remaining first dielectric layer 104 is only filled in the second trench 101b, and a linear conductive line trench 101c is simultaneously formed in the first dielectric layer 104 on the second trench 101b, at this time, the structure of the remaining first dielectric layer 104 is L-shaped or linear, when the structure of the remaining first dielectric layer 104 is L-shaped, a sidewall and a bottom surface of the subsequently formed embedded conductive line 105 are surrounded and covered by the remaining first dielectric layer 104, when the remaining first dielectric layer 104 is linear, the remaining first dielectric layer 104 is completely located under the subsequently formed buried conductive line 105, only the bottom surface of the buried conductive line 105 is in contact with the remaining first dielectric layer 104, the conductive line trench 101c extends along the second direction to the entire length of the second trench 101b, the conductive line trench 101c exposes sidewalls within the height of the second source/drain region 107a of the vertical fin 1001 extending along the second direction, the bottom of the conductive line trench 101c does not expose the surface of the semiconductor substrate 100 at the bottom of the second trench 101b, and the sidewalls of the conductive line trench 101c expose sidewalls of the fin 102 at the bottom of the first trench 101a, so that the subsequently formed buried conductive line 105 is electrically connected with the subsequently formed second source/drain region 107a in the fin 102 at the bottom of the first trench 101 a.
Step three, the conductive wire trench 101c may be filled with a conductive material through electroplating, physical vapor deposition, chemical vapor deposition, and other processes to form the embedded wire 105, where the conductive material may be single to form the embedded wire 105 in a single-layer film structure, and the conductive material may also be multiple to form the embedded wire 105 in a stacked structure, where the stacked structure may include a metal bottom layer and a polysilicon top layer, and the metal bottom layer may include tungsten, nickel, tungsten nitride, titanium nitride, tantalum nitride, copper, aluminum, silver, gold, or the like, but is not limited thereto. The top layer of polysilicon may be an undoped polysilicon layer or a heavily doped polysilicon layer, such as an N-type doped polysilicon layer.
And fourthly, at least etching one side of the embedded type conducting wire 105 close to the vertical fin 1001 by adopting a dry etching process, and reducing the line width of the embedded type conducting wire 105 to form a conductive contact groove 101d in the conducting wire groove 101c, wherein the conductive contact groove 101d extends to the length of the whole second groove 101b, and the bottom of the conductive contact groove 101d is exposed out of the top surface of the rest first dielectric layer 104.
Step five, the conductive contact structure 106 may be filled in the conductive contact groove 101d through electroplating, physical vapor deposition, chemical vapor deposition, and other processes, the conductive contact structure 106 fills the conductive contact groove 101d, and further the conductive contact structure 106 is etched, so as to remove the conductive contact structure 106 on the sidewall of the vertical fin 1001 outside the fin 102 region at the bottom of the first trench 101a, so as to isolate the embedded wire 105 from the vertical fin 1001 portion outside the second source/drain region 107a formed subsequently, and the conductive contact groove 101d region exposed again in this step will be filled with the second dielectric layer 108 in the subsequent step.
It should be appreciated that the solution of forming the buried conductive line 105 in the present invention is not limited thereto, as long as the buried conductive line 105 can be electrically connected to the fin 102 at the bottom of the first trench 101a (i.e. the portion for forming the second source/drain region 107a later, and insulated and isolated from the fin 101 at both sides of the first trench 101a and the fin 102 under the second source/drain region 107, therefore, with continuing reference to fig. 5B, 6B, 7B, 8C and 9C, in another embodiment of the present invention, the solution of forming the buried conductive line 105 in the step S2 may further include the following processes:
step one, a thermal oxidation (wet oxidation or dry oxidation) process, an in-situ steam generation process (ISSG), a Chemical Vapor Deposition (CVD) process, an atomic layer deposition process, or the like may be employed to form a first dielectric layer 104 over the entire semiconductor substrate 100 structure having the U-shaped vertical fin 1001, the isolation trench 101e, and the second trench 101b, the thickness of the first dielectric layer 104 on the bottom of the second trench 101b is less than H2 and not less than the height of the bottom surface of the subsequently formed second source/drain region 107a, so that the bottom surface of the subsequently formed buried conductive line 105 is not lower than the bottom surface of the second source/drain region 107a and is isolated from the semiconductor substrate 100 under the second source/drain region 107a, and the top surface of the subsequently formed buried conductive line 105 is not higher than the top surface of the second source/drain region 107a, for example, is flush with the top surface of the second source/drain region 107a, to provide a globally planar trench bottom surface for subsequent formation of the first and second gate structures 112 and 113. .
Step two, the first dielectric layer 104 may be etched by using an anisotropic dry etching process to expose the first trench 101a of the vertical fin 1001 and the inner surface (including the sidewall and the bottom surface) of the isolation trench 101e outside the vertical fin 1001 (i.e., the region where the first trench 101a and the isolation trench 101e do not intersect with the second trench 101 b), so that the remaining first dielectric layer 104 is only filled in the second trench 101b, and a linear conductive line trench 101c is simultaneously formed in the first dielectric layer 104, at this time, the remaining first dielectric layer 104 is of a U-shaped structure, the conductive line trench 101c extends to the length of the entire second trench 101b along the second direction, and the second source extending along the second direction is not exposed on both sides of the conductive line trench 101c
The sidewall of the semiconductor substrate 100 within the height of the drain region 107a, and the bottom of the conductive line trench 101c are not exposed to the surface of the semiconductor substrate 100 at the bottom of the second trench 101b, and at this time, the top surface of the first dielectric layer 104 in the second trench 101b including the intersection with the first trench 101a and the isolation trench 101e may be flush with the top surface of the bottom of the first trench 101a due to etching.
In step three, the conductive wire trench 101c may be filled with a conductive material through a plating process, a physical vapor deposition process, a chemical vapor deposition process, or the like, so as to form the buried conductive wire 105.
Step four, the first dielectric layer 104 between the embedded type wire 105 and the fin 102 at the bottom of the first trench 101a is etched and removed by using a dry etching process to form a conductive contact groove 101d, the bottom of the conductive contact groove 101d exposes the top surface of the remaining first dielectric layer 104, the length of the conductive contact groove 101d along the second direction is only the length of the fin 102 at the bottom of the first trench 101a (i.e., the line width of the first trench 101a), and the first dielectric layer 104 can directly isolate the embedded type wire 105 and a subsequently formed conductive contact structure 106 from the fins 101 at two sides of the first trench 101a, so as to prevent the embedded type wire 105 and the conductive contact structure 106 from being electrically connected with the fins 101 at two sides of the first trench 101 a.
Step five, the conductive contact structure 106 may be filled in the conductive contact groove 101d by electroplating, physical vapor deposition, chemical vapor deposition, or the like, and the conductive contact structure 106 is filled in the conductive contact groove 101 d.
This scheme of forming the buried conductive lines 105 can avoid etching of the excess buried conductive lines 105 and the excess conductive contact structures 106 on the sidewalls of the fins 101 on both sides of the first trench 101a, and the process is relatively simple.
In other embodiments of the present invention, when the first dielectric layer 104 is etched in the second step, the second dielectric layer 104 in the second trench 101b may further be made to be a linear structure, the top surfaces of the second dielectric layer 104 are both located below the embedded conductive line 105 to be formed subsequently, the second trench 101 between the top surface of the first dielectric layer 104 and the top surface of the second source/drain region 107a to be formed is a linear conductive line trench for filling the embedded conductive line 105 and the conductive contact structure 106, the embedded conductive line 105 and the conductive contact structure 106 are sequentially disposed in the conductive line trench from far to near to the second source/drain region 107a along the first direction, and the remaining space of the conductive line trench is filled with the subsequent second dielectric layer 108. The scheme for forming the buried conductive line 105 can reduce the etching difficulty of the first dielectric layer 104.
In the above embodiments, the embedded conductive line 105 is formed first, and then the conductive contact structure 106 is formed, but the technical solution of the present invention is not limited thereto, and the conductive contact structure 106 may be formed first, and then the embedded conductive line 105 is formed, for example, the first dielectric layer 104 is etched to form a conductive contact trench for filling the conductive contact structure 106, and after the conductive contact trench is filled with the conductive contact trench, the first dielectric layer 104 is etched to form a conductive line trench 101c for filling the embedded conductive line 105, and then the embedded conductive line 105 is filled in the conductive line trench 101c, or the first dielectric layer 104 is etched to form a conductive line trench 101c for filling the conductive contact structure 106 and the embedded conductive line 105, and then the conductive contact structure 106 is deposited and etched in the conductive line trench 101c to form the conductive contact structure 106, and then the embedded conductive line 105 is deposited, and the buried conductive line 105 is formed by etching, so that the process window for forming the conductive contact structure 106 can be increased, the process difficulty for forming the conductive contact structure 106 can be reduced, and the electrical connection performance between the buried conductive line 105 and the subsequently formed second source/drain region 107a can be improved. In addition, it should be noted that, in other embodiments of the present invention, when the deposition thickness of the first dielectric layer 105 is below the bottom surface of the second source/drain region 107a, a sacrificial layer may be additionally deposited to protect other regions, and the sacrificial layer is further etched to open the conductive contact groove corresponding to the conductive contact structure 106, and after the conductive contact structure 106 is filled in the conductive contact groove, the sacrificial layer is continuously etched to open the conductive line trench corresponding to the embedded conductive line 105 and fill the embedded conductive line 105 in the conductive line trench, and then the sacrificial layer is removed.
With continuing reference to fig. 3, fig. 5B, fig. 6B, fig. 7B, fig. 8C and fig. 9C, in yet another embodiment of the present invention, the step S2 of forming the embedded conductive line 105 may further include the following steps:
step one, a thermal oxidation (wet oxidation or dry oxidation) process, an in-situ steam generation process (ISSG), a Chemical Vapor Deposition (CVD) process, an atomic layer deposition process, or the like may be employed to form a first dielectric layer 104 over the entire semiconductor substrate 100 structure having the U-shaped vertical fin 1001, the isolation trench 101e, and the second trench 101b, the thickness of the first dielectric layer 104 on the bottom of the second trench 101b is less than H2 and not less than the height of the bottom surface of the subsequently formed second source/drain region 107a, so that the bottom surface of the subsequently formed buried conductive line 105 is not lower than the bottom surface of the second source/drain region 107a and is isolated from the semiconductor substrate 100 under the second source/drain region 107a, and the top surface of the subsequently formed buried conductive line 105 is not higher than the top surface of the second source/drain region 107a, for example, is flush with the top surface of the second source/drain region 107a, to provide a globally planar trench bottom surface for subsequent formation of the first and second gate structures 112 and 113. .
Step two, the first dielectric layer 104 may be etched by using an anisotropic dry etching process to expose the first trench 101a of the vertical fin 1001 and the inner surface (including the sidewall and the bottom surface) of the isolation trench 101e (i.e., the region where the first trench 101a and the isolation trench 101e do not intersect with the second trench 101 b) outside the vertical fin 1001, so that the remaining first dielectric layer 104 is only filled in the second trench 101b, and simultaneously a comb-shaped conductive line trench 101c is formed in the first dielectric layer 104 on the second trench 101b, the bottom of the conductive line trench 101c is not exposed out of the surface of the semiconductor substrate 100 at the bottom of the second trench 101b, the conductive line trench 101c has a comb-shaped opening portion extending along the second direction to the entire length of the second trench 101b, and a side of the second source/drain region 107a is extended from the comb-shaped opening portion along the first direction A comb tooth opening portion at the wall; at this time, the top surface of the first dielectric layer 104 in the second trench 101b may be flush with the bottom surface of the first trench 101a due to etching.
In step three, the conductive material may be filled in the conductive line trench 101c through electroplating, physical vapor deposition, chemical vapor deposition, or the like, so as to form the comb-shaped buried conductive line 105. The first dielectric layer 104 can directly isolate the buried conductive line 105 from the fins 101 on both sides of the first trench 101a, thereby preventing the buried conductive line 105 from being electrically connected to the fins 101 on both sides of the first trench 101 a. Referring to fig. 3, the comb-shaped embedded conductive line 105 includes a comb base 105a and comb teeth 105b, the comb base 105a is located in the second trench 101b and extends along the second direction, i.e., the comb base 105a is filled in the comb base opening portion of the comb-shaped conductive line trench 101c and is insulated and isolated from the fins 101 on both sides of the first trench 101a by the first dielectric layer 104, and the comb teeth 105b extend along the first direction from the comb base 105a to the sidewall surface of the fin 102 (i.e., the subsequent second source/drain region 107a) at the bottom of the first trench 101a, i.e., the comb teeth 105b are filled in the comb tooth opening portion of the conductive line trench 101 c. Therefore, the embedded conductive line 105 can be electrically contacted with the second source/drain region 107a formed subsequently directly through the comb teeth 105b, thereby saving the manufacturing process of the conductive contact structure 106, further simplifying the process, and reducing the process defects.
Fig. 5C is a schematic top view illustrating a structure of the method for manufacturing the double vertical channel transistor in step S3, and fig. 6C, 7B, 8D, and 9D are schematic cross-sectional structures along the XX ', MM', YY ', and NN' lines in fig. 5C during step S3.
Referring to fig. 5C, fig. 6C, fig. 7B, fig. 8D and fig. 9D, in step S3, the same source/drain ion implantation process may be used to perform source/drain ion doping on the fin 101 at the top of the two sides of the first trench 101a and the fin 102 at the bottom of the first trench 101a, so as to simultaneously form the first source/drain region 107B in the fin 101 at the top of the two sides of the first trench 101a and the second source/drain region 107a in the fin 102 at the bottom of the first trench 101a in one step. Furthermore, the first source/drain region 107b and the second source/drain region 107a are doped with respective conductive layers according to transistor structures of different conductivity typesAn electric type ion, for example, when the transistor structure is an N-type transistor, the doping ions in the first source/drain region 107b and the second source/drain region 107a are N-type doping ions, for example, phosphorus (P) ions, arsenic (As) ions, and antimony (Sb) ions; when the transistor structure is a P-type transistor, the doped ions in the first source/drain region 107B and the second source/drain region 107a are P-type doped ions, such as boron (B) ions and Boron Fluoride (BF)2 +) Ions, gallium (Ga) ions, and indium (In) ions. In this embodiment, the first source/drain region 107b and the second source/drain region 107a are formed without step-by-step ion implantation, and the ion implantation is performed by using the same process, so that the first source/drain region 107b and the second source/drain region 107a are formed.
Fig. 5D to 5F are schematic top-view structural diagrams of the method for manufacturing a dual vertical channel transistor in the embodiment of the invention when step S4 is performed, and fig. 6D to 6F are schematic cross-sectional structural diagrams along line XX' in fig. 5D to 5F during step S4 is performed; fig. 7C to 7E are schematic cross-sectional views along the MM' line in fig. 5D to 5F during the step S4; fig. 8E to 8G are schematic cross-sectional views along the YY' line in fig. 5D to 5F during the step S4; fig. 9E to 9G are schematic cross-sectional structures along the NN' line in fig. 5D to 5F during the step S4.
Referring to fig. 5D, fig. 6D, fig. 7C, fig. 8E and fig. 9E are schematic cross-sectional views along the XX ', MM', YY 'and NN' lines in fig. 5D, respectively. In step S4, first, a thermal oxidation (wet oxidation or dry oxidation) process, an in-situ steam generation process (ISSG), a Chemical Vapor Deposition (CVD) process, an atomic layer deposition process, or the like may be employed to form the second dielectric layer 108 over the entire structure having the first source/drain region 107b and the second source/drain region 107a, and the second dielectric layer 108 may fill the second trench 101 b. The material of the second dielectric layer 108 may be silicon oxide, silicon nitride, amorphous carbon, organic dielectric material (ODL), low-K dielectric (dielectric constant K is less than 4), etc. as long as the etching selectivity ratio of the second dielectric layer to the semiconductor substrate 100, the embedded conductive line 105 and the conductive contact structure 106 is high. Further, a Chemical Mechanical Planarization (CMP) process may be used to planarize the top surface of the second dielectric layer 108 to provide a planar process surface for subsequent processing. Optionally, the top surface of the second dielectric layer 108 may be planarized to stop on the top surface of the first source/drain region 107 b.
Referring to fig. 5E, fig. 6E, fig. 7D, fig. 8F and fig. 9F are schematic cross-sectional views along the line XX ', the line MM', the line YY 'and the line NN' in fig. 5E, respectively. In step S4, the second dielectric layer 108 in the first trench 101a (including the region intersecting the second trench 101 b) and the isolation trench 101e (including the region intersecting the second trench 101 b) above the second source/drain region 107a may be removed by a photolithography process and further combined with a plasma etching process to expose the top surface of the second source/drain region 107a, i.e., to re-expose the sidewall and bottom surface of the first trench 101a, i.e., to form a gate trench (also referred to as a word line trench), at which time, all regions of the first trench 101a including the region communicating with (i.e., intersecting) the second trench 101b and all regions of the isolation trench 101e including the region intersecting the second trench 101b, which are higher than the top surface of the second source/drain region 107a, are removed, that is, the re-exposed first trench 101a penetrating through the plurality of side-by-side vertical fins 1001 is used for subsequently forming the first gate structure 112 (i.e., word line of the integrated circuit memory), and the re-exposed isolation trench 100 outside the plurality of side-by-side vertical fins 1001 is used for subsequently forming the second gate structure 113 (i.e., dummy gate structure of the dual vertical channel transistor, i.e., dummy word line of the integrated circuit memory); then, a gate dielectric layer 109 may be covered on the exposed inner surface of the first trench 101a and the inner surface of the isolation trench 101e by using a thermal oxidation (wet oxidation or dry oxidation) process, an in-situ steam generation process (ISSG), a Chemical Vapor Deposition (CVD) process, an atomic layer deposition process, or the like, the inner surface of the first trench 101a including the inner sidewall of the fin 101 having the first source/drain region 107b, the top surface of the second source/drain region 107a, and the sidewall and the bottom where the first trench 101a communicates with the second trench 101b, and the inner surface of the isolation trench 101e including the outer sidewall of the fin 101 having the first source/drain region 107b, the top surface of the semiconductor substrate 100, and the sidewall and the bottom where the isolation trench 101e communicates with the second trench 101 b. When the first gate structure 112 and the second gate structure 113 formed subsequently are polysilicon gate structures, the gate dielectric layer 109 is preferably made of silicon dioxide; when the gate electrode layer 110 to be formed later is a metal gate, the material of the gate dielectric layer 109 is preferably a high-K dielectric (K is greater than 7).
Referring to fig. 5F, fig. 6F, fig. 7E, fig. 8G and fig. 9G, fig. 5F is a schematic top view of the second dielectric layer 108 and the gate isolation layer 111, which are omitted, and fig. 6F, fig. 7E, fig. 8G and fig. 9G are schematic cross-sectional views along the line XX ', the line MM', the line YY 'and the line NN' in fig. 5F, respectively. In step S4, the gate electrode layer 110 (i.e., the word line) is filled in the first trench 101a having the gate dielectric layer 109, and the gate electrode layer 110 is simultaneously filled in the isolation trench 110e having the gate dielectric layer 109. The specific process comprises the following steps:
firstly, depositing a gate electrode layer 110 on the surface of the gate dielectric layer 109 through processes such as evaporation, electroplating, chemical vapor deposition, atomic layer deposition, and the like, wherein the deposition thickness on the bottom surfaces of the first trench 101a and the isolation trench 110e at least reaches the thickness required by the gate electrode layer 110 (i.e., word line) to be formed, the gate electrode layer 110 may be a single-layer structure or a stacked-layer structure, the gate electrode layer 110 may be made of a material for manufacturing a polysilicon gate, such as undoped polysilicon or doped polysilicon, or a material for manufacturing a metal gate, such as a metal barrier layer (TiN, etc.), a work function layer (TiAl, TiN, etc.), and a metal electrode layer (tungsten W, etc.) sequentially stacked on the surface (including the bottom surface and the sidewall) of the gate dielectric layer 109; thereafter, the gate electrode layer 110 on the region outside the first trench 101a and the isolation trench 110e may be removed by an etch-back or chemical mechanical planarization process or the like, so that the gate electrode layer 110 is only filled in the first trench 101a and the isolation trench 110e, and the top surface of the gate electrode layer 110 remaining in the first trench 101a and the isolation trench 110 is lower than the top surface of the first source/drain region 107b, even lower than the bottom surface of the first source/drain region 107 b; next, a gate isolation layer 111 may be deposited on the exposed surfaces of the gate dielectric layer 109 and the gate electrode layer 110 by using a physical vapor deposition, a chemical vapor deposition, an atomic layer deposition, or the like, wherein the material of the gate isolation layer 111 includes, but is not limited to, silicon oxide, silicon nitride, and silicon oxynitride. Thereafter, the excess gate isolation layer 111 and the gate dielectric layer 109 above the first source/drain region 107b may be further removed by a chemical mechanical planarization process to embed the gate electrode layer 110 in the first trench 101a and the isolation trench 101e, respectively, so as to form a first gate structure 112 (i.e., an embedded word line) embedded in the first trench 101a and a second gate structure 113 (i.e., an embedded dummy word line or a dummy gate structure) embedded in the isolation trench 101 e.
In summary, the method for manufacturing a double vertical channel transistor of the present invention forms a double vertical L-shaped channel, and compared to a planar transistor, the double vertical L-shaped channel can increase the effective channel length by increasing the height of the semiconductor pillar between the first source/drain region and the second source/drain region on the premise that the double vertical L-shaped channel occupies the same substrate area, thereby overcoming the short channel effect and facilitating the realization of smaller feature size; and because the second source/drain region of the double vertical L-shaped channel is positioned at the bottom of the transistor, the second source/drain region does not need to be directly led out from the surface of the transistor, so that the isolation of the periphery of the transistor is easier to form, the area of the device is reduced under the condition of the same size, and higher integration level of the device can be provided in a given space amount. In addition, the method for preparing the double-vertical-channel transistor can form the first source/drain region and the second source/drain region together by the same ion implantation process, on one hand, the process flow is simplified, the production cost is saved, on the other hand, the ion implantation process is not limited by the depth of the groove, the difficulty in manufacturing the ion implantation process is greatly reduced, and meanwhile, the manufacture procedure of the ion implantation process is not required to be changed while the depth of the groove is changed, so that the method is favorable for adapting to the change of the size of a product. Furthermore, an isolation groove is arranged outside the outer side wall of the vertical fin along the first direction, the isolation groove and the first groove are formed by the same process, a first grid structure is filled in the first groove, and a second grid structure (namely a virtual grid structure) is also filled in the isolation groove, so that a double-grid double-vertical-channel transistor is formed, the virtual grid structure can be connected with substrate voltage, the transistor has the function of the substrate voltage, and the electrical property of the transistor is further optimized. The preparation method of the double vertical channel transistor is suitable for manufacturing the storage array of the integrated circuit memories such as the dynamic random access memory.
Therefore, with continued reference to fig. 3, fig. 5F, fig. 6F, fig. 7E, fig. 8G and fig. 9G, an embodiment of the present invention provides an integrated circuit memory, which includes a plurality of dual vertical channel transistors according to the present invention, the dual vertical channel transistors are arranged in a cell row and a cell column in an array along a first direction and a second direction, that is, each dual vertical channel transistor is connected to a corresponding storage capacitor to form a memory cell and a memory array, and the first trenches 101a of all the dual vertical channel transistors in each cell row are integrally formed (i.e., integrally connected along the row direction), so that the first gate structures 112 of all the dual vertical channel transistors in the cell row are integrally formed as a Word Line (WL) of the integrated circuit memory, and the isolation trenches 101E of all the dual vertical channel transistors in each cell row are integrally formed (i.e., integrally connected along the row direction), the second gate structures 113 of all the dual vertical channel transistors on the cell row are integrally formed as a DUMMY word line (DUMMY WL) of the integrated circuit memory, and the buried conductive lines 105 of all the dual vertical channel transistors on each cell column are integrally formed as a Bit Line (BL) of the integrated circuit memory. The isolation trench 101e is located outside the outer sidewall of the vertical fins 1001 of all the double vertical channel transistors in the cell row along the first direction, and exposes the outer sidewall of the vertical fins 1001 of all the double vertical channel transistors in the cell row along the first direction, so as to achieve isolation between the double vertical channel transistors in two adjacent cell rows, the isolation trench 101e and the first trench 101a are formed by using the same process, and the dummy word line embedded in the isolation trench 101e and the word line embedded in the first trench 101a are formed by using the same process.
The semiconductor substrate 100 further has a second trench 101b extending in the second direction, the second trench 101b exposes sidewalls of all the vertical fins 1001 of the dual vertical channel transistors on the cell column extending in the second direction, the bit line is formed in the second trench 101b, ends of the first trench 101a and the isolation trench 101e in the first direction extend to the second trench 101b so that the first trench 101a and the isolation trench 101e communicate with the second trench 101b on the sidewalls of the second trench 101b, respectively, and the first trench 101a and the isolation trench 101e have the same depth and bottom surfaces of the first trench 101a and the isolation trench 101e are higher than that of the second trench 101b so that the second source/drain region 107a is exposed in the second trench 101b and electrically connected to the bit line, the bottom surfaces of the first gate structure 112 and the second gate structure 113 are equal in height.
That is to say, in the integrated circuit memory of the present invention, a second trench 101b extending along the second direction is disposed between two adjacent cell columns, the second trench 101b exposes sidewalls of vertical fins 1001 of all the dual vertical channel transistors on the two adjacent cell columns extending along the second direction, a bit line of the integrated circuit memory is filled in the second trench 101b, and the bit line is electrically connected to the second source/drain regions 107a of all the dual vertical channel transistors on the cell column on one side of the second trench 101 b; an isolation trench 101e extending along the first direction is formed between two adjacent cell rows, and the isolation trench 101e exposes the outer sidewalls of the vertical fins 1001 of all the dual vertical channel transistors in the two adjacent cell rows along the first direction, so as to achieve isolation between the dual vertical channel transistors in the two adjacent cell rows.
With continued reference to fig. 4, the present invention further provides a method for manufacturing an integrated circuit memory, wherein a plurality of double vertical channel transistors are manufactured by the method for manufacturing double vertical channel transistors according to the present invention, all the double vertical channel transistors are arranged in an array along a first direction and a second direction according to a unit row and a unit column, and first trenches 101a of all the double vertical channel transistors in each unit row are integrally formed, so that first gate structures 112 of all the double vertical channel transistors in the unit row are integrally formed to serve as a word line of the integrated circuit memory; the buried conductive lines 105 of all the dual vertical channel transistors on each cell column are integrally formed to serve as a bit line of the integrated circuit memory. A second trench 101b extending along the second direction is disposed between two adjacent cell columns, the second trench 101b exposes sidewalls of all vertical fins 1001 of the dual vertical channel transistors on the two adjacent cell columns extending along the second direction, a bit line of the integrated circuit memory is filled in the second trench 101b, and the bit line is electrically connected to the second source/drain regions 107a of all the dual vertical channel transistors on the cell column on one side of the second trench 101 b.
In the method for manufacturing an integrated circuit memory according to the present invention, while forming the first trench 101a, an isolation trench 101e between the dual vertical channel transistors in two adjacent cell rows is further formed in the semiconductor substrate 100, the isolation trench 101e extends along the first direction and exposes the outer sidewalls of the vertical fins 1001 of all the dual vertical channel transistors in two adjacent cell rows along the first direction, so as to achieve isolation between the dual vertical channel transistors in two adjacent cell rows, and when filling the first gate structure 112 in the first trench 101a above the second source/drain region 107a, the second gate structure 113 is also filled in the isolation trench 101e, that is, the second gate structures 113 of the dual vertical channel transistors corresponding to the same side in the isolation trench 101e are connected together, to form a dummy word line for the integrated circuit memory.
It will be apparent to those skilled in the art that various changes and modifications may be made in the invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (15)
1. A dual vertical channel transistor, comprising:
the semiconductor substrate is provided with a vertical fin extending along a second direction, the vertical fin is provided with a first groove extending along a first direction, a second source/drain region is formed in the fin at the bottom of the first groove, and a first source/drain region is formed in the fin at the top of the side wall of the first groove; and
and the first gate structure is filled in the first trench and extends along the first direction, the first gate structure is positioned above the second source/drain region, and the side wall of the first gate structure and the exposed side wall of the first source/drain region of the first trench are at least partially overlapped in space in height.
2. The dual vertical channel transistor of claim 1, wherein the semiconductor substrate further has an isolation trench extending along the first direction and exposing sidewalls of the vertical fin along the first direction for achieving device isolation between the dual vertical channel transistor and an adjacent element, the isolation trench having an inner surface filled with a second gate structure for coupling a substrate voltage to the dual vertical channel transistor.
3. The double vertical channel transistor of claim 1, wherein an isolation region is further disposed in a bottom portion of the vertical fin, the isolation region extending along the second direction, and a portion extending at a bottom portion of the first trench is located below the second source/drain region, and a portion of the isolation region extending at both sides of the first trench at least partially spatially overlaps the second source/drain region in height.
4. The dual vertical channel transistor of claim 1, wherein the first gate structure comprises a gate dielectric layer overlying sidewalls and a bottom surface of the first trench, a gate electrode layer filling the first trench with the gate dielectric layer and having a top surface lower than a top surface of the first source/drain region, and a gate isolation layer filling the first trench above the gate electrode layer.
5. The dual vertical channel transistor of claim 1, wherein the semiconductor substrate further has a second trench, the second trench extends along the second direction and exposes the sidewall of the vertical fin, an end of the first trench along the first direction extends to the second trench so that the first trench and the second trench communicate on the sidewall of the second trench, and a bottom surface of the first trench is higher than a bottom surface of the second trench to expose sidewalls of the fin at the bottom of the first trench including the second source/drain region into the second trench, an embedded conductive line is embedded in the second trench, and an end of the first trench in the first direction extends to a sidewall of the embedded conductive line, so that the embedded conductive line is electrically connected to the second source/drain region.
6. The dual vertical channel transistor of claim 5, further comprising a first dielectric layer in the second trench, the buried conductive line on the first dielectric layer, a portion of the first dielectric layer on a bottom surface of the buried conductive line extending to a boundary with the second source/drain region such that the bottom surface of the buried conductive line is not lower than the bottom surface of the second source/drain region.
7. The dual vertical channel transistor of claim 6, further comprising a second dielectric layer overlying the buried conductive line in the second trench and exposing a portion of the first gate structure extending from the first trench into the second trench.
8. The dual vertical channel transistor of claim 5, further comprising a conductive contact structure formed in the second trench and disposed between the buried conductive line and the second source/drain region, one sidewall of the conductive contact structure being in surface contact with a sidewall of the second source/drain region, another sidewall of the conductive contact structure being in surface contact with a sidewall of the buried conductive line, a bottom surface of the conductive contact structure being insulated from a surface of the semiconductor substrate at a bottom of the second trench.
9. A method for manufacturing a double vertical channel transistor comprises the following steps:
providing a semiconductor substrate, and etching the semiconductor substrate along a first direction and a second direction respectively to form a vertical fin extending along the second direction and a second groove, wherein the second groove exposes a side wall of the vertical fin extending along the second direction, a first groove extending along the first direction is arranged in the vertical fin, an end part of the first groove along the first direction extends to the second groove, so that the first groove and the second groove are communicated on the side wall of the second groove, and the bottom surface of the first groove is higher than the bottom surface of the second groove;
forming an embedded conductive line in the second trench, the embedded conductive line extending along a second direction and electrically connected to the fins at the bottom of the first trench;
forming a first source/drain region and a second source/drain region in one step by adopting the same ion implantation process, wherein the first source/drain region is formed in the fin at the top of the side wall of the first groove, and the second source/drain region is formed in the fin at the bottom of the first groove; and the number of the first and second groups,
and filling a first gate structure in the first groove above the second source/drain region.
10. The method of claim 9, wherein prior to forming the first source/drain region and the second source/drain region, a well ion implantation process is performed to implant ions that are inverse to the second source/drain region into the bottom of the vertical fin to form an isolation region, wherein the isolation region extends along the second direction, a portion of the isolation region extending at the bottom of the first trench is located below the second source/drain region, and portions of the isolation region extending at both sides of the first trench are at least partially spatially overlapped with the second source/drain region in height.
11. The method of claim 9, wherein a first dielectric layer is filled in the second trench before the buried conductive line is formed, the buried conductive line is located on the first dielectric layer, and the buried conductive line is isolated from the semiconductor substrate by the first dielectric layer.
12. The method of claim 9, wherein forming the first gate structure comprises:
depositing a second dielectric layer on the surface of the semiconductor substrate with the first source/drain region and the second source/drain region, wherein the second dielectric layer fills the second groove above the embedded type conducting wire;
etching the second dielectric layer to expose the side wall and the bottom surface of the first groove above the second source/drain region, and forming a gate dielectric layer on the side wall and the bottom surface of the first groove;
filling a gate electrode layer in the first groove with the gate dielectric layer, wherein the side wall of the gate electrode layer is at least partially overlapped with the side wall of the first source/drain region in space in height; and;
and filling a gate isolation layer in the first groove above the gate electrode layer, wherein the gate isolation layer fills the first groove above the gate electrode layer.
13. The method of claim 9, wherein an isolation trench is formed in the semiconductor substrate while the first trench is formed by etching the semiconductor substrate in a first direction, the isolation trench extending in the first direction and exposing sidewalls of the vertical fins in the first direction to achieve device isolation between the double vertical channel transistor and adjacent elements; and filling a first gate structure in the first trench above the second source/drain region, and simultaneously filling a second gate structure in the isolation trench.
14. An integrated circuit memory, comprising: a plurality of the double vertical channel transistors of any one of claims 1 to 8, all of the double vertical channel transistors being arranged in an array in rows and columns of cells along a first direction and a second direction; a second trench extending along the second direction is arranged between two adjacent cell columns, the second trench exposes sidewalls of vertical fins of all the double vertical channel transistors on the two adjacent cell columns extending along the second direction, a bit line of the integrated circuit memory is filled in the second trench, and the bit line is electrically connected with second source/drain regions of all the double vertical channel transistors on the cell column on one side of the second trench; the end of the first groove of all the double vertical channel transistors on each unit row along the first direction extends to the second groove and is communicated with the second groove on the side wall of the second groove, so that the first gate structures of all the double vertical channel transistors on each unit row are connected into a whole to be used as a word line of the integrated circuit memory; the isolation trench extending along the first direction is further arranged between every two adjacent unit rows, the isolation trench exposes all the vertical fins of the double-vertical-channel transistors on the two adjacent unit rows along the outer side wall of the first direction and is used for realizing isolation between the double-vertical-channel transistors on the two adjacent unit rows, the isolation trench and the first trench are formed by the same process, the isolation trench is filled with the second gate structures of the double-vertical-channel transistors on the corresponding side, the second gate structures of the double-vertical-channel transistors on the same side in the isolation trench are connected into a whole to serve as a virtual word line of the integrated circuit memory, and the virtual word line and the word line are formed in the same process.
15. A method of fabricating an integrated circuit memory, comprising: preparing a plurality of double vertical channel transistors by using the method for preparing double vertical channel transistors according to any one of claims 9 to 13, wherein all the double vertical channel transistors are arranged in an array along a first direction and a second direction according to unit rows and unit columns, and an isolation trench extending along the first direction is further formed in the semiconductor substrate while the first trench is formed, so as to realize isolation between the double vertical channel transistors on two adjacent unit rows, and a first gate structure is filled in the first trench above the second source/drain region while a second gate structure is filled in the isolation trench; a second trench extending along the second direction is arranged between two adjacent cell columns, the second trench exposes sidewalls of vertical fins of all the double vertical channel transistors on the two adjacent cell columns extending along the second direction, a bit line of the integrated circuit memory is filled in the second trench, and the bit line is electrically connected with second source/drain regions of all the double vertical channel transistors on the cell column on one side of the second trench; the end of the first groove of all the double vertical channel transistors on each unit row along the first direction extends to the second groove and is communicated with the second groove on the side wall of the second groove, so that the first gate structures of all the double vertical channel transistors on each unit row are connected into a whole to be used as a word line of the integrated circuit memory; the isolation trench exposes the outer side wall of the vertical fin along the first direction of all the double vertical channel transistors on the two adjacent unit rows, and the second gate structures of the double vertical channel transistors corresponding to the same side in the isolation trench are connected into a whole to be used as a virtual word line of the integrated circuit memory.
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