CN110896075B

CN110896075B - Integrated circuit memory and preparation method thereof

Info

Publication number: CN110896075B
Application number: CN201811068565.8A
Authority: CN
Inventors: 不公告发明人
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2018-09-13
Filing date: 2018-09-13
Publication date: 2022-02-08
Anticipated expiration: 2038-09-13
Also published as: CN110896075A

Abstract

The invention provides an integrated circuit memory and a preparation method thereof, wherein the preparation method adopts an inclined ion implantation process with an inclined angle to ensure that two adjacent sacrificial structures have different etching selectivity due to different doping concentrations, so as to form mask openings with different depths in a mask material layer, and a semiconductor substrate is etched by taking the mask material layer as a mask, so that grooves with different depths can be obtained, and further adjacent embedded word lines with embedded depths can be formed, so that the coupling effect between the adjacent embedded word lines can be restrained and alleviated through the height difference between the bottom surfaces of the adjacent embedded word lines, and the device efficiency and the reliability are improved.

Description

Integrated circuit memory and preparation method thereof

Technical Field

The invention relates to the technical field of integrated circuit manufacturing, in particular to an integrated circuit memory and a preparation method thereof.

Background

Dynamic Random Access Memory (DRAM) is a well-known semiconductor Memory device, and is widely used in various electronic devices. A Dynamic Random Access Memory (DRAM) is composed of a plurality of repetitive memory cells (cells), each of which is mainly composed of a transistor and a capacitor operated by the transistor, and the memory cells are arranged in an array form, and each of the memory cells is electrically connected to a Bit Line (BL) through a Word Line (WL). In order to increase the density of Dynamic Random Access Memory (DRAM) devices to increase the operating speed of the devices and meet the demands of consumers for miniaturized electronic devices, the design of the transistor channel region length in the DRAM devices has been continuously shortened recently. However, the transistor has serious problems of short channel effect (short channel effect) and on current (on current) drop.

One known solution is to change a horizontal Transistor structure in a Dynamic Random Access Memory (DRAM) to a vertical Buried Channel Array Transistor (BCAT) structure, and the structure of the Dynamic Random Access Memory (DRAM) having the Buried Channel Array Transistor (BCAT) is shown in fig. 1A and 1B and includes: the semiconductor device comprises a semiconductor substrate 100, a plurality of Shallow Trench Isolation Structures (STIs) 101, a plurality of active regions 102 (arranged in an array) for manufacturing Buried Channel Array Transistors (BCATs), and buried word lines (i.e., gates of the BCATs) 103 intersecting the active regions 102, wherein the buried word lines 103 are buried in U-shaped longitudinal grooves extending in the length direction (i.e., word line direction) and penetrating through the active regions in the direction, and the groove depths of the U-shaped longitudinal grooves are uniform (i.e., all the buried word lines 103 are arranged at equal depths, as shown by dotted lines in fig. 1B). Since the current needs to flow between the source region (not shown in the active region 102 on one side of the buried word line 103) and the drain region (not shown in the active region 302 on the other side of the buried word line 103) along the U-shaped longitudinal trench portion by detour, the effective channel length is increased, which reduces the area occupied by the transistor in each memory cell and suppresses the short channel effect. In addition, this structure can increase the number of bits in the same area, i.e., increase the storage density.

However, due to the miniaturization of semiconductor devices, the memory cells of a Dynamic Random Access Memory (DRAM) are spaced closer to each other, which often results in a very strong word-line coupling effect (word-line coupling), i.e., a severe coupling effect is easily generated between two adjacent buried word lines 103 passing through each active region 102, which increases coupling noise, affects device performance and reliability, and even causes data access errors of the DRAM.

Therefore, it is desirable to design a new integrated circuit memory and a method for manufacturing the same to solve the above-mentioned problems.

Disclosure of Invention

The invention provides an integrated circuit memory and a manufacturing method thereof, which can improve the coupling effect between adjacent embedded word lines and improve the device efficiency and reliability.

To solve the above technical problem, the present invention provides a method for manufacturing an integrated circuit memory, comprising the following steps:

providing a semiconductor substrate, wherein a sacrificial layer is formed on the semiconductor substrate, and a plurality of auxiliary lines are formed on the sacrificial layer and extend along a first direction;

forming side walls on the side walls of the auxiliary lines, wherein the side walls facing each other between the adjacent auxiliary lines define first spaced openings;

removing the auxiliary lines, and etching the sacrificial layer by using the side walls as masks to form a plurality of sacrificial structures extending along the first direction, wherein a second interval opening is formed between two side walls corresponding to the same auxiliary line side wall, and the opening size of the second interval opening is larger than that of the first interval opening;

doping the sacrificial structures by adopting an inclined ion implantation process so as to enable the adjacent sacrificial structures to have different doping concentrations;

filling a mask material layer between the adjacent sacrificial structures and exposing the top surfaces of the sacrificial structures;

etching the sacrificial structures to form mask openings extending into the mask material layer, wherein the depths of the mask openings formed by the adjacent sacrificial structures are different;

etching the residual sacrificial structure by taking the mask material layer as a mask and extending and etching the residual sacrificial structure into the semiconductor substrate to form grooves corresponding to the mask openings, wherein the depths of the adjacent grooves are different; and the number of the first and second groups,

and forming embedded word lines in the grooves, wherein the embedded word lines are asymmetrically arranged in the adjacent grooves.

Optionally, the lateral size of the side wall is 12nm to 18nm, the size of the second spaced opening is 90nm to 100nm, and the size of the first spaced opening is 20nm to 30 nm.

Optionally, the sacrificial structure is doped by using a same tilted ion implantation process, and an included angle between an implantation direction of the same tilted ion implantation process and the surface of the semiconductor substrate is 5 ° to 85 ° or 95 ° to 175 °.

Optionally, the implanted ions of the tilted ion implantation process include at least one of N-type ions, P-type ions, carbon ions, fluorine ions, nitrogen ions, hydrogen ions, oxygen ions, and metal ions.

Optionally, the depth difference between the adjacent grooves is 5nm to 200 nm.

Optionally, the step of forming the buried word line includes:

forming a gate dielectric layer on the surface of the groove;

filling a conductive layer in the groove, wherein the top surface of the conductive layer is lower than the surface of the semiconductor substrate, and the depth difference between the conductive layers in the adjacent grooves is 80 nm-170 nm; and

and filling a grid isolation layer in the groove, wherein the grid isolation layer is laminated on the conductive layer and fills the groove.

The present invention also provides an integrated circuit memory, comprising:

the semiconductor device comprises a semiconductor substrate, wherein grooves with different depths are formed in the semiconductor substrate; and the number of the first and second groups,

and the embedded word lines are embedded in the grooves, and the embedded word lines are asymmetrically arranged in the adjacent grooves.

Optionally, the depth difference between adjacent grooves is 5nm to 200 nm.

Optionally, the size of the transverse opening of each groove is 12nm to 18nm, and the distance between every two adjacent grooves is 20nm to 30 nm.

Optionally, the embedded word lines include gate dielectric layers covering the sidewalls and the bottom surfaces of the recesses, and conductive layers and gate isolation layers sequentially stacked in the recesses having the gate dielectric layers from bottom to top, and a depth difference between the conductive layers of adjacent embedded word lines is 80nm to 170 nm.

Compared with the prior art, the technical scheme of the invention has the following beneficial effects:

1. the method for preparing the integrated circuit memory comprises the steps of adopting an inclined ion implantation process with an inclined angle, enabling one sacrificial structure in adjacent sacrificial structures to be shielded by the other sacrificial structure in the inclined ion implantation process and doped slightly or not doped, enabling the two sacrificial structures to have different doping concentrations and different etching selectivity, and accordingly forming mask openings with different depths in a mask material layer due to the fact that the sacrificial structure etched slowly is remained when the sacrificial structure etched quickly is etched, obtaining a first groove and a second groove with different groove depths when the mask material layer is used as a mask and continuously etched downwards to a semiconductor substrate, and further forming embedded word lines with different depths embedded in the first groove and the second groove, by the height difference (i.e., the gap) between the bottom surfaces of the two buried word lines, the coupling effect (i.e., WL-WL coupling effect) between the adjacent buried word lines can be restrained and reduced, and the device performance and reliability can be improved.

2. The integrated circuit memory of the invention is provided with the embedded word lines with different depths embedded in the semiconductor substrate, and the coupling effect (namely WL-WL coupling effect) between the adjacent embedded word lines can be restrained and lightened through the height difference (namely the gap) between the bottom surfaces of the adjacent embedded word lines, thereby improving the device efficiency and the reliability.

Drawings

FIG. 1A is a schematic diagram of a top view of a conventional DRAM with a BCAT.

FIG. 1B is a cross-sectional structure view of the DRAM of FIG. 1A taken along line LL' (only the structure at one active region is shown).

FIG. 2 is a flow chart of a method for fabricating an integrated circuit memory according to an embodiment of the invention.

Fig. 3A to 3I are schematic cross-sectional views of device structures in the method for manufacturing the integrated circuit memory shown in fig. 2.

Wherein the reference numbers are as follows:

100. 300-a semiconductor substrate;

101. 301-shallow trench isolation structures;

102. 302-an active region;

x-a second direction;

y-a first direction;

302 a-a first groove;

302 b-a second groove;

103. 315-buried word line;

303-pad oxide layer;

304-a hard mask layer;

305-a cover layer;

306-a first etch stop layer;

307-sacrificial layer;

308-a second etch stop layer;

309-auxiliary line;

310-side wall material layer;

310 a-side wall;

310 b-a first spaced opening;

310 c-a second spaced opening;

307a, 307 b-sacrificial structures;

307c — remaining sacrificial structures;

311-a layer of masking material;

311 a-first mask opening;

311 b-second mask opening;

312-a gate dielectric layer;

312 a-a gate dielectric layer in the first recess and the second recess;

313-a conductive layer; 314-a gate isolation layer;

314 a-a gate isolation layer in the first and second recesses;

d1-the sum of the line width of one auxiliary line and the opening size of the interval between two adjacent auxiliary lines;

d2 — line width of auxiliary line, opening size of second spaced opening 310 c;

d3 — opening size of the space between two adjacent auxiliary lines;

d31-line width of the sidewall 310 a;

d32 — opening size of first spaced openings 310 b;

d4-the difference in groove depth (gap) of the first groove 302a and the second groove 302 b.

Detailed Description

As mentioned above, the electrical characteristics of the Buried Channel Array Transistor (BCAT) in a Dynamic Random Access Memory (DRAM) may vary according to the depth from the upper surface of the semiconductor substrate to the bottom surface of its buried word line, for example, the magnitude of the coupling effect between two adjacent buried word lines in a Dynamic Random Access Memory (DRAM) may vary according to the depth.

Based on the above, the invention provides an integrated circuit memory and a manufacturing method thereof, wherein two adjacent embedded word lines are asymmetrically arranged, a certain height difference is formed between the bottom surfaces of the two embedded word lines, and the height difference is utilized to restrict and reduce the coupling effect between the two adjacent embedded word lines, so that the device efficiency and the reliability are improved.

The integrated circuit memory and the method for manufacturing the integrated circuit memory according to the present invention will be described in detail with reference to fig. 2, fig. 3A to fig. 3H and the following embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.

Referring to fig. 2, the present invention provides a method for manufacturing an integrated circuit memory, comprising the following steps:

s1, providing a semiconductor substrate, wherein a sacrificial layer is formed on the semiconductor substrate, and a plurality of auxiliary lines are formed on the sacrificial layer and extend along a first direction to be formed;

s2, forming side walls on the side walls of the auxiliary lines, and defining first interval openings between the side walls facing each other between the adjacent auxiliary lines;

s3, removing the auxiliary lines, and etching the sacrificial layer by using the side walls as masks to form a plurality of sacrificial structures extending along the first direction, wherein a second interval opening is formed between two side walls corresponding to the same auxiliary line side wall, and the opening size of the second interval opening is larger than that of the first interval opening;

s4, doping the sacrificial structures by adopting an inclined ion implantation process so that two adjacent sacrificial structures have different doping concentrations;

s5, filling a mask material layer between the adjacent sacrificial structures and exposing the top surfaces of the sacrificial structures;

s6, etching the sacrificial structures to form mask openings extending into the mask material layer, wherein the depths of the mask openings formed by the adjacent sacrificial structures are different;

s7, with the mask material layer as a mask, etching the remaining sacrificial structures and extending and etching the sacrificial structures into the semiconductor substrate to form grooves corresponding to the mask openings, wherein the depths of the adjacent grooves are different; and the number of the first and second groups,

s8, forming buried word lines in the grooves, wherein the buried word lines are asymmetrically disposed in the adjacent grooves.

First, step S1 is executed, and referring to fig. 2 and fig. 3A specifically, a semiconductor substrate 300 is provided, where the semiconductor substrate 300 may be any substrate known to those skilled in the art for carrying semiconductor integrated circuit components, such as a silicon-on-insulator (SOI) substrate, bulk silicon (bulk silicon) substrate, germanium substrate, silicon germanium substrate, gallium arsenide substrate, or germanium-on-insulator substrate. A plurality of active regions 302 for forming a Buried Channel Array Transistor (BCAT) and a shallow trench isolation structure 301 for isolating adjacent active regions 302 may be defined in the semiconductor substrate 300, where the active regions 302 may be fin-type solid structures or planar structures; the shallow trench isolation structure 301 may isolate all the active regions 302 in an array, and the shallow trench isolation structure 301 may include a shallow trench (not shown) in the semiconductor substrate 300 and a dielectric material filling the shallow trench, where the dielectric material may include a liner oxide layer (line oxide) formed by a thermal oxidation process and covering the shallow trench and silicon dioxide located on a surface of the liner oxide layer and filling the shallow trench, thereby improving an isolation performance of the shallow trench isolation structure 301. In this embodiment, the top surface of the shallow trench isolation structure 301 is higher than the top surface of the semiconductor substrate 300, and the specific forming process includes:

referring to fig. 3A, a shallow trench is formed in the semiconductor substrate 300, and specifically, a pad oxide layer 303 is formed on the surface of the semiconductor substrate 300 by a thermal oxidation process; then, a silicon nitride hard mask layer (not shown) is formed through a chemical vapor deposition process, and a patterned photoresist layer (not shown) is further formed on the silicon nitride hard mask layer through photoresist coating, exposing, developing and other photolithography processes, wherein the patterned photoresist layer covers the active region 302 and the layers above the active region and exposes the silicon nitride hard mask layer above the semiconductor substrate 300 serving as an isolation region between the active regions 302; then, with the patterned photoresist layer as a mask, performing an etching process on the exposed silicon nitride hard mask layer, the pad oxide layer 301 below the exposed silicon nitride hard mask layer, and the semiconductor substrate 300 with a partial depth to form the shallow trench in the semiconductor substrate 300 between the active regions 302, wherein the etching process may be dry etching; then, removing the patterned photoresist layer;

step two, with continued reference to fig. 3A, forming a liner oxide (not shown) on the sidewalls and bottom surface of the shallow trench; specifically, a liner oxide layer can be formed on the side wall and the bottom surface of the shallow trench through a vapor deposition process or a thermal oxidation process;

step three, continuing to refer to fig. 3A, filling the shallow trench with silicon dioxide on the liner oxide layer, specifically, firstly, depositing silicon dioxide on the surface of the shallow trench and the surface of the silicon nitride hard mask layer by using processes such as chemical vapor deposition and the like until the shallow trench is filled with the silicon dioxide; then, performing top surface planarization on the silicon dioxide by adopting a chemical mechanical planarization process until the top surface of the silicon dioxide is flush with the top surface of the silicon nitride hard mask layer to form a shallow trench isolation structure 301; and then, removing the silicon nitride hard mask layer by adopting a wet etching process and other processes. Further, after depositing silicon dioxide, or planarizing the top surface of the silicon dioxide, or removing the silicon nitride hard mask layer, the method further includes performing densification (densification) on the silicon dioxide by using the high-temperature thermal annealing, high-energy light excitation process such as Ultraviolet (UV) or laser (laser), etc. to increase the compactness of the dielectric material, ensure the isolation effect of the shallow trench isolation structure 301, andthe mechanical strength is enhanced. The process temperature of the high-temperature thermal annealing process is, for example, 800 ℃ to 1200 ℃, and ozone (O) can be further introduced when the high-temperature thermal annealing process is performed₃) And/or a strongly reactive gas such as carbon monoxide (CO).

In addition, in step S1, after the shallow trench isolation structure 301 is formed, a well region (not shown) may be formed in the active region 302 by an ion implantation process and further combined with an annealing activation process, wherein a doping type of the well region is determined by a conductivity type of a BCAT transistor to be formed, for example, in the present embodiment, if the formed BCAT transistor is an N-type transistor, the well region is a P-type doping region. The doping depth of the well region can be adjusted according to actual conditions.

It should be noted that the pad oxide layer 303 may protect the semiconductor substrate 300 and the active region 302 during the formation of the shallow trench isolation structure 301, and the pad oxide layer 303 may remain to be used as a protection layer for the top surfaces of the semiconductor substrate 300 and the active region 302 in the subsequent processes.

Next, with reference to fig. 3A, a hard mask layer 304, a capping layer 305, a first etching stop layer 306, a sacrificial layer 307, a second etching stop layer 308 and an auxiliary line 309 are sequentially formed on the surface of the shallow trench isolation structure 301 and the pad oxide layer 303, and the specific process includes:

firstly, forming a hard mask layer 304, a covering layer 305 and a first etching stop layer 306 on the surfaces of the pad oxide layer 303 and the shallow trench isolation structure 301 in sequence, specifically, firstly, forming the hard mask layer 304 on the surfaces of the shallow trench isolation structure 301 and the pad oxide layer 303 by processes such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD) or Atomic Layer Deposition (ALD), and the like, wherein the hard mask layer 304 is made of at least one of silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, metal nitride, metal oxide and metal carbide, preferably silicon nitride (SiN), and the silicon nitride material is easy to obtain, low in cost, mature in manufacturing method and has a higher etching selection ratio with the pad oxide layer 303; next, a covering layer 305 may be formed on the surface of the hard mask layer 304 through a spin coating process, a vacuum evaporation process, a sputtering deposition process, a chemical vapor deposition process, or the like, where the covering layer 305 is mainly used to provide a flat process surface for the subsequent formation of the sacrificial layer 307 and to provide a high etching selectivity and a low Line Edge Roughness (LER) to improve the transfer effect of the subsequent pattern into the hard mask layer 304, and the material of the covering layer 305 may include at least one of an undoped silicon dioxide-based material, a doped silicon dioxide-based material, an organosilicate glass, a porous silicate glass, a silicon nitride-based material, a silicon oxynitride-based material, a silicon carbide-based material, an organic polymer material, amorphous carbon (α -carbon), and a silicon-containing anti-reflective coating material; then, a first etch stop layer 306 for providing an etch stop point of the etching sacrificial layer 307 may be formed on the surface of the capping layer 305 by a process of Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or the like, and the first etch stop layer 306 may be selected from at least one of silicon nitride (SiNx), silicon carbide (SiC), silicon oxynitride (SiON), silicon oxycarbide (SiOC), and silicon carbonitride (SiCN).

Step two, forming a sacrificial layer 307 and a second etch stop layer 308 on the surface of the first etch stop layer 306 in sequence, specifically, depositing the sacrificial layer 307 and the second etch stop layer 308 on the surface of the first etch stop layer 306 in sequence by using a Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), or Atomic Layer Deposition (ALD), and the like, since the capping layer 305 provides a flat process surface, the thickness of the formed sacrificial layer 307 can be made uniform in the whole, which is beneficial for improving the appearance of a subsequently formed sacrificial structure, the material of the sacrificial layer 307 can be any suitable material capable of changing the etching selectivity by ion doping, and can include at least one of polysilicon, amorphous silicon, monocrystalline silicon, silicon germanium, silicon carbide, a metal and a metal compound, wherein the metal compound is a metal nitride, a metal oxide, a silicon carbide, a metal oxide, and a metal oxide, The metal carbide, the metal silicide, the metal boride or the metal phosphide, wherein the metal can be a pure metal or an alloy, the pure metal is copper, aluminum, gold, silver, tantalum, titanium, nickel or tungsten, and the alloy comprises at least one of copper, aluminum, gold, silver, tantalum, titanium, nickel and tungsten; the sacrificial layer 307 is preferably polysilicon, which has the advantages of easily available materials, low cost, mature manufacturing method, and capability of changing the etching selection ratio through an ion implantation process. The second etch stop layer 308 may be selected from at least one of silicon nitride (SiNx), silicon carbide (SiC), silicon oxynitride (SiON), silicon oxycarbide (SiOC), and silicon carbonitride (SiCN), and the second etch stop layer 308 may provide an etch stop point for the process of the subsequently formed auxiliary line 309 and the sidewall 310a, preferably silicon oxynitride, which may be subsequently easily removed by a wet etching process.

Step three, forming a plurality of auxiliary lines 309 on the surface of the second etch stop layer 308, specifically, forming a plurality of auxiliary lines 309 extending in the first direction (i.e., the word line direction) on the surface of the second etch stop layer 308 through a series of photolithography processes such as photoresist coating, exposure using a word line mask (WL mask), development, and the like, wherein a line width D2 of the auxiliary lines 309 is greater than an opening dimension D3 of a space between two adjacent auxiliary lines 309, and a sum of D2 and D3 may be equal to a dimension D1(pitch) of 1 photolithography pattern in the word line mask, so as to ensure that after the subsequent formation of the side walls 310a, a difference exists in opening dimensions of the space opening between different adjacent side walls 310a, that is, a final purpose is to achieve a difference in space dimensions between a certain side wall and two adjacent side walls on both sides, that a size of D3 is equal to a sum of a line width D31 of two subsequently formed side walls 310a and an opening dimension D32 of the first space opening 310b .

In addition, in order to improve the forming effect of the auxiliary lines 309, in other embodiments of the present invention, an anti-reflection layer (not shown) may be further formed on the surface of the second etch stop layer 308 before the photoresist is coated, which may be used to reduce the reflected light and standing wave when the auxiliary lines 309 are formed and protect the layers therebelow from the light radiation when the auxiliary lines 309 are formed.

Referring to fig. 3B and 3C, in step S2, first, a sidewall material layer 310 may be deposited on the surfaces of the second etch stop layer 308 and the auxiliary line 309 by Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or the like, where the material of the sidewall material layer 310 is selected as long as the material has a higher etching selectivity ratio with respect to the auxiliary line 309 and the second etch stop layer 308, for example, when the auxiliary line 309 is a photoresist and the second etch stop layer 308 is silicon oxynitride, the material of the sidewall material layer 310 may be silicon nitride, silicon oxide, titanium nitride, or other metal compounds; next, the sidewall material layer 310 may be etched by a dry etching process such as plasma etching, so as to form a sidewall 310a on the sidewall of the auxiliary line 309, a line width D31 of the sidewall 310a determines line widths of the first groove 302a and the second groove 302b formed subsequently, that is, a line width of the embedded word line 315 formed subsequently, a line width D31 of the sidewall 310a may be 12nm to 18nm, the sidewall 310a facing each other between the adjacent auxiliary lines 309 defines a first spaced opening 310b, a line width D32 of the first spaced opening 310b determines a spacing distance between the first groove 302a and the second groove 302b formed subsequently in a horizontal direction, a line width D32 of the first spaced opening 310b may be 20nm to 30nm, wherein 2D 31+ D32 is D3.

Referring to fig. 3D and 3E, in step S3, first, the auxiliary line 309 may be removed by selecting a suitable removal process according to the material of the auxiliary line 309, for example, when the auxiliary line 309 is made of photoresist, an oxygen ion ashing process may be used to remove the auxiliary line 309, a second spaced opening 310c is formed between two sidewalls 310a corresponding to the sidewalls of the same auxiliary line 309, and the opening size of the second spaced opening 310c (i.e., D2) is larger than the opening size of the first spaced opening 310b (i.e., D32); then, with the sidewall 310a as a mask, the second etching stop layer 308 and the sacrificial layer 307 are sequentially etched by dry etching and other processes, the etching stops on the surface of the first etching stop layer 306, and at this time, the pattern in the sidewall 310a is transferred into the sacrificial layer 307, so that a plurality of

sacrificial structures

307a and 307b extending along the first direction are formed.

With continued reference to fig. 3E, in step S4, the

sacrificial structures

307a and 307b are doped by an oblique ion implantation process, an implantation angle of the oblique ion implantation process may be determined according to the stacking height of the sacrificial structure 307a to the sidewall 310a thereon and the opening dimension D32 of the first spaced opening 310b, as long as one of the two

sacrificial structures

307a and 307b (e.g. 307a) on both sides under the first spaced opening 310b can shield the other sacrificial structure (e.g. 307b) during the oblique ion implantation, so that the two

sacrificial structures

307a and 307b under the first spaced opening 310b have different doping concentrations after the tilted ion implantation, for example, an included angle between the implantation direction of the tilted ion implantation process and the surface of the semiconductor substrate 300 is 5 ° to 85 ° or 95 ° to 175 °. Furthermore, the material of the implanted ions of the tilted ion implantation process needs to be selected according to the material of the sacrificial layer 307, and needs to be satisfied to enable the

sacrificial structures

307a and 307b to have different etching selectivity due to different doping concentrations, for example, when the material of the sacrificial layer 307 includes at least one of polysilicon, amorphous silicon, monocrystalline silicon, silicon germanium, silicon carbide, and metal compounds (which are metal nitrides, metal oxides, metal carbides, metal silicides, metal borides, or metal phosphides), the implanted ions of the tilted ion implantation process include at least one of N-type ions (such as phosphorus, arsenic, antimony, etc.), P-type ions (such as boron, gallium, indium, etc.), carbon ions, fluorine ions, nitrogen ions, hydrogen ions, oxygen ions, and metal ions (such as cobalt, nickel, manganese, copper, tungsten, titanium, tantalum, etc.). In addition, the implanted ions and the implanted concentration of the tilted ion implantation process may determine the etching selection ratio of the

sacrificial structures

307a and 307b, and further determine the depth difference between the finally formed adjacent grooves (i.e., the first groove 302a and the second groove 302b), so that after the implanted ion species of the tilted ion implantation process is determined, the implanted concentration may be determined according to the depth difference between the finally formed adjacent grooves (i.e., the first groove 302a and the second groove 302 b). The etch selectivity of the

sacrificial structures

307a and 307b may increase with increasing ion doping concentration or may decrease with increasing ion doping concentration. In order to increase the density of the device as much as possible, the distance between the adjacent grooves in the same active region is 20 nm-30 nm.

Referring to fig. 3F, in step S5, first, in order to avoid difficulty in filling the adjacent sacrificial structures 307a and 307b with a high aspect ratio and avoid the influence of the existence of the sidewall 310a and the second etch stop layer 308 on the effect of forming the first groove 302a and the second groove 302b by subsequent etching, the sidewall 310a and the remaining second etch stop layer 308 may be removed by wet etching, Chemical Mechanical Planarization (CMP), and other processes; next, a mask material layer 311 may be deposited on the surfaces of the sacrificial structures 307a and 307b and the first etch stop layer 306 by using a Chemical Vapor Deposition (CVD), a Physical Vapor Deposition (PVD), or an Atomic Layer Deposition (ALD), the deposition thickness of the mask material layer 311 is sufficient to fill the gap between the adjacent sacrificial structures 307a and 307b, the material of the mask material layer 311 is required to have a higher etching selectivity than the sacrificial structures 307a and 307b and the first etch stop layer 306, for example, when the sacrificial structures 307a and 307b are made of polysilicon and the first etch stop layer 306 is made of silicon oxynitride, the material of the mask material layer 311 may include at least one of silicon nitride, silicon carbide, silicon oxycarbide (SiOC), and silicon carbonitride (SiCN); the masking material layer 311 may then be processed by an etch-back process or a chemical mechanical planarization process to expose the top surfaces of the sacrificial structures 307a, 307b to facilitate the subsequent etching of the sacrificial structures 307a, 307b, thereby filling the masking material layer between the adjacent sacrificial structures 307a, 307b and exposing the top surfaces of the sacrificial structures 307a, 307 b. In other embodiments of the present invention, when the sidewall 310a and the second etch stop layer 308 are thin, the sidewall 310a and the remaining second etch stop layer 308 may not be removed first, but the mask material layer 311 is deposited directly on the surfaces of the sidewall 310a, the second etch stop layer 308, the

sacrificial structures

307a and 307b, and the first etch stop layer 306, and then the sidewall 310a, the remaining second etch stop layer 308, and the excess mask material layer 311 may be removed by an etching process or a chemical mechanical planarization process, so that the remaining mask material layer 311 is filled between the adjacent

sacrificial structures

307a and 307b, and the top surfaces of the

sacrificial structures

307a and 307b are exposed, thereby facilitating the subsequent etching of the

sacrificial structures

307a and 307 b.

Referring to fig. 3G, in step S6, the

sacrificial structures

307a, 307b may be etched by using a dry etching process or a wet etching process, because the

sacrificial structures

307a, 307b are doped with ions to different degrees in step S4, so that the

sacrificial structures

307a, 307b in this step generate different etching selectivities due to the difference of the ion doping concentrations, that is, one sacrificial structure (for example, the sacrificial structure 307a with a higher doping concentration) in two adjacent

sacrificial structures

307a, 307b is etched faster, and the other sacrificial structure (for example, the sacrificial structure 307b with a lower doping concentration) is etched slower, so that, when the sacrificial structure with a faster etching speed (for example, the sacrificial structure 307a with a higher doping concentration) is completely etched away, a first mask opening 311a extending to the bottom surface of the mask material layer is formed at the position of the sacrificial structure with a faster etching speed, at this time, the sacrificial structure (for example, the sacrificial structure 307b with a smaller doping concentration) etched slowly still remains, i.e., a second mask opening 311b may be formed above the remaining sacrificial structure 307c, so that mask openings with different depths may be formed in the mask material layer 311. It should be understood that "etch faster" herein means that the sacrificial structure 307a is considered to etch faster and the sacrificial structure 307b is considered to etch slower, as long as the etch rate of one sacrificial structure 307a of the two adjacent

sacrificial structures

307a, 307b is greater than the etch rate of the other sacrificial structure 307 b.

Referring to fig. 3H, in step S7, first, the remaining sacrificial structure 307c (i.e., the remaining portion of the sacrificial structure 307b that is etched slowly) and the first etch stop layer 306 and the capping layer 305 are sequentially etched by using the mask material layer 311 as a mask to transfer the pattern in the mask material layer 311 to the capping layer 305, where the capping layer 305 has a deeper opening (corresponding to the first mask opening 311a) that can expose the top surface of the hard mask layer 304 and a shallower opening (corresponding to the second mask opening 311b) that does not expose the top surface of the hard mask layer 304; then, in order to reduce the aspect ratio of the subsequent etching and reduce the generation of etching by-products to improve the etching effect, the mask material layer 311 and the remaining first etching stop layer 306 may be removed by an etching process or a chemical mechanical planarization process; then, with the covering layer 305 with the openings of different depths as a mask, the hard mask layer 304, the pad oxide layer 303, and the semiconductor substrate 300 (including the active region 302 and the shallow trench isolation structure 301) with a partial depth are sequentially etched, so as to form a first groove 302a corresponding to the first mask opening 311a and a second groove 302b corresponding to the second mask opening 311b in the semiconductor substrate 300, where the first groove 302a and the second groove 302b are parallel to each other and have different groove depths, and both shapes may be U-shaped. In this embodiment, the depth of the first recess 302a corresponding to the first mask opening 311a is deeper, the depth of the second recess 302b corresponding to the second mask opening 311b is shallower, and the difference between the trench depths of the first recess 302a and the second recess 302b is D4, since the electrical characteristics of the Buried Channel Array Transistor (BCAT) can be changed according to the depth from the upper surface (i.e. the top surface) of the semiconductor substrate to the bottom surface of the buried word line thereof, therefore, the setting of different depth differences of the adjacent recess members has different effects on constraining and reducing the coupling effect between the buried word lines 315 corresponding to the adjacent recesses, while ensuring the performance of the buried word lines 315 corresponding to the first recess 302a and the second recess 302b, setting the most suitable size of D4 can maximally constrain and reduce the coupling effect between the buried word lines 315 corresponding to the first recess 302a and the second recess 302b, thereby improving the electrical performance and reliability of the integrated circuit memory ultimately formed. Preferably, the groove depth difference (i.e., depth difference) D4 between the first groove 302a and the second groove 302b may be 5nm to 200nm, such as 10nm, 50nm, 100nm, etc.

In other embodiments of the present invention, in order to avoid the mask material layer 311 and the first etch stop layer 306 from causing high aspect ratio etching when the first recess 302a and the second recess 302b are formed subsequently by the stacked thickness of the covering layer 305, so as to minimize the generation of etching byproducts, and improve the profile of the formed first recess 302a and second recess 302b, referring to fig. 3H, in step S7, the remaining sacrificial structure (i.e. the remaining portion 307c of the sacrificial structure that is etched slowly), the first etch stop layer 306, the covering layer 305, and the hard mask layer 304 may be etched in sequence by using the mask material layer 311 as a mask, and the etching is stopped on the top surface of the pad oxide layer 303 to transfer the pattern in the mask material layer 311 into the hard mask layer 304, where the hard mask layer 304 also has two different depths of openings, and the opening corresponding to the first mask opening 311a is a deeper opening, the top surface of the pad oxide layer 303 can be exposed, and the opening corresponding to the second mask opening 311b is a shallower opening, which does not expose the top surface of the pad oxide layer 303; next, in order to reduce the aspect ratio of the subsequent etching and reduce the generation of etching by-products, so as to improve the etching effect, the mask material layer 311, the remaining first etching stop layer 306, and the capping layer 305 may be removed by an etching process or a chemical mechanical planarization process; then, the hard mask layer 304 is used as a mask, the pad oxide layer 303 and the semiconductor substrate 300 with a partial depth are etched, so as to form a first groove 302a and a second groove 302b with different groove depths in the semiconductor substrate 300, wherein the first groove 302a corresponds to the first mask opening 311a and the second groove 302 corresponds to the second mask opening 311 b.

Referring to fig. 3I, in step S8, the embedded word line 315 embedded in the first recess 302a and the second recess 302b is formed, which includes the following steps:

first, the pad oxide layer 303, the hard mask layer 304, and the like on the surface of the semiconductor substrate 300 may be removed by an etching process, a chemical mechanical planarization process, or the like, and further cleaned to expose clean surfaces of the active region 302 and sidewalls and bottom surfaces of the first and second grooves 302a and 302 b; then, a thermal oxidation (dry oxygen or wet oxygen) process, a chemical vapor deposition, an atomic layer deposition, or the like may be adopted, a gate dielectric layer 312 covers the sidewalls and the bottom surfaces of the active region 302 and the first and second recesses 302a and 302b, when it is finally required to form the embedded word lines 315 made of polysilicon in the first and second recesses 302a and 302b, the gate dielectric layer 312 may be made of silicon dioxide, and when it is finally required to form the embedded word lines made of metal gate material in the first and second recesses 302a and 302b, the gate dielectric layer 312 may be made of a high-K dielectric (dielectric constant K is greater than 7) such as hafnium oxide; then, a conductive layer 313 is deposited on the surface of the gate dielectric layer 312 by processes such as evaporation, electroplating, chemical vapor deposition, atomic layer deposition, and the like, the deposition thickness of the conductive layer 313 on the bottom surfaces of the first recess 302a and the second recess 302b at least reaches the thickness required by the embedded word line 315 to be formed, the conductive layer 313 may be a single-layer structure or a stacked-layer structure, the material of the conductive layer 313 may be a material for manufacturing a polysilicon gate, such as undoped polysilicon or doped polysilicon, or a material for manufacturing a metal gate, such as a metal barrier layer (TiN, etc.), a work function layer (TiAl, TiN, etc.), and a metal electrode layer (tungsten W, etc.) sequentially stacked on the surface (including the bottom surface and the sidewall) of the gate dielectric layer 312; thereafter, the conductive layer 313 on the region other than the first and second grooves 302a and 302b may be removed by an etch-back or chemical mechanical planarization process, etc., so that the conductive layer 313 is filled only in the first and second grooves 302a and 302b to serve as a conductive portion of the buried word line 315; next, a gate isolation layer 314 may be deposited on the surfaces of the gate dielectric layer 312 (including the portion 312a located in the first and second grooves 302a and 302b) and the conductive layer 313 by using a physical vapor deposition, a chemical vapor deposition, an atomic layer deposition, or the like, wherein the material of the gate isolation layer 314 includes, but is not limited to, silicon oxide, silicon nitride, and silicon oxynitride. Thereafter, the excess gate isolation layer 314 and the gate dielectric layer 312 on the surface of the active region 302 may be further removed by a chemical mechanical planarization process to form the buried word lines 315 buried in the first and

second recesses

302a and 302 b. Since the depth difference between the conductive layers 313 of the adjacent buried word lines 315 may affect the constraint effect of the coupling effect between the buried word lines 315 and the electrical characteristics of the formed Buried Channel Array Transistor (BCAT), preferably, the depth difference between the conductive layers 313 of the adjacent buried word lines 315 is preferably 80nm to 170 nm.

Then, LDD (lightly doped drain) ion implantation, Halo (Halo) ion implantation, source-drain heavily doped ion implantation, and the like may be performed on the active regions 302 on both sides of the embedded word line 315 by using the embedded word line 315 and the shallow trench isolation structure 301 as masks, so as to form source/drain regions (not shown) in the active regions 302 on both sides of the embedded word line 315, and thus, the embedded word line 315 and the source/drain regions on both sides thereof constitute a main portion of the BCAT structure. In an embodiment of the present invention, the source/drain region between two adjacent buried word lines 315 in the same active region 302 may be a drain region for electrically connecting to a capacitor to be formed later, and the source/drain region outside two adjacent buried word lines 315 in the same active region 302 may be a source region for electrically connecting to a bit line to be formed later. In another embodiment of the present invention, the source/drain region between two adjacent buried word lines 315 in the same active region 302 may be a drain region for electrical connection with a subsequently formed shared bit line, and the source/drain region outside two adjacent buried word lines 315 in the same active region 302 may be a source region for electrical connection with a subsequently formed capacitor. In other embodiments of the present invention, the gate dielectric layer 312 and the gate isolation layer 314 between the two embedded word lines 315 and on the surface of the active region 302 outside the two embedded word lines 315 may also be etched by an etching process to form an opening exposing the surface of the active region 302 for forming a source/drain region, and then LDD (lightly doped drain) ion implantation, Halo (Halo) ion implantation, source/drain heavily doped ion implantation, and the like are performed on the active region 302 between the two embedded word lines 315 and outside the two embedded word lines 315 with the remaining gate dielectric layer 312 and gate isolation layer 314 as masks to form source/drain regions in the active region 302 at both sides of the embedded word lines 315.

Therefore, the method for manufacturing the integrated circuit memory has the advantages that the ion doping concentrations in the two adjacent sacrificial structures are different by adopting the inclined ion implantation process, different etching selection ratios are generated, so that mask openings with different depths can be formed in the second mask layer, the second mask layer can be used as a mask, the semiconductor substrate is etched to form grooves with different groove depths, and further a plurality of embedded word lines with different embedding depths are formed, on one hand, the method can avoid the problem that the photoetching and etching processes are additionally added when one groove is continuously etched on the basis of the two grooves with the same depth to deepen the groove, the process is simple, and the cost is low; on the other hand, the coupling effect between two adjacent embedded word lines can be restrained and reduced by utilizing the height difference between the bottom surfaces of the two embedded word lines embedded in the adjacent grooves with different depths, and the device performance and the reliability are improved.

In addition, the present invention also provides an integrated circuit memory prepared by the above method for preparing an integrated circuit memory, referring to fig. 1 and 3I, the integrated circuit memory includes: a semiconductor substrate 300, wherein grooves (marked as a first groove 302a and a second groove 302b) with different depths are formed in the semiconductor substrate 300; and a buried word line 315 buried in the recess 302 a.

In this embodiment, the first recess 302a and the second recess 302b extend in the semiconductor substrate 300 along the word line direction, and the pitch is 20nm to 30 nm. The buried word line in the first recess 302a includes a gate dielectric layer 312a covering sidewalls and a bottom surface of the first recess 302a, and a conductive layer 313 and a gate isolation layer 314a sequentially stacked from bottom to top in the first recess 302a having the gate dielectric layer 312 a; the buried word line in the second recess 320b includes a gate dielectric layer 312a covering sidewalls and a bottom surface of the second recess 302b, and a conductive layer 313 and a gate isolation layer 314a sequentially stacked from bottom to top in the second recess 302b having the gate dielectric layer 312 a. The conductive layer 313 may have a single-layer structure or a stacked-layer structure, and the material of the conductive layer 313 may include polysilicon used to form a polysilicon gate or metal used to form a metal gate. The gate dielectric layer 312a in the first groove 302a and the second groove 302b is formed by using the same process, the conductive layer 313 in the first groove 302a and the second groove 302b is formed by using the same process, and the gate isolation layer 314a in the first groove 302a and the second groove 302b is formed by using the same process. Therefore, the process flow is simplified. The thickness of the gate dielectric layer 312a and the gate isolation layer 314a is, for example, 3nm to 500 nm. When the embedded word line 315 is a high-K metal gate structure, the gate dielectric layer 312a is a high-K dielectric, the conductive layer 313 includes a metal barrier layer, a work function layer and a metal gate electrode layer sequentially stacked on the gate dielectric layer 312a, the work function layer can realize adjustment of a work function, and further improve the performance of the embedded word line, such as titanium nitride (TiN), titanium aluminum (TiAl), titanium silicide (SiTi) or cobalt silicide (CoSi); the metal gate electrode layer is, for example, tungsten (W), aluminum (Al), or the like.

Since the depth difference between the conductive layers 313 of the adjacent buried word lines 315 may affect the constraint effect of the coupling effect between the buried word lines 315 and the electrical characteristics of the formed Buried Channel Array Transistor (BCAT), preferably, the depth difference between the conductive layers 313 of the adjacent buried word lines 315 is preferably 80nm to 170 nm.

The semiconductor substrate 300 has a plurality of active regions 302 arranged in a cell row (i.e., corresponding to a word line direction, i.e., corresponding to a first direction) and a cell column (i.e., corresponding to a bit line direction, i.e., corresponding to a second direction perpendicular to the first direction), and shallow trench isolation structures 301 are further disposed between adjacent active regions 302, i.e., all the shallow trench isolation structures 301 include a plurality of parallel and a plurality of perpendicular intersecting strips, thereby isolating all the active regions 302 into an array structure in which the cell row and the cell column are arranged. Each of the active regions 302 arranged along a word line direction (i.e., a first direction) intersects the adjacent first and

second grooves

302a and 302 b. The shallow trench isolation structure 301 may include a liner oxide layer covering sidewalls and a bottom surface of a shallow trench used to form the shallow trench isolation structure 301 and an insulating isolation material such as silicon dioxide filling the shallow trench.

Furthermore, it should be appreciated that the integrated circuit memory further includes source/drain regions (not shown) formed in the active region 302 at both sides of the buried word line 315, the source/drain regions being respectively located between two buried word lines 315 passing through the active region 302 and outside the two buried word lines 315, a top surface of the source/drain regions being flush with a top surface of the semiconductor substrate 300, whereby the buried word lines 315 serve as gates of BCAT structures, and the source/drain regions at both sides of the buried word lines 315 serve as source and drain regions of BCAT structures. The first and

second grooves

302a and 302b may be U-shaped grooves, so as to flow along a current conducting direction (i.e., a current flowing direction from a source region to a drain region on both sides of one buried word line 315)To) a conductive channel can be formed in a U-shape, thereby increasing the length of the conductive channel. As a result, even though the absolute distance between the source region and the drain region on both sides of the buried word line 315 is reduced as the memory size is reduced, the short channel effect of the transistor structure can be effectively improved because the formed conductive channel is a U-shaped channel. In addition, the source/drain regions are doped with ions of corresponding conductivity types according to transistor structures of different conductivity types, for example, when the transistor structure is an N-type transistor, the doped ions in the source/drain regions are N-type doped ions, and the N-type doped ions are, for example, phosphorus (P) ions, arsenic (As) ions, and antimony (Sb) ions; when the transistor structure is a P-type transistor, the doped ions in the source/drain region are P-type doped ions, such as boron (B) ions and Boron Fluoride (BF)₂ ⁺) Ions, gallium (Ga) ions, and indium (In) ions. Further, a well region (not shown) is formed in the semiconductor substrate 300, and the source/drain regions are formed in the well region, the well region extends in the horizontal direction to a boundary region between the shallow trench isolation structure 301 and the active region 302, and when the transistor structure is turned on, a conductive channel can be formed in the well region.

Further, the top surface of the work function layer in the embedded word line 315 is lower than the top surface of the semiconductor substrate 300 (i.e., the source/drain region), so that the distance between the work function layer and the source/drain region is increased, which is beneficial to preventing gate-to-drain doped region (GIDL) of the work function layer between the source/drain regions.

It should be understood that the respective depths of the first recess 302a and the second recess 302b and the depth difference therebetween (i.e., the trench depth difference) may determine the electrical characteristics of the BCAT structure, that is, the magnitude of the coupling effect between two adjacent buried word lines 315 may be different according to the trench depth difference between the first recess 302a and the second recess 302b, so that by setting the reasonable depth difference between the first recess 302a and the second recess 302b, a better constraint effect of the coupling effect between two adjacent buried word lines 315 may be achieved, and preferably, the trench depth difference between the first recess 302a and the second recess 302b (i.e., the depth difference) is 5nm to 200 nm.

In an embodiment of the present invention, the source/drain region between two buried word lines 315 intersecting with the same active region 302 is a drain region (or a source region) for electrically connecting to a subsequently formed capacitor (not shown), and the source/drain region in the active region 302 outside the two buried word lines 315 is a source region (or a drain region) electrically connecting to a subsequent bit line (not shown), so that two BCATs sharing a drain region (shared capacitor) are formed, and the two BCATs are controlled by one bit line respectively, so that separate operations (e.g., reading, writing, and erasing) on the shared capacitor can be realized. In another embodiment of the present invention, the source/drain region between two buried word lines 315 intersecting with the same active region 302 is a drain region (or a source region) for electrically connecting to a subsequently formed bit line, and the source/drain region in the active region 302 outside the two buried word lines 315 is a source region (or a drain region) electrically connecting to the subsequently formed bit line, so that two BCAT transistors sharing a bit line are formed, and the two BCAT transistors are simultaneously controlled by the same bit line, and capacitors connected thereto can be respectively controlled, thereby implementing dual bit storage.

As can be seen from the above description, the embedded word lines are embedded in the first and second recesses having different depths of the semiconductor substrate, and the height difference (i.e., the gap) between the bottom surfaces of the two embedded word lines can restrict and reduce the coupling effect (i.e., the WL-WL coupling effect) between the adjacent embedded word lines, thereby improving the device performance and reliability. The integrated circuit memory of the present invention is suitable for use in applications such as Dynamic Random Access Memory (DRAM).

In addition, the invention also provides an electronic device comprising the integrated circuit memory. That is, the electronic device of the present invention uses the integrated circuit memory of the present invention as a memory for storing data and the like. The electronic equipment can be various mobile terminals such as mobile phones, wearable equipment, notebook computers and tablet computers, and the wearable equipment comprises intelligent glasses, head-wearing equipment and wrist-wearing equipment such as watches and bracelets.

The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.

Claims

1. A method of manufacturing an integrated circuit memory, comprising the steps of:

2. The method of claim 1, wherein the lateral dimension of the sidewall is 12nm to 18nm, the dimension of the second spaced opening is 90nm to 100nm, and the dimension of the first spaced opening is 20nm to 30 nm.

3. The method of claim 1, wherein the sacrificial structure is doped using a single tilted ion implantation process, and an angle between an implantation direction of the single tilted ion implantation process and a surface of the semiconductor substrate is 5 ° to 85 ° or 95 ° to 175 °.

4. The method of claim 3, wherein the implanted ions of the tilted ion implantation process comprise at least one of N-type ions, P-type ions, carbon ions, fluorine ions, nitrogen ions, hydrogen ions, oxygen ions, and metal ions.

5. The method of claim 1, wherein the difference in depth between adjacent recesses is between 5nm and 200 nm.

6. The method of claim 1, wherein the step of forming the buried word line comprises:

forming a gate dielectric layer on the surface of the groove;

7. An integrated circuit memory, comprising:

the embedded word lines are embedded in the grooves and asymmetrically arranged in the adjacent grooves, each embedded word line comprises a gate dielectric layer covering the side wall and the bottom surface of each groove, and a conductive layer and a gate isolation layer which are sequentially stacked in the groove with the gate dielectric layer from bottom to top, and the depth difference between the conductive layers of the adjacent embedded word lines is 80-170 nm.

8. The integrated circuit memory of claim 7 wherein the difference in depth between adjacent said recesses is between 5nm and 200 nm.

9. The integrated circuit memory of claim 7 wherein said recesses have a lateral opening dimension of 12nm to 18nm and a spacing between adjacent ones of said recesses of 20nm to 30 nm.