CN111261632A - Semiconductor grid structure and preparation method thereof - Google Patents

Semiconductor grid structure and preparation method thereof Download PDF

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Publication number
CN111261632A
CN111261632A CN201910095566.XA CN201910095566A CN111261632A CN 111261632 A CN111261632 A CN 111261632A CN 201910095566 A CN201910095566 A CN 201910095566A CN 111261632 A CN111261632 A CN 111261632A
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gate
metal
layer
trench
barrier layer
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高玮
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Changxin Memory Technologies Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
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Abstract

The invention provides a semiconductor gate structure and a preparation method thereof, and the filling thickness of a metal gate in a gate groove is reduced to 1/7-2/5 of the depth of the gate groove, so that the gate resistance is reduced, the device current is increased, and the device performance is improved.

Description

Semiconductor grid structure and preparation method thereof
Technical Field
The invention relates to the technical field of integrated circuit manufacturing, in particular to a semiconductor grid structure and a preparation method thereof.
Background
Dynamic Random Access Memory (DRAM) is a well-known semiconductor Memory device, and is widely used in various electronic devices. A Dynamic Random Access Memory (DRAM) is composed of a plurality of repetitive memory cells (cells), each of which is mainly composed of a transistor and a capacitor operated by the transistor, and the memory cells are arranged in an array form, and each of the memory cells is electrically connected to a Bit Line (BL) through a Word Line (WL).
In order to increase the integration of Dynamic Random Access Memory (DRAM), increase the operation speed of devices, and meet the demand of consumers for miniaturized electronic devices, the design of the channel region length of the transistor in the DRAM has been continuously shortened recently, but the transistor will generate serious short channel effect (short channel effect) and on-current (on-current) decrease. One known solution is to change a horizontal Transistor structure in a Dynamic Random Access Memory (DRAM) to a vertical Buried Channel Array Transistor (BCAT) structure, and the structure of the Dynamic Random Access Memory (DRAM) having the Buried Channel Array Transistor (BCAT) is shown in fig. 1 and includes: the semiconductor device comprises a semiconductor substrate 100, a gate dielectric layer 101, a first metal barrier layer 102, a metal gate (i.e. a word line) 103, a gate isolation layer 104, a first conductive contact structure 105 and a second conductive contact structure 106, wherein the semiconductor substrate 100 is provided with a longitudinal U-shaped gate trench (not shown), the metal gate 103 is buried in the gate trench through the gate isolation layer 104 and is insulated and isolated from the semiconductor substrate 100 through the gate dielectric layer 101, source/drain regions (not shown) are respectively formed in the semiconductor substrate 100 at two sides of the metal gate 103, the first conductive contact structure 105 is electrically connected with the source/drain region at one side of the metal gate 103, and the second conductive contact structure 106 is electrically connected with the source/drain region at the other side of the metal gate 103. Since the current needs to flow between the source region (i.e., the source/drain region on one side of the metal gate 103) and the drain region (i.e., the source/drain region on the other side of the metal gate 103) by detour along the U-shaped structure of the gate trench, the effective channel length is increased, which reduces the area occupied by the BCAT transistor in each memory cell and simultaneously suppresses the short channel effect.
In the conventional dram, the filling thickness of the metal gate 103 in the gate trench is large, for example, greater than 5/13 of the depth of the gate trench, or even greater than half the depth of the gate trench, which can increase the length of the channel, but also increase the gate resistance and reduce the device current, which is not favorable for improving the device performance.
Therefore, a new semiconductor gate structure and a method for fabricating the same are needed to solve the above-mentioned problems.
Disclosure of Invention
The invention aims to provide a semiconductor grid structure and a preparation method thereof, which can reduce grid resistance and enlarge a device circuit so as to improve device performance.
To solve the above technical problem, the present invention provides a semiconductor gate structure, including:
a semiconductor substrate having a gate trench; and the number of the first and second groups,
and the metal gate is filled in the gate trench, and the filling thickness of the metal gate is 1/7-2/5 of the depth of the gate trench.
Optionally, the semiconductor gate structure further includes a gate dielectric layer and a gate isolation layer, the gate dielectric layer is formed on the sidewall and the bottom wall of the gate trench, and the gate isolation layer is filled in the gate trench having the gate dielectric layer and buries the metal gate therein.
Optionally, the semiconductor gate structure further includes a first metal blocking layer, the first metal blocking layer is formed between the gate dielectric layer and the metal gate, and the first metal blocking layer surrounds the bottom wall and the side wall of the metal gate and exposes the surface of the gate dielectric layer above the metal gate.
Optionally, the semiconductor gate structure further includes a first metal blocking layer, the first metal blocking layer is formed between the gate dielectric layer and the metal gate, and the first metal blocking layer surrounds the bottom wall and the side wall of the metal gate and covers the surface of the gate dielectric layer above the metal gate.
Optionally, the semiconductor gate structure further comprises a second metal barrier layer formed between the top surface of the metal gate and the gate isolation layer.
Optionally, the first metal barrier layer and the second metal barrier layer are made of titanium aluminum nitride, respectively.
Optionally, the depth of the gate trench is 100nm to 130nm, and the filling thickness of the metal gate is 20nm to 30 nm.
The invention also provides a preparation method of the semiconductor grid structure, which comprises the following steps:
forming a gate trench in a semiconductor substrate; and the number of the first and second groups,
and filling a metal gate in the gate trench, wherein the filling thickness of the metal gate is 1/7-2/5 of the depth of the gate trench.
Optionally, the step of filling the metal gate in the gate trench includes:
forming a gate dielectric layer on the bottom wall and the side wall of the gate groove;
depositing a gate metal material in the gate trench, and etching back the gate metal material to the filling thickness to form the metal gate;
and filling a grid isolation layer in the grid groove, wherein the grid isolation layer buries the metal grid inside.
Optionally, before depositing the gate metal electrode material in the gate trench, forming a first metal blocking layer on the gate dielectric layer, where the gate trench is not filled with the first metal blocking layer; forming a second metal barrier layer on the upper surface of the metal gate before filling the gate isolation layer in the gate trench.
Optionally, the first metal barrier layer and the second metal barrier layer are made of titanium aluminum nitride, respectively.
Optionally, the depth of the gate trench is 100nm to 130nm, and the filling thickness of the metal gate is 20nm to 30 nm.
Compared with the prior art, the semiconductor grid structure and the preparation method thereof have the following beneficial effects:
1. the filling thickness of the metal gate in the gate groove is reduced to 1/7-2/5 of the depth of the gate groove, so that the gate resistance is reduced, the device current is increased, and the device performance is improved.
2. Due to the fact that the filling thickness of the metal grid electrode is reduced, the grid electrode isolation layer above the metal grid electrode is thickened correspondingly, the risk that a subsequent second conductive contact structure and the metal grid electrode are short-circuited can be avoided, the distance between the metal grid electrode and the subsequently formed second conductive contact structure and the storage node contact structure can be enlarged, and then electric leakage between the metal grid electrode and the drain electrode and between the metal grid electrode and the source electrode is reduced.
3. Further, titanium aluminum nitride (TiAlN) is formed between the metal grid and the grid dielectric layer and between the metal grid and the grid isolating layer to serve as a metal blocking layer, and the stability and the reliability of a formed device are enhanced by utilizing the characteristic that TiAlN is more high-temperature resistant and more stable compared with TiN. In addition, after the metal barrier layer adopts TiAlN, the lattice constant can be changed due to the introduction of Al atoms, so that the lattice is changed to the preferred orientation, and the performance of the device is further improved.
Drawings
Fig. 1 is a schematic cross-sectional view of a conventional DRAM with a BCAT (only the structure at one active region is shown).
Fig. 2A and 2B are schematic cross-sectional views of a semiconductor gate structure according to an embodiment of the invention.
Fig. 3 is a flow chart of a method of fabricating a semiconductor gate structure in accordance with an embodiment of the present invention.
Fig. 4A to 4D are schematic cross-sectional views of the device structure in the method for manufacturing the semiconductor gate structure shown in fig. 3.
Wherein the reference numbers are as follows:
100-a semiconductor substrate; 100 a-gate trench; 101-a gate dielectric layer; 102-a first metal barrier layer; 103-metal gate; 104-a gate isolation layer; 105-a first conductive contact structure; 106-a second conductive contact structure; 107-a second metal barrier layer; 108-pad oxide layer; 109-interlayer dielectric layer.
Detailed Description
The technical solution proposed by the present invention will be further described in detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Referring to fig. 2A, an embodiment of the invention provides a semiconductor gate structure, including: a semiconductor substrate 100 having a gate trench (not shown in fig. 2A, which can be referred to as 100a in fig. 4A), a gate dielectric layer 101, a first metal barrier layer 102, a metal gate 103, a gate isolation layer 104, a first conductive contact structure 105, a second conductive contact structure 106, and a second metal barrier layer 107.
The semiconductor substrate 100 may be any substrate known to those skilled in the art for supporting semiconductor integrated circuit components, such as silicon-on-insulator (SOI), bulk silicon (bulk silicon), germanium, silicon germanium, gallium arsenide, or germanium-on-insulator (ge). At least one active region (not shown) for forming a Buried Channel Array Transistor (BCAT), which may be a fin-type three-dimensional structure or a planar structure, and a shallow trench isolation structure (not shown) for isolating the active region from the surrounding environment may be defined in the semiconductor substrate 100. When the semiconductor gate structure to be manufactured is a word line of a memory, the shallow trench isolation structure can isolate all active regions into array arrangement so as to manufacture a storage array of the memory. The shallow trench isolation structure may include a shallow trench (not shown) in the semiconductor substrate 100 and a dielectric material filling the shallow trench, and the dielectric material may include a liner oxide layer (line oxide) formed by a thermal oxidation process and covering the shallow trench and silicon dioxide located on a surface of the liner oxide layer and filling the shallow trench.
The gate trenches are formed in the corresponding active regions and may be in the shape of a right-angled U-shape or a rounded U-shape. An active region (not shown) and a drain region (not shown) may be formed in the semiconductor substrate 100 on both sides of the gate trench, respectively. Further, two gate trenches are arranged in parallel in at least one active region of the semiconductor substrate 100, a drain region is formed in the active region between the two gate trenches, and an active region is formed in the active region on the opposite side of the two gate trenches, so that two BCATs can be manufactured in one active region, which is beneficial to improving the integration level of devices.
A first conductive contact structure 105 and a second conductive contact structure 106 are respectively formed on the semiconductor substrate 100 (i.e., active region) at both sides of the gate trench. When the semiconductor gate structure is a word line of a memory, the semiconductor substrate 100 has a plurality of active regions arranged in an array according to a unit row and a unit column, the first conductive contact structure 105 on each active region is a storage node contact, the bottom of the first conductive contact structure is electrically connected to, for example, a source region in the semiconductor substrate 100, the top of the first conductive contact structure is electrically connected to a capacitor (not shown) controlled by a BCAT and used for storing data, the second conductive contact structure 106 is a bit line contact, the bottom of the second conductive contact structure is electrically connected to a drain region, and the top of the second conductive contact structure is electrically connected to a bit line (not shown) of the memory. The metal gates 103 in each cell row are connected as a whole to serve as a word line of the memory, and each bit line is electrically connected to the drain region of the corresponding BCAT through the second conductive contact structure 106 in the cell column. Preferably, the first conductive contact structure 105 and the second conductive contact structure 106 are each a composite structure including a metal silicide layer (not shown), a metal barrier layer (not shown), and a metal layer (not shown) sequentially stacked on the semiconductor substrate 100. The metal silicide layer can reduce contact resistance, and the metal silicide layer can be a metal silicide containing at least one of metal elements such as Ti, W, Co, Ni, Zr, Mo and Ta. The metal barrier layer can prevent metal in the metal layer from diffusing into the semiconductor substrate 100 to affect the performance of the device, and the material of the metal barrier layer can be TiAlN, TaCN, TaSiN, TiN or TaN and other metal nitrides; the material of the metal layer may be at least one of metals including W, Cu, Ni, Co, Ti, and Ta.
The gate dielectric layer 101 covers the side wall and the bottom wall of the gate trench, the first metal barrier layer 102 covers the surface of the gate dielectric layer 101, and the metal gate 103 is filled in the gate trenchOn the bottom of the gate trench, the second metal barrier layer 107 covers the top surface of the metal gate 103. The filling thickness H2 of the metal gate 103 is preferably 1/7-2/5 of the depth H of the gate trench, for example, when the depth H of the gate trench is 100-130 nm, the filling thickness H2 of the metal gate 103 is 20-30 nm, so that on one hand, the gate resistance can be reduced, and the device current can be increased; on the other hand, the distance between the top of the metal gate 103 and the first conductive contact structure 105 and the second conductive contact structure 106 can be increased, so that the short circuit problem between the metal gate 103 and the first conductive contact structure 105 and the second conductive contact structure 106 is avoided, and the electric leakage between the metal gate 103 and the drain region and between the metal gate 103 and the source region is reduced. The metal gate 103 may include one or more work function metal layers and a metal electrode layer surrounded by the work function metal layers, wherein a material of the work function metal layer is determined by a conductive type of a BCAT transistor to be formed, and when the BCAT transistor to be formed is a P-type transistor, the work function metal layer in the metal gate 103 is a P-type work function metal material, and the P-type work function metal material may include TiN, TaN, Ru, Mo, Al, WN, ZrSi2、MoSi2、TaSi2、NiSi2W or other suitable p-type work function material, or a combination thereof, and when the BCAT transistor to be formed is an N-type transistor, the work function metal layer in the metal gate 103 is an N-type work function metal material, and the N-type work function metal material includes Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable N-type work function material, or a combination thereof; the material of the metal electrode layer may include Al, W, Cu, and/or other suitable metal materials. Correspondingly, the gate dielectric layer 102 is made of a high-K dielectric (the dielectric constant K is greater than 7), such as Ta2O5、TiO2、TiN、Al2O3、Pr2O3、La2O3、LaAlO3、HfO2、ZrO2Or metal oxides of other compositions, etc. to be compatible with the metal gate 103, which is beneficial to improving the mobility of carriers and improving the device performance. The first metal barrierThe layer 102 is used for blocking metal ions in the metal gate 103 from diffusing into the gate dielectric layer 102 and the semiconductor substrate 100, and simultaneously improving the adhesion between the gate dielectric layer 101 and the metal gate 103. The second metal barrier layer 107 is used for blocking metal ions in the metal gate 103 from diffusing into the gate isolation layer 104 and the semiconductor substrate 100 above the metal gate 103, and simultaneously is used for providing adhesion between the gate isolation layer 104 and the metal gate 103. The first metal barrier layer 102 and the second metal barrier layer 107 are preferably made of titanium aluminum nitride (TiAlN), which is more resistant to high temperature and more stable in chemical properties than titanium nitride (TiN), and the introduction of Al atoms can cause a change in lattice constant, which causes a change in lattice orientation, thereby further improving device performance. In this embodiment, the first metal barrier layer 102 not only surrounds the bottom surface and the sidewall of the metal gate 103, but also extends upward to the sidewall of the gate dielectric layer 101 above the metal gate 103, the second metal barrier layer 107 not only covers the top surface of the metal gate 103, but also extends upward to the sidewall of the first metal barrier layer 102 above the metal gate 103, that is, the second metal barrier layer 107 surrounds the bottom surface and the sidewall of the gate isolation layer 104, and the first metal barrier layer 102 also covers the sidewall of the second metal barrier layer 107. Referring to fig. 2B, in other embodiments of the present invention, the first metal barrier layer 102 may only cover the sidewalls and the bottom surface of the metal gate 103, and the second metal barrier layer 107 may only cover the top surface of the metal gate 103 and the top surface of the first metal barrier layer 102.
The gate isolation layer 104 is filled in the gate trench 101 and fills the gate trench, burying the metal gate 103 therein. The material of the gate isolation layer 104 includes, but is not limited to, silicon oxide, silicon nitride, and silicon oxynitride.
It should be appreciated that the first metal barrier layer 102 and the second metal barrier layer 107 of the present invention are not limited to the TiAlN single layer film, but may be a stacked structure including a metal layer of Ti or Ta, a metal nitride layer of TiAlN, TaCN, TaSiN, TiN, or TaN, or at least one of a metal and a metal nitride.
The semiconductor grid structure is suitable for manufacturing various electronic devices, the electronic devices can be various mobile terminals such as mobile phones, wearable devices, notebook computers and tablet computers, and the wearable devices comprise intelligent glasses, head-wearing devices and wrist-wearing devices such as watches and bracelets.
Referring to fig. 3, the semiconductor gate structure of the present invention can be fabricated by the following method for fabricating a semiconductor gate structure, which includes the following steps:
s1, forming a gate trench in the semiconductor substrate;
s2, sequentially forming a gate dielectric layer and a first metal barrier layer on the side wall and the bottom wall of the gate trench;
s3, filling a metal gate in the gate trench, wherein the filling thickness of the metal gate is 1/7-2/5 of the depth of the gate trench; and the number of the first and second groups,
s4, forming a second metal barrier layer on the top surface of the metal gate and filling the gate isolation layer in the gate trench;
and S5, respectively forming a first conductive contact structure and a second conductive contact structure on the semiconductor substrate at two sides of the gate trench.
Referring to fig. 4A, first, step S1 is executed to form a gate trench 101 in a semiconductor substrate 100, which includes the following steps:
first, a semiconductor substrate 100 is provided, wherein the semiconductor substrate 100 may be any substrate known to those skilled in the art for supporting semiconductor integrated circuit components, such as silicon-on-insulator (SOI), bulk silicon (bulk silicon), germanium, silicon germanium, gallium arsenide, or germanium-on-insulator (ge). At least one active region (not shown) for forming a Buried Channel Array Transistor (BCAT), which may be a fin-type three-dimensional structure or a shallow trench isolation structure (not shown) for isolating the active region from the surrounding environment, and a shallow trench isolation structure (not shown) for isolating the active region from the surrounding environment may be defined in the semiconductor substrate 100May be a planar structure. When the semiconductor gate structure to be manufactured is a word line of a memory, the shallow trench isolation structure can isolate all active regions into array arrangement so as to manufacture a storage array of the memory. The shallow trench isolation structure may include a shallow trench (not shown) in the semiconductor substrate 100 and a dielectric material (not shown) filling the shallow trench, and the dielectric material may include a liner oxide (not shown) formed by a thermal oxidation process and covering the shallow trench and a silicon dioxide (not shown) located on a surface of the liner oxide and filling the shallow trench, so as to improve an isolation performance of the shallow trench isolation structure, and the forming process includes: (1) forming a pad oxide layer 108 on a surface of the semiconductor substrate 100 through a thermal oxidation process; (2) forming a silicon nitride hard mask layer (not shown) by a chemical vapor deposition process, and further forming a patterned photoresist layer (not shown) on the silicon nitride hard mask layer by photoresist coating, exposing, developing and other photolithography processes, wherein the patterned photoresist layer covers the active region and the layers above the active region and exposes the silicon nitride hard mask layer above the semiconductor substrate 100 serving as an isolation region between the active regions; (3) performing an etching process on the exposed silicon nitride hard mask layer, the pad oxide layer below the exposed silicon nitride hard mask layer and the semiconductor substrate 100 with partial depth by taking the patterned photoresist layer as a mask so as to form shallow trenches in the semiconductor substrate 100 between the active regions; (4) removing the patterned photoresist layer; (5) forming a line oxide (not shown) on the sidewalls and bottom surface of the shallow trench by a vapor deposition process or a thermal oxidation process; (6) depositing silicon dioxide on the surface of the shallow trench and the surface of the silicon nitride hard mask layer by adopting the processes of chemical vapor deposition and the like until the shallow trench is filled with the silicon dioxide; (7) carrying out top surface planarization on the silicon dioxide by adopting a chemical mechanical planarization process until the top surface of the silicon dioxide is flush with the top surface of the silicon nitride hard mask layer so as to form a shallow trench isolation structure; (8) the silicon nitride hard mask layer can be removed by wet etching and other processes. Further, after depositing silicon dioxide, or top surface planarization of the silicon dioxideAnd then, or after removing the silicon nitride hard mask layer, performing densification (densification) on the silicon dioxide filled in the shallow trench by adopting high-temperature thermal annealing, Ultraviolet (UV) or laser (laser) high-energy light excitation process and the like so as to increase the compactness of the dielectric material, ensure the isolation effect of the shallow trench isolation structure and strengthen the mechanical strength of the shallow trench isolation structure. The process temperature of the high-temperature thermal annealing process is, for example, 800 ℃ to 1200 ℃, and ozone (O) can be further introduced when the high-temperature thermal annealing process is performed3) And/or a strongly reactive gas such as carbon monoxide (CO). In addition, after the shallow trench isolation structure is formed, a well region (not shown) may be formed in each active region by an ion implantation process and further combining with annealing activation and other processes, wherein a doping type of the well region is determined by a conductivity type of a BCAT transistor to be formed, for example, in the present embodiment, if the formed BCAT transistor is an N-type transistor, the well region is a P-type doping region. The doping depth of the well region can be adjusted according to actual conditions. It should be noted that the pad oxide layer described above can protect the semiconductor substrate 100 and the active region during the process of forming the shallow trench isolation structure, and the pad oxide layer 108 can remain to serve as a protection layer for the top surfaces of the semiconductor substrate 100 and the active region in the subsequent process.
Referring to fig. 4A, a patterned hard mask layer (not shown) is sequentially formed on the surface of the shallow trench isolation structure and the pad oxide layer 108, and the specific forming process includes: (1) a hard mask layer can be formed on the surface with the shallow trench isolation structure and the pad oxide layer through processes of Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD) and the like, the material of the hard mask layer comprises at least one of silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, metal nitride, metal oxide and metal carbide, preferably silicon nitride (SiN), the silicon nitride material is easy to obtain, low in cost and mature in manufacturing method, and has a higher etching selection ratio with the pad oxide layer; (2) openings (not shown) for defining gates (i.e., word lines) can be formed by a series of photolithography processes such as photoresist coating, exposure using a gate mask (not shown), and development using a word line mask (not shown) when the semiconductor gate structure to be fabricated is a word line of a memory; (3) etching the hard mask layer to the surface of the pad oxide layer 108 by using the photoresist layer (not shown) having the opening as a mask, so as to transfer the gate (i.e., word line) pattern in the photoresist to the hard mask layer; (4) the photoresist is removed, and the hard mask layer is used as a mask to continue to etch downward, that is, the pad oxide layer 108 and the semiconductor substrate 100 (including the active region and the shallow trench isolation structure) with a partial depth are sequentially etched, so as to form a gate trench 100a in the semiconductor substrate 100. The gate trench 100a may have a rounded U shape, a right-angled U shape, or a trapezoid shape with a wide top and a narrow bottom. Since the electrical characteristics of the Buried Channel Array Transistor (BCAT) may vary according to the depth from the upper surface (i.e., the top surface) of the semiconductor substrate to the bottom surface of the buried gate thereof, adjusting the depth of the gate trench 100a may achieve desired electrical characteristics of the Buried Channel Array Transistor (BCAT), thereby improving the electrical performance and reliability of the finally formed semiconductor gate structure. In this embodiment, the depth H of the gate trench 100a is 100nm to 130 nm.
With reference to fig. 4A, the hard mask layer on the surface of the pad oxide layer 108 may be removed by an etching process or a chemical mechanical planarization process, and the like, and further cleaned to expose the sidewalls and the bottom surface of the gate trench 100a, so as to prepare for forming the metal gate 103. In this embodiment, two gate trenches 100a may be arranged side by side in one active region of the semiconductor substrate 100, the active region between the two gate trenches 100a is subsequently used to form a drain region, and the active regions on the opposite sides of the two gate trenches 100a are subsequently used to form source regions, respectively, so that two BCATs may be fabricated in one active region, which is beneficial to improving the device integration level.
Referring to fig. 4B, in step S2, a thermal oxidation (dry or wet oxygen) process, a chemical vapor deposition (cvd), an atomic layer deposition (ald), etc. may be first employed to cover the pad oxide layer 108 and the sidewalls and bottom surface of the gate trench 100a with a gate dielectric layer 101, wherein the gate dielectric layer 101 is preferably made of a high-k materialA K dielectric (dielectric constant K greater than 7) and a high K dielectric material such as Ta2O5、TiO2、TiN、Al2O3、Pr2O3、La2O3、LaAlO3、HfO2、ZrO2Or metal oxide of other composition, etc. to be compatible with the metal gate 103 to be formed, which is beneficial to improving the mobility of carriers and improving the device performance. And preferably, the gate dielectric layer 101 made of the high-K dielectric material is prepared by adopting an atomic layer deposition process (ALD) to maintain the film-forming quality and the thickness uniformity of the gate dielectric layer 101.
With reference to fig. 4B, in step S2, a first metal blocking layer 102 is deposited on the surface of the gate dielectric layer 101 by a physical vapor deposition process, a chemical vapor deposition process, an atomic layer deposition process, or the like, and the first metal blocking layer 102 is preferably prepared by the atomic layer deposition process to protect the gate dielectric layer 101 and prevent the quality of the gate dielectric layer 101 from deteriorating. The first metal barrier layer 102, also referred to as a metal barrier layer or a metal adhesion barrier layer, is intended to protect the gate dielectric layer 101 from introducing metal impurities in subsequent steps, and to improve adhesion between the gate dielectric layer 101 and the subsequently formed metal gate 103. For example, in the present embodiment, the metal gate 103 includes one or more work function metal layers. Without the metal barrier layer 102, metal material from those work function metal layers would diffuse into the gate dielectric layer 101, causing manufacturing defects. In various embodiments, the first metal barrier layer 102 includes any one or more of a metal layer such as Ti or Ta, a metal nitride layer such as TiAlN, TaCN, TaSiN, TiN, or TaN, or a combination of metal and metal nitride. It should be appreciated that in some cases, the single-layer first metal barrier layer 102 may not provide enough protection for the gate dielectric layer 101, and it is necessary to form the first metal barrier layer 102 having a multi-layer stacked composite structure in the gate trench 100a to enhance the protection for the gate dielectric layer 101, so as to prevent the material in the metal gate 103 from diffusing into the gate dielectric layer 101 and causing device defects when the surface metal barrier layer is etched and damaged. Preferably, the material of the first metal barrier layer 102 includes titanium aluminum nitride (TiAlN), which is more resistant to high temperature and more stable in chemical properties than titanium nitride (TiN), and the introduction of Al atoms can cause a change in lattice constant, causing a change in lattice orientation, thereby further improving device performance.
With reference to fig. 4B, in step S3, a gate metal material is deposited on the surface of the first metal barrier layer 102 by evaporation, electroplating, chemical vapor deposition, atomic layer deposition, or the like, wherein the deposition thickness of the gate metal material on the bottom of the gate trench 100a is at least as thick as the metal gate 103 to be formed. Then, the gate metal material on the region outside the gate trench 100a may be removed by an etch-back process, and the gate metal material is only filled in the gate trench 100a and used as the metal gate 103, and the etch-back process may enable a higher etching ratio between the gate metal material and the first metal blocking layer 102, after the etch-back is finished, the filling thickness (or height) of the formed metal gate 103 is smaller than the depth of the gate trench 100a, and the first metal blocking layer 102 above the metal gate 103 is also retained. In other embodiments of the present invention, the etch-back process may enable a near-etching ratio between the metal gate material and the first metal blocking layer 102, after the etch-back process is completed, a filling thickness (or height) of the formed metal gate 103 is smaller than a depth of the gate trench 100a, and the first metal blocking layer 102 above the metal gate 103 is also etched away, for example, the top of the first metal blocking layer 102 on the sidewall of the gate dielectric layer 101 is lower than the height of the metal gate 103. The metal gate 103 is typically a stacked structure including a work function metal layer (not shown) covering the first metal barrier layer 102 and a metal electrode layer (not shown) surrounded by the work function metal layer. The material of the work function metal layer is determined by the conductivity type of the BCAT transistor to be formed, and when the BCAT transistor to be formed is a P-type transistor, the work function metal layer in the metal gate 103 is a P-type work function metal material, which may include TiN, TaN, Ru, Mo, Al, WN, ZrSi2、MoSi2、TaSi2、NiSi2W or other suitable p-type work function material, or a combination thereof, and when the BCAT transistor to be formed is an N-type transistor, the work function metal layer in the metal gate 103 is an N-type work function metal material, which includes Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable N-type work function material, or a combination thereof. The work function metal layer may be a single layer or may be a plurality of layers. In this embodiment, the top surface of the metal gate 103 is lower than the top surfaces of a source region (not shown) and a drain region (not shown) formed subsequently, so that the distance between the work function metal layer and the source region and the drain region is increased, which is beneficial to preventing gate-induced drain leakage (GIDL) from occurring between the work function metal layer and the source region and the drain region. The material of the metal electrode layer in the metal gate 103 may include Al, W, Cu, and/or other suitable metal materials.
Referring to fig. 4B and 4C, in step S4, first, a second metal barrier layer 107 is deposited on the top surface of the metal gate 103 and the surface of the first metal barrier layer 102 by a physical vapor deposition, a chemical vapor deposition, an atomic layer deposition, or the like, and the atomic layer deposition process is preferably used to prepare the second metal barrier layer 107 so as to prevent the metal in the metal gate 103 from diffusing upwards and improve the adhesion between the metal gate 103 and the subsequently formed gate isolation layer 104. The second metal barrier layer 107 may include a metal layer such as Ti or Ta, a metal nitride layer such as TiAlN, TaCN, TaSiN, TiN, or TaN, or any one or more combinations of metals and metal nitrides. Preferably, the material of the second metal barrier layer 107 includes titanium aluminum nitride (TiAlN), which is more resistant to high temperature and more stable in chemical properties than titanium nitride (TiN), and the introduction of Al atoms can cause a change in lattice constant, causing a change in lattice orientation, thereby further improving device performance. In other embodiments of the present invention, the second metal barrier layer 107 may be etched back to a certain height by an etch-back process to expose a portion of the sidewall of the gate dielectric layer 101 above the gate.
With continued reference to fig. 4B and 4C, in step S4, a gate isolation layer 104 is deposited on the second metal barrier layer 107 by using a physical vapor deposition, a chemical vapor deposition, an atomic layer deposition, or the like, wherein the gate isolation layer 104 is made of a material including, but not limited to, silicon oxide, silicon nitride, and silicon oxynitride, and the deposited gate isolation layer 104 at least fills the gate trench 100 a. The top of the gate isolation layer 104 is further planarized by a chemical mechanical planarization process to the top surface of the semiconductor substrate 100 or the top surface of the pad oxide layer 108 around the gate trench 100a, so as to remove the gate isolation layer 104, the second metal barrier layer 107, the first metal barrier layer 102 and the gate dielectric layer 101 on the semiconductor substrate 100 at the periphery of the gate trench 100a, thereby forming the metal gate 103 embedded in the gate trench 100 a.
Then, LDD (lightly doped drain) ion implantation, Halo (Halo) ion implantation, source-drain heavily doped ion implantation, and the like may be performed on the active regions on both sides of the gate trench 100a by using the gate isolation layer 104 as a mask, so as to form a source region (not shown) and a drain region (not shown) in the active regions on both sides of the gate trench 100a, respectively, whereby the metal gate 103 and the source region and the drain region on both sides of the metal gate 103 constitute a main portion of the BCAT structure. When two gate trenches 100a are formed in one active region, two BCATs may be fabricated in the active region, and a source region or a drain region shared by the two BCATs is formed in the active region between the two gate trenches 100a, the shared source region or drain region is electrically connected to a second conductive contact structure formed later, and a source region or drain region on the other side of the gate trench 100a is electrically connected to a first conductive contact structure formed later. In other embodiments of the present invention, the stacked structure of the gate dielectric layer 101 to the gate isolation layer 104 on the surface of the active region on both sides of the metal gate 103 may also be etched by an etching process to form an opening exposing the surface of the active region for forming the source region and the drain region, and then, with the stacked structure of the remaining gate dielectric layer 101 to the gate isolation layer 104 as a mask, LDD (lightly doped drain) ion implantation, Halo (Halo) ion implantation, source-drain heavily doped ion implantation, and the like are performed on the exposed active region to form a required source region (not shown) and drain region in the active region on both sides of the metal gate 103(not shown). When the gate trench 100a is a U-shaped groove, a U-shaped conductive channel may be formed in a conducting direction along a current (i.e., a current flowing direction of the source region to the drain region that are interposed between both sides of the metal gate 103), thereby increasing the length of the conductive channel. Therefore, as the size of the transistor is reduced, even if the absolute distance between the source region and the drain region on both sides of the metal gate 103 is reduced, the short channel effect of the transistor structure can be effectively improved because the formed conductive channel is a U-shaped channel. Furthermore, according to the transistor structures with different conductivity types, ions with corresponding conductivity types are doped in the source region and the drain region, for example, when the BCAT transistor structure is an N-type transistor, the doped ions in the source region and the drain region are N-type doped ions, for example, phosphorus (P) ions, arsenic (As) ions, and antimony (Sb) ions; when the BCAT transistor structure is a P-type transistor, the doped ions in the source region and the drain region are P-type doped ions, such as boron (B) ions and Boron Fluoride (BF)2 +) Ions, gallium (Ga) ions, and indium (In) ions.
Referring to fig. 4D, in step S5, an interlayer dielectric layer 109, which may be silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric material and/or other suitable insulating materials, is first formed on the semiconductor substrate 100 and the gate isolation layer 104; then, opening the interlayer dielectric layers 109 on both sides of the gate trench 100a by photolithography and etching processes to form contact holes (not shown) exposing the surface of the semiconductor substrate 100 on both sides of the gate trench 100 a; then, depositing a conductive material in the contact hole by using a physical vapor deposition (including electroplating, evaporation and the like), a chemical vapor deposition, an atomic layer deposition and the like until the deposited conductive material fills the contact hole, wherein the conductive material can comprise at least one of doped polysilicon, undoped polysilicon and metal (including Al, W, Cu and the like); the conductive material is further planarized using a Chemical Mechanical Planarization (CMP) process to the surface of the interlevel dielectric layer 109 to form a first conductive contact structure 105 and a second conductive contact structure 106. In other embodiments of the present invention, the first conductive contact structure 105 and the second conductive contact structure 106 may be a composite structure including a metal silicide layer (not shown), a metal barrier layer (not shown), and a metal layer (not shown) sequentially stacked on the semiconductor substrate 100, thereby reducing contact resistance. Wherein, the material of the metal layer can be W, Ti, Al, Cu or Ta; the metal barrier layer can prevent metal in the metal layer from diffusing into the semiconductor substrate 100 to affect the performance of the device, and the material of the metal barrier layer can be TiAlN, TaCN, TaSiN, TiN, TaN or other metal nitrides; the metal silicide layer may reduce contact resistance between the metal layer and the semiconductor substrate 100, and may be a metal silicide containing at least one of metal elements of Ti, W, Co, Ni, Zr, Mo, Ta, and the like.
According to the preparation method of the semiconductor gate structure, the filling thickness of the metal gate in the gate groove is set to be 1/7-2/5 of the depth of the gate groove, so that the gate resistance is reduced, the device current is increased, the device performance is improved, and the preparation method is particularly suitable for manufacturing a memory. When the preparation method of the semiconductor grid structure is applied to manufacturing the memory, the metal grids in the plurality of active regions are aligned and connected together to form a word line of the memory, and the plurality of second conductive contact structures are aligned and connected to the same bit line.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.

Claims (12)

1. A semiconductor gate structure, comprising:
a semiconductor substrate having a gate trench; and the number of the first and second groups,
and the metal gate is filled in the gate trench, and the filling thickness of the metal gate is 1/7-2/5 of the depth of the gate trench.
2. The semiconductor gate structure of claim 1, further comprising a gate dielectric layer formed on sidewalls and a bottom wall of the gate trench and a gate isolation layer filled in the gate trench with the gate dielectric layer and burying the metal gate therein.
3. The semiconductor gate structure of claim 2, further comprising a first metal barrier layer formed between the gate dielectric layer and the metal gate, the first metal barrier layer surrounding the bottom wall and sidewalls of the metal gate and exposing a surface of the gate dielectric layer above the metal gate.
4. The semiconductor gate structure of claim 2, further comprising a first metal barrier layer formed between the gate dielectric layer and the metal gate, the first metal barrier layer surrounding a bottom wall and sidewalls of the metal gate and covering a surface of the gate dielectric layer above the metal gate.
5. The semiconductor gate structure of claim 3 or 4, further comprising a second metal barrier layer formed between a top surface of the metal gate and the gate isolation layer.
6. The semiconductor gate structure of claim 5, wherein the first metal barrier layer and the second metal barrier layer each comprise titanium aluminum nitride.
7. The semiconductor gate structure of any of claims 1 to 4 or 6, wherein the depth of the gate trench is 100nm to 130nm, and the filling thickness of the metal gate is 20nm to 30 nm.
8. A method for manufacturing a semiconductor gate structure, comprising:
forming a gate trench in a semiconductor substrate;
and filling a metal gate in the gate trench, wherein the filling thickness of the metal gate is 1/7-2/5 of the depth of the gate trench.
9. The method of claim 8, wherein the step of filling the metal gate in the gate trench comprises:
forming a gate dielectric layer on the bottom wall and the side wall of the gate groove;
depositing a gate metal material in the gate trench, and etching back the gate metal material to the filling thickness to form the metal gate;
and filling a grid isolation layer in the grid groove, wherein the grid isolation layer buries the metal grid inside.
10. The method of claim 9, wherein a first metal barrier layer is formed on the gate dielectric layer before depositing the gate metal material in the gate trench, the first metal barrier layer not filling the gate trench; forming a second metal barrier layer on the upper surface of the metal gate before filling the gate isolation layer in the gate trench.
11. The method of claim 10, wherein the first metal barrier layer and the second metal barrier layer each comprise titanium aluminum nitride.
12. The method of manufacturing a semiconductor gate structure according to any one of claims 8 to 11, wherein a depth of the gate trench is 100nm to 130nm, and a filling thickness of the metal gate is 20nm to 30 nm.
CN201910095566.XA 2018-11-30 2019-01-31 Semiconductor grid structure and preparation method thereof Pending CN111261632A (en)

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Cited By (3)

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Publication number Priority date Publication date Assignee Title
CN113782534A (en) * 2021-09-15 2021-12-10 长鑫存储技术有限公司 Semiconductor structure, manufacturing method thereof and memory
CN114861925A (en) * 2022-04-28 2022-08-05 清华大学 Capacitor, filter circuit chip, surface chip ion trap and quantum computer
CN117529102A (en) * 2024-01-03 2024-02-06 长鑫新桥存储技术有限公司 Semiconductor structure and preparation method thereof

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113782534A (en) * 2021-09-15 2021-12-10 长鑫存储技术有限公司 Semiconductor structure, manufacturing method thereof and memory
WO2023040140A1 (en) * 2021-09-15 2023-03-23 长鑫存储技术有限公司 Semiconductor structure and manufacturing method therefor, and memory
CN114861925A (en) * 2022-04-28 2022-08-05 清华大学 Capacitor, filter circuit chip, surface chip ion trap and quantum computer
CN114861925B (en) * 2022-04-28 2024-03-19 清华大学 Capacitor, filter circuit chip, surface chip ion trap and quantum computer
CN117529102A (en) * 2024-01-03 2024-02-06 长鑫新桥存储技术有限公司 Semiconductor structure and preparation method thereof
CN117529102B (en) * 2024-01-03 2024-05-14 长鑫新桥存储技术有限公司 Semiconductor structure and preparation method thereof

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