WO2023040140A1 - Semiconductor structure and manufacturing method therefor, and memory - Google Patents

Abstract

Provided in the embodiments of the present application are a semiconductor structure and a manufacturing method therefor, and a memory. The semiconductor structure comprises a substrate, a gate dielectric layer, a metal gate electrode, a metal barrier layer, a protective layer and a gate isolation layer, wherein the substrate is internally provided with a gate trench; the gate dielectric layer is located on a side wall and a bottom wall of the gate trench; the gate trench having the gate dielectric layer is filled with the metal gate electrode, and a filling thickness of the metal gate electrode is smaller than the depth of the gate trench; the metal barrier layer is located between the gate dielectric layer and the metal gate electrode; the protective layer covers a side wall and a bottom wall of a first trench, and the first trench is a spare portion of the gate trench after the gate dielectric layer, the metal gate electrode and the metal barrier layer are formed; and the first trench having the protective layer is filled with the gate isolation layer. By means of the present application, a gate dielectric layer can be effectively isolated from the outside by means of the protective layer, so that the improvement of the electrical stability of a WL is facilitated, and the performance of a memory is thus improved.

Description

Semiconductor structure and manufacturing method thereof, memory

This application claims the priority of the Chinese patent application with the application number 202111078957.4 and the application title "semiconductor structure and its manufacturing method, memory" submitted to the China Patent Office on September 15, 2021, the entire content of which is incorporated by reference in this application middle.

technical field

The embodiments of the present application relate to the field of semiconductor technologies, and in particular, to a semiconductor structure, a manufacturing method thereof, and a memory.

Background technique

Dynamic Random Access Memory (Dynamic Random Access Memory, referred to as DRAM), as a well-known semiconductor storage element, has been widely used in various electronic devices at present. Among them, DRAM is composed of many repeated memory cells (cells), each memory cell is mainly composed of a transistor and a capacitor controlled by the transistor, and the memory cells are arranged in an array form, and each memory cell passes through a word line ( A word line (WL for short) and a bit line (BL for short) are electrically connected to each other.

In traditional DRAM, when the gate isolation layer is deposited on the top layer of WL, the by-products generated by the gate isolation layer will directly contact the gate dielectric layer of WL. Under the action of high temperature, the by-products will directly enter the gate dielectric layer, resulting in the Electrical instability, thus affecting the performance of the memory.

Contents of the invention

Embodiments of the present application provide a semiconductor structure, a manufacturing method thereof, and a memory, which can effectively improve the electrical stability of the WL and improve the performance of the memory.

In a first aspect, the present application provides a semiconductor structure, the semiconductor structure comprising:

a substrate, a gate trench is arranged in the substrate;

a gate dielectric layer, the gate dielectric layer is located on the sidewall and bottom wall of the gate trench;

a metal gate, the metal gate is filled in the gate trench having the gate dielectric layer, and the filling thickness of the metal gate is smaller than the depth of the gate trench;

a metal barrier layer, the metal barrier layer is located between the gate dielectric layer and the metal gate;

a protection layer, the protection layer covers the sidewall and the bottom wall of the first trench, and the first trench is used for forming the gate dielectric layer, the metal gate and the metal gate trench. The empty part after the barrier layer;

A gate isolation layer, the gate isolation layer is filled in the first trench with the protection layer.

In a second aspect, the present application provides a method for manufacturing a semiconductor structure, including:

A substrate is provided, and a gate trench is provided in the substrate, and the gate trench includes a gate dielectric layer, a metal gate, and a metal barrier layer; wherein, the gate dielectric layer is located in the gate trench The metal gate is filled in the gate trench with the gate dielectric layer, and the filling thickness of the metal gate is smaller than the depth of the gate trench, so The metal barrier layer is located between the gate dielectric layer and the metal gate;

Forming a protection layer, the protection layer covers the sidewall and the bottom wall of the first trench, and the first trench is the gate dielectric layer, the metal gate and the gate trench formed in the first trench. The vacant part after the metal barrier layer;

A gate isolation layer is deposited, and the gate isolation layer is filled in the first trench with the protection layer.

In a third aspect, the present application provides a memory, including the semiconductor structure provided in the first aspect.

The semiconductor structure and its manufacturing method provided by the embodiments of the present application can effectively isolate the gate dielectric layer of WL from the outside world by setting the above protective layer. Therefore, when depositing the gate isolation layer on the top layer of WL, it is possible to avoid gate The by-products generated by the pole isolation layer are in direct contact with the gate dielectric layer of the WL, thereby helping to improve the electrical stability of the WL, thereby improving the performance of the memory.

Description of drawings

FIG. 1 is a first schematic cross-sectional structure diagram of a semiconductor structure provided in an embodiment of the present application;

FIG. 2 is a second schematic cross-sectional structure diagram of a semiconductor structure provided in an embodiment of the present application;

FIG. 3 is a third schematic cross-sectional structure diagram of a semiconductor structure provided in an embodiment of the present application;

FIG. 4 is a schematic diagram 4 of a cross-sectional structure of a semiconductor structure provided in an embodiment of the present application;

FIG. 5 is a schematic diagram of a cross-sectional structure of a semiconductor structure provided in the embodiment of the present application (5);

FIG. 6 is a sixth schematic cross-sectional structure diagram of a semiconductor structure provided in the embodiment of the present application;

FIG. 7 is a seventh schematic cross-sectional structure diagram of a semiconductor structure provided in an embodiment of the present application.

Component label description:

10 Substrate

20 gate dielectric layer

30 metal barrier

40 metal grid

50 layers of insulation

60 metal layers

61 SiN

70 gate isolation layer

80 first groove

90 layers of protection

Detailed ways

In order to make the purposes, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments It is a part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the scope of protection of this application. In addition, although the disclosures in this application are introduced as exemplary one or several examples, it should be understood that each aspect of these disclosures can also independently constitute a complete implementation.

It should be noted that the brief description of the terms in this application is only for the convenience of understanding the implementations described below, and is not intended to limit the implementations of this application. These terms are to be understood according to their ordinary and usual meaning unless otherwise stated.

The terms "first" and "second" in the description and claims of this application and the above drawings are used to distinguish similar or similar objects or entities, and do not necessarily mean limiting a specific order or sequence. unless otherwise noted. It should be understood that the terms used in this way can be interchanged under appropriate circumstances, for example, they can be implemented in a sequence other than those shown in the illustrations or descriptions of the embodiments of the present application.

Furthermore, the terms "comprising" and "having" and any variations thereof, are intended to cover but not exclusively include, for example, a product or device comprising a series of components need not be limited to those components explicitly listed, but may include other components not expressly listed or inherent in these products or equipment.

It should be noted that the drawings are all in very simplified form and use imprecise scales, and are only used to facilitate and clearly assist the purpose of illustrating the embodiments of the present application. It should be understood that in the following description, references to 'on' and 'under' each layer may be made based on the drawings. It will be understood, however, that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over or otherwise positioned differently (eg, rotated), the exemplary term "on" could also include "below" and other orientational relationships. When a layer, region, pattern or structure is referred to as being "on" a substrate, layer, region and/or pattern, it can be directly on another layer or substrate, and/or intervening layers may also be present. Similarly, when a layer is referred to as being 'under' another layer, it can be directly under another layer, and/or one or more intervening layers may also be present.

As a common semiconductor memory device, DRAM usually consists of many repeated memory cells. Wherein, each memory cell is mainly composed of a transistor and a capacitor controlled by the transistor, and the memory cells are arranged in an array, and each memory cell is electrically connected to each other through WL and BL. As electronic products are becoming lighter, thinner, shorter, and smaller, in order to increase the integration of DRAM to meet the needs of consumers, DRAMs with embedded WLs have been developed in recent years to meet the above-mentioned needs.

In order to better understand the embodiment of the present application, refer to FIG. 1 , which is a first cross-sectional schematic diagram of a semiconductor structure provided in the embodiment of the present application.

As shown in FIG. 1 , the semiconductor structure includes a substrate 10 , a gate dielectric layer 20 , a metal barrier layer 30 , a metal gate (ie, a word line) 40 , an insulating layer 50 and a gate isolation layer 60 . Wherein, the substrate 10 has a long U-shaped gate trench, and the metal gate 40 is buried in the gate trench through the gate isolation layer 60, and is insulated and isolated from the semiconductor substrate 10 through the gate dielectric layer 20. , source/drain regions are respectively formed in the semiconductor substrate 10 on both sides of the metal gate 40 .

Wherein, the substrate 10 may be any substrate known by those skilled in the art to carry components of semiconductor integrated circuits, such as silicon-on-insulator (silicon-on-insulator, SOI), bulk silicon (bulk silicon), germanium, germanium Silicon, gallium arsenide, or germanium-on-insulator, etc. At least one active region for forming a buried channel array transistor (BCAT) and a shallow trench isolation structure for isolating the active region from the surrounding environment may be defined in the substrate 10, and the active region may be a fin A chip-like three-dimensional structure can also be a planar structure. When the semiconductor gate structure to be fabricated is a word line of a memory, the shallow trench isolation structure can isolate all active regions into an array arrangement to fabricate a memory array of the memory. The above-mentioned shallow trench isolation structure may include a shallow trench in the substrate 10 and a dielectric material filling the shallow trench. The dielectric material may include a liner oxide layer (liner) formed by a thermal oxidation process and covering the shallow trench. oxide) and silicon dioxide that is located on the surface of the liner oxide layer and fills the aforementioned shallow trenches.

In some embodiments, the aforementioned gate trench is formed in the corresponding active region, and its shape may be a U-shape with right angles or a U-shape with rounded corners.

In some embodiments, an active region and a drain region may be respectively formed in the semiconductor substrate 10 on both sides of the gate trench. Further, two gate trenches are arranged side by side in at least one active region of the substrate 10, a drain region is formed in the active region between the two gate trenches, and the two gate trenches are opposite to each other. An active region is formed in the active region on one side, so that two BCATs can be fabricated in one active region, which is beneficial to improve device integration.

The gate dielectric layer 20 covers the sidewall and bottom wall of the gate trench, the metal barrier layer 30 covers the surface of the gate dielectric layer 20 , and the metal gate 40 fills the bottom of the gate trench.

Optionally, the filling thickness of the metal gate 40 may be 1/7˜2/5 of the depth of the gate trench. For example, when the depth of the gate trench is 100 nm˜130 nm, the filling thickness of the metal gate 40 may be 20 nm˜30 nm.

The metal gate 40 may include one or more work function metal layers and a metal electrode layer surrounded by the work function metal layer, wherein the material selection of the work function metal layer is determined by the conductivity type of the BCAT transistor to be formed, when the BCAT transistor to be formed When it is a P-type transistor, the work function metal layer in the metal gate 40 is a p-type work function metal material, and the p-type work function metal material can include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, W and other suitable p-type work function materials or their combinations. When the BCAT transistor to be formed is an N-type transistor, the work function metal layer in the metal gate 40 is an n-type work function metal material, and the n-type work function metal material includes Ti, Ag, TaAl, TaAlC, TiAlN, TaC , TaCN, TaSiN, Mn, Zr, other suitable n-type work function materials or their combinations.

The material of the gate dielectric layer 20 can be a high-K dielectric (dielectric constant K greater than 7), and the material of the high-K dielectric is, for example, Ta2O5, TiO2, TiN, Al2O3, Pr2O3, La2O3, LaAlO3, HfO2, ZrO2 or metals of other components Oxide, etc., are compatible with the metal gate 40, which is beneficial to improve the mobility of carriers and improve the performance of the device.

The metal barrier layer 30 is used to prevent metal ions in the metal gate 40 from diffusing into the gate dielectric layer 20 and the substrate 10, and at the same time improve the adhesion between the gate dielectric layer 20 and the metal gate 40.

The gate isolation layer 60 is filled in the gate trench and fills up the gate trench, and buries the metal gate 40 therein.

Optionally, the material of the gate isolation layer 60 includes but not limited to silicon oxide, silicon nitride and silicon oxynitride.

Optionally, the barrier metal layer 20 may be a metal nitride layer such as TiAlN, TaCN, TaSiN, TiN or TaN, or at least one of metal and metal nitride.

In a feasible implementation manner, the above-mentioned semiconductor structure can be manufactured by the following preparation method, and the preparation method includes the following steps:

S11, prepare a substrate, the upper surface of the substrate is provided with an insulating layer and a SIN layer.

S12, forming a gate trench in the substrate.

S13, forming a gate dielectric layer and a metal barrier layer on the sidewall and bottom wall of the gate trench.

Optionally, thermal oxidation (dry oxygen or wet oxygen) process, chemical vapor deposition, atomic layer deposition and other processes can be used to cover the gate dielectric layer 20 on the sidewall and bottom surface of the gate trench; The material can be a high-K medium (dielectric constant K greater than 7). The material of the high-K medium is, for example, Ta2O5, TiO2, TiN, Al2O3, Pr2O3, La2O3, LaAlO3, HfO2, ZrO2 or metal oxides of other components. It is compatible with the metal gate 103 to be formed, which is conducive to improving the mobility of carriers and improving device performance.

Optionally, the metal barrier layer 30 can be deposited on the surface of the gate dielectric layer 20 by physical vapor deposition, chemical vapor deposition, atomic layer deposition and other processes. The metal barrier layer 30 is also called a metal barrier layer or a metal adhesion barrier layer, and is intended to protect the gate dielectric layer 20 from introducing metal impurities in subsequent steps, and at the same time improve the gap between the gate dielectric layer 20 and the subsequently formed metal gate 40. Adhesion between.

The material of the barrier metal layer 30 may be a metal layer such as Ti or Ta, a metal nitride layer such as TiAlN, TaCN, TaSiN, TiN or TaN, or any one or more combinations of metal and metal nitride.

S14, depositing a W layer into the gate trench, and the W layer covers the surface of the substrate.

In order to better understand the embodiment of the present application. Referring to FIG. 2 , FIG. 2 is a second cross-sectional schematic diagram of a semiconductor structure provided in an embodiment of the present application. In FIG. 2, an insulating layer 50 and a SIN layer 61 are provided on the upper surface of the substrate 10, a gate dielectric layer 20 and a metal barrier layer 30 are formed on the sidewall and bottom wall of the gate trench, and a metal tungsten W layer 70 fills the in the gate trench and cover the surface of the substrate 10 .

S15 , etching the metal barrier layer and the W layer to form a metal gate, and the filling thickness of the metal gate is smaller than the depth of the gate trench.

In order to better understand the embodiment of the present application, refer to FIG. 3 , which is a third schematic cross-sectional structure diagram of a semiconductor structure provided in the embodiment of the present application. In FIG. 3 , after the metal barrier layer 30 and the W layer 70 are etched, the metal gate 40 can be formed.

Optionally, the gate metal material can be deposited on the surface of the metal barrier layer 30 by processes such as evaporation, electroplating, chemical vapor deposition, atomic layer deposition, etc., and then, the gate metal material can be removed by etching back. The gate metal material on the region, and make the gate metal material only fill in the gate trench, used as the metal gate 40, wherein, the filling thickness (or height) of the formed metal gate 40 is smaller than the gate Pole groove depth.

S16, depositing a gate isolation layer, where the gate isolation layer fills the gate trench.

In order to better understand the embodiment of the present application, please refer to FIG. 1. In FIG. in the gate trench.

Optionally, a gate isolation layer 60 can be deposited on the gate trench by using physical vapor deposition, chemical vapor deposition, atomic layer deposition, etc. The material of the gate isolation layer 60 includes but is not limited to silicon oxide, nitride For silicon and silicon oxynitride, the deposited gate isolation layer 60 can at least fill up the gate trench. The top of the gate isolation layer 60 is further planarized to the top surface of the substrate 10 around the gate trench by a chemical mechanical planarization process, so as to remove the gate isolation layer 60 on the substrate 10 around the gate trench, The metal barrier layer 30 and the gate dielectric layer 20 further form a metal gate 40 buried in the gate trench.

Among them, in the process of depositing the gate isolation layer, the by-products generated by the gate isolation layer will directly contact the gate dielectric layer of WL, and the by-products will directly enter the gate dielectric layer under the action of high temperature, causing the electrical property of WL Unstable, which affects the performance of the memory.

For example, refer to FIG. 4 . FIG. 4 is a fourth schematic cross-sectional structure diagram of a semiconductor structure provided in an embodiment of the present application.

In some embodiments, during the process of depositing the gate isolation layer, the by-product H ⁺ generated by the gate isolation layer will directly contact the gate dielectric layer 20, and under the action of high temperature, H ⁺ will directly enter the gate dielectric layer 20 , And then cause WL electrical instability.

In order to solve the above technical problems, an embodiment of the present application provides a method for fabricating a semiconductor structure, the method comprising:

S21. Provide a substrate, the substrate is provided with a gate trench, and the gate trench includes a gate dielectric layer, a metal gate, and a metal barrier layer; wherein, the gate dielectric layer is located on the sidewall and the sidewall of the gate trench On the bottom wall, the metal gate is filled in the gate trench with a gate dielectric layer, and the filling thickness of the metal gate is less than the depth of the gate trench, and the metal barrier layer is located between the gate dielectric layer and the metal gate .

In order to better understand the embodiment of the present application, refer to FIG. 5 , which is a schematic cross-sectional structure diagram 5 of a semiconductor structure provided in the embodiment of the present application.

In FIG. 5 , a gate trench is disposed in the substrate 10 , and the gate trench includes a gate dielectric layer 20 , a metal gate 40 and a metal barrier layer 30 .

In the embodiment of the present application, the filling thickness of the metal gate 40 is smaller than the depth of the gate trench, and the vacant part of the gate trench after forming the gate dielectric layer 20, the metal gate 40 and the metal barrier layer 30 is called the first trench. Slot 80.

S22 , forming a protection layer, the protection layer covering the sidewall and the bottom wall of the first trench 80 .

In order to better understand the embodiment of the present application, refer to FIG. 6 , which is a sixth schematic cross-sectional structure diagram of a semiconductor structure provided in the embodiment of the present application.

In the embodiment of the present application, the protective layer 90 may be formed on the sidewall and bottom wall of the first trench 80 and the upper surface of the substrate 10 by using a spin-on-coat (SOD) dielectric process or an atomic layer deposition (ALD) process.

Optionally, the protective layer 90 is made of oxide, including but not limited to silicon dioxide and/or silicon oxynitride.

Optionally, the protective layer 90 has a thickness of 2nm˜5nm.

S23 , depositing a gate isolation layer, the gate isolation layer is filled in the first trench 80 having the protection layer 90 and covers the upper surface of the substrate 10 .

In order to better understand the embodiment of the present application, refer to FIG. 7 , which is a schematic cross-sectional structural diagram VII of a semiconductor structure provided in the embodiment of the present application.

In the embodiment of the present application, after the protective layer 90 is formed in the first trench 80 , the gate isolation layer 60 can be deposited in the first trench 80 with the protective layer 90 .

It can be understood that, the semiconductor structure manufacturing method provided in the embodiment of the present application can effectively isolate the gate dielectric layer 20 of the WL from the outside world by setting the protective layer 90. Therefore, the gate isolation layer 60 is deposited on the top layer of the WL In this case, the by-products generated by the gate isolation layer 60 can be prevented from directly contacting the gate dielectric layer 20 of the WL, thereby helping to improve the electrical stability of the WL, thereby improving the performance of the memory.

Based on the content described in the above embodiment, a semiconductor structure is also provided in the embodiment of the present application. For details, refer to FIG. 7. In the embodiment of the present application, the above semiconductor structure includes:

The substrate 10 is provided with gate trenches in the substrate 10 .

A gate dielectric layer 20, the gate dielectric layer 20 is located on the sidewall and bottom wall of the gate trench.

A metal gate 40, the metal gate 40 is filled in the gate trench with the gate dielectric layer 20, and the filling thickness of the metal gate 40 is smaller than the depth of the gate trench.

The metal barrier layer 30 is located between the gate dielectric layer 20 and the metal gate 40 .

A protective layer 90, the protective layer 90 covers the sidewall and bottom wall of the first trench, wherein the first trench is a gate trench after the gate dielectric layer 20, the metal gate 40 and the metal barrier layer 30 are formed spare part.

The gate isolation layer 60 , the gate isolation layer 60 is filled in the first trench with the protection layer 90 and covers the upper surface of the substrate 10 .

It can be understood that the semiconductor structure provided by the embodiment of the present application can effectively isolate the gate dielectric layer 20 of the WL from the outside world by setting the protective layer 90. Therefore, when the gate isolation layer 60 is deposited on the top layer of the WL, it is By-products generated by the gate isolation layer 60 can be prevented from directly contacting the gate dielectric layer 20 of the WL, thereby helping to improve the electrical stability of the WL, thereby improving the performance of the memory.

In a feasible implementation manner, the protection layer 90 is also located between the upper surface of the substrate 10 and the gate isolation layer 60 .

In a feasible implementation manner, the material of the protective layer 90 is oxide. Optionally, the material of the oxide includes silicon dioxide and/or silicon oxynitride.

In a feasible implementation manner, the protective layer 90 has a thickness of 2 nm˜5 nm.

In a feasible implementation manner, the gate dielectric layer 20 is made of high dielectric constant material.

In a feasible implementation manner, the material used for the barrier metal layer 30 includes titanium nitride.

In a feasible implementation manner, the material used for the gate isolation layer 20 includes silicon nitride.

Based on the content described in the above embodiment, the embodiment of the present application also provides a memory, which includes the semiconductor structure scanned in the above embodiment, for details, please refer to the description in the above embodiment, and will not repeat it here .

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and are not intended to limit it; although the application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: It is still possible to modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the technical solutions of the various embodiments of the present application. scope.

Claims (16)

A semiconductor structure comprising: a substrate, a gate trench is arranged in the substrate; a gate dielectric layer, the gate dielectric layer is located on the sidewall and bottom wall of the gate trench; a metal gate, the metal gate is filled in the gate trench having the gate dielectric layer, and the filling thickness of the metal gate is smaller than the depth of the gate trench; a metal barrier layer, the metal barrier layer is located between the gate dielectric layer and the metal gate; a protection layer, the protection layer covers the sidewall and the bottom wall of the first trench, and the first trench is used for forming the gate dielectric layer, the metal gate and the metal gate trench. The empty part after the barrier layer; A gate isolation layer, the gate isolation layer is filled in the first trench with the protection layer. The semiconductor structure according to claim 1, wherein the protective layer is further located between the upper surface of the substrate and the gate isolation layer. The semiconductor structure according to claim 1, wherein the protective layer is made of oxide. The semiconductor structure of claim 3, wherein the material of the oxide comprises silicon dioxide and/or silicon oxynitride. The semiconductor structure according to claim 1, wherein the protective layer has a thickness of 2nm˜5nm. The semiconductor structure according to claim 1, wherein the gate dielectric layer is made of high dielectric constant material. The semiconductor structure according to claim 1, wherein the material used for the barrier metal layer comprises titanium nitride. The semiconductor structure according to claim 1, wherein the gate isolation layer is made of silicon nitride, and the gate isolation layer covers the upper surface of the substrate. A method of manufacturing a semiconductor structure, comprising: A substrate is provided, and a gate trench is provided in the substrate, and the gate trench includes a gate dielectric layer, a metal gate, and a metal barrier layer; wherein, the gate dielectric layer is located in the gate trench The metal gate is filled in the gate trench with the gate dielectric layer, and the filling thickness of the metal gate is smaller than the depth of the gate trench, so The metal barrier layer is located between the gate dielectric layer and the metal gate; Forming a protection layer, the protection layer covers the sidewall and the bottom wall of the first trench, and the first trench is the gate dielectric layer, the metal gate and the gate trench formed in the first trench. The vacant part after the metal barrier layer; A gate isolation layer is deposited, and the gate isolation layer is filled in the first trench with the protection layer. The method according to claim 9, wherein said forming a protective layer comprises: The protective layer is formed on the sidewall and bottom wall of the first trench and the upper surface of the substrate by using a spin-on-dielectric process. The method according to claim 9, wherein said forming a protective layer comprises: The protective layer is formed on the sidewall and bottom wall of the first trench and the upper surface of the substrate by atomic layer deposition process. The method according to claim 9, wherein the protective layer is made of oxide. The method according to claim 12, wherein the material of the oxide comprises silicon dioxide and/or silicon oxynitride. The method according to claim 12, wherein the protective layer has a thickness of 2nm˜5nm. The method according to claim 12, wherein the gate dielectric layer is made of high dielectric constant material, the metal barrier layer is made of titanium nitride, and the gate isolation layer is made of silicon nitride. A memory comprising the semiconductor structure according to any one of claims 1 to 8.

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