CN208655649U - Semiconductor devices - Google Patents
Semiconductor devices Download PDFInfo
- Publication number
- CN208655649U CN208655649U CN201821504075.3U CN201821504075U CN208655649U CN 208655649 U CN208655649 U CN 208655649U CN 201821504075 U CN201821504075 U CN 201821504075U CN 208655649 U CN208655649 U CN 208655649U
- Authority
- CN
- China
- Prior art keywords
- metal
- gate
- layer
- source
- conductive contact
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Semiconductor Memories (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The utility model provides a kind of semiconductor devices, compound grid is formed by the way that polysilicon gate to be stacked in above metal gates, the field distribution of compound grid and source electrode, drain overlapping areas can be improved, thus, it being capable of compatible metal grid and the advantages of polysilicon gate, in the case where guaranteeing that grid has low-resistance value, additionally it is possible to the leakage current of grid and source electrode, drain overlapping areas is reduced, to improve device efficiency and reliability.Further, so that the first conductive contact structure below the conducting wire is the composite construction mainly stacked by metal layer and polysilicon layer, it can reduce contact resistance, improve device performance.
Description
Technical field
The utility model relates to ic manufacturing technology field, in particular to a kind of semiconductor devices.
Background technique
Dynamic random access memory (Dynamic Random Access Memory, abbreviation DRAM) is as known in one kind
Semiconductor storage, be widely used in various electronic equipments at present.Dynamic random access memory (DRAM) is by being permitted
Mostly duplicate storage unit (cell) composition, each storage unit are mainly manipulated with one by transistor by a transistor
Capacitor constituted, and storage unit can be arranged in array format, each storage unit passes through wordline (word line, letter
It is written as WL) it is electrically connected to each other with bit line (bit line, be abbreviated as BL).
To improve the integrated level of dynamic random access memory (DRAM) and accelerate the service speed of element, and meets and disappear
Demand of the person of expense for miniaturized electronic device, transistor channels section length in recent dynamic random access memory (DRAM)
Design have the tendency that lasting shortening, consequently transistor can generate serious short-channel effect (short channel
Effect the problems such as) and conducting electric current (on current) declines.A kind of known solution is by dynamic randon access
The transistor arrangement of horizontal direction in memory (DRAM) is changed to the buried channel array transistor (Buried of vertical direction
Channel Array Transistor, BCAT) structure, this dynamic with buried channel array transistor (BCAT) with
Machine access memory (DRAM) structure it is as shown in Figure 1, comprising: semiconductor substrate 100, grid (i.e. the wordline of DRAM) 104 with
And conducting wire (i.e. the bit line of DRAM) 111.The grid 104 of word BCAT is embedded in semiconductor substrate 100 by gate isolation 106
In U-shaped lengthwise groove (not shown), and it is dielectrically separated from by gate dielectric layer 102 with semiconductor substrate 100,104 two sides of grid
It is respectively formed in semiconductor substrate 100 source/drain region (not shown), conducting wire 111 passes through the first conductive contact structure 109 and grid
The source/drain region of 104 sides connects, and the source/drain region of 104 other side of wordline is (i.e. conductive by the second conductive contact structure of top
Plug) 113 extractions outward, conducting wire 111 and the second conductive contact structure 113 are both formed in interlayer dielectric layer 112.Due to electric current
Between source region (i.e. the source/drain region of 104 side of grid) and drain region (positioned at the source/drain region of the other side of grid 104, not shown)
It is flowed through along the U-shaped lengthwise trench portions with needing to detour, therefore actually active channel length is elongated, this is just reduced respectively
Area shared by BCAT transistor in a storage unit, while short-channel effect can be inhibited.
The wordline of existing dynamic random access memory mostly uses metal material to be formed, i.e. the grid of the BCAT of storage unit
Pole 104 is mostly metal gates, and relative to polysilicon gate, metal gates have low resistance characteristic, and channel switch is controlled
Ability is preferable, but in when channel is in close state, metal gates will cause the electric leakage of grid Yu source electrode, drain overlapping areas
It flows (such as GIDL, Gate Induced Drain leakage), this will affect the efficiency and reliability of storage unit, or even cause
The problems such as data access mistake of DRAM.
In consideration of it, it is necessary to design a kind of new semiconductor devices, to solve the above problems.
Utility model content
The purpose of this utility model is to provide a kind of semiconductor devices, it is capable of compatible metal grid and polysilicon gate
Advantage, in the case where guaranteeing that grid has low-resistance value, additionally it is possible to reduce the electric leakage of grid Yu source electrode, drain overlapping areas
Stream, to improve device efficiency and reliability.
In order to solve the above technical problems, the utility model provides a kind of semiconductor devices, comprising:
Semiconductor substrate with gate trench；
Metal gates are filled in the gate trench, and the height of the metal gates is less than the gate trench
Depth；And
Polysilicon gate is filled in the gate trench, and the polysilicon gate is stacked on the metal gates.
Optionally, top table of the top surface of the polysilicon gate lower than the semiconductor substrate in the gate trench sidewalls
Face, the semiconductor devices further include: gate isolation is filled in the gate trench, and the gate isolation fills up institute
Gate trench is stated, the metal gates and the polysilicon gate are buried in interior.
Optionally, the semiconductor devices further includes gate dielectric layer and metal barrier, and the gate dielectric layer is formed in
On the side wall and bottom wall of the gate trench, the metal barrier be formed in the gate dielectric layer and the metal gates it
Between, it is enclosed on the bottom wall and side wall of the metal gates and exposes the gate dielectric layer table above the metal gates
Face, the side wall of the polysilicon gate are directly connect with the gate dielectric layer by the sidewall surfaces that the metal barrier exposes
Touching.
Optionally, the semiconductor devices further include:
First conductive contact structure is formed in the semiconductor substrate of the gate trench side；
Conducting wire is formed on first conductive contact structure；
Interlayer dielectric layer is covered on the gate trench and the semiconductor substrate, and the interlayer dielectric layer will be described
In conducting wire and first conductive contact structure are buried in；And
Second conductive contact structure is formed in the interlayer dielectric layer, the bottom surface of second conductive contact structure
It is contacted with the surface of the semiconductor substrate of the gate trench other side.
Optionally, at least one active area is formed in the semiconductor substrate, being arranged side by side in the active area has two
A gate trench is formed with the first source/drain region, two grid ditches in the active area between two gate trench
The second source/drain region is respectively formed in the active area of the opposite side of slot, first conductive contact structure is formed in described
Above one source/drain region and bottom surface is contacted with the top surface of first source/drain region, and second conductive contact structure is formed in
Above second source/drain region and bottom surface is contacted with the top surface of second source/drain region.
Optionally, it is formed with gap between first conductive contact structure and the opposite side wall of the gate trench, institute
It states interlayer dielectric layer and fills up the gap.
Optionally, first conductive contact structure is composite construction, including metal layer and is stacked on the metal layer
The polysilicon layer of top, the material of the conducting wire include metal.
Compared with prior art, the technical solution of the utility model has the advantages that
1, the semiconductor devices of the utility model, it is compound to be formed above metal gates by the way that polysilicon gate to be stacked in
Grid can improve the field distribution of compound grid and source electrode, drain overlapping areas, and thereby, it is possible to compatible metal grids and more
The advantages of polysilicon gate, in the case where guaranteeing that grid has low-resistance value, additionally it is possible to reduce grid and source electrode, drain electrode overlay region
The leakage current in domain, to improve device efficiency and reliability.Further, so that below conducting wire (bit line i.e. in memory)
One conductive contact structure is the composite construction mainly stacked by metal layer and polysilicon layer, can reduce contact resistance, improves device
Part performance.
2, the semiconductor devices of the utility model is especially suitable for tool suitable for any product manufacturing with metal gates
There is the dynamic random of the structure of buried channel array transistor (Buried Channel Array Transistor, BCAT) to deposit
Access to memory (DRAM), can improve because grid and source electrode, drain overlapping areas leakage path caused by DRAM data
The problems such as access errors, improves the performance of DRAM.
Detailed description of the invention
Fig. 1 is that the schematic diagram of the section structure of known DRAM with BCAT a kind of (illustrates only at an active area
Structure).
Fig. 2 is the preparation method flow chart of the semiconductor devices of the utility model specific embodiment.
Fig. 3 A to 3I is the device architecture diagrammatic cross-section in the preparation method of semiconductor devices shown in Fig. 2.
Fig. 4 is the device architecture diagrammatic cross-section of the semiconductor devices of an embodiment of the present invention.
Wherein, appended drawing reference is as follows:
100- semiconductor substrate；
The first source/drain region 1002-；
The second source/drain region 1003-；
101- gate trench；
102- gate dielectric layer；
103,1042,1094,1097- metal barrier；
104- metal gates；
1041,1093,1098- metal adhesion layers；
1043,1095,1096- metal silicide layer
105- polysilicon gate；
106- gate isolation；
107- hard mask layer；
108- contact trench；
The gap 108a-；
The first conductive contact structure of 109-；
Metal layer in the first conductive contact structure of 1091-；
Polysilicon layer in the first conductive contact structure of 1092-；
110- sacrificial layer；
111- conducting wire (when semiconductor devices is memory, the conducting wire is bit line)；
112- interlayer dielectric layer；
The second conductive contact structure of 113-.
Specific embodiment
Below in conjunction with the drawings and specific embodiments to the utility model proposes integrated circuit memory and preparation method thereof
It is described in further detail.According to following explanation, will be become apparent from feature the advantages of the utility model.It should be noted that attached drawing
It is all made of very simplified form and uses non-accurate ratio, only to facilitate, lucidly aid in illustrating the utility model
The purpose of embodiment.
Referring to FIG. 2, an embodiment of the present invention provides a kind of preparation method of semiconductor devices, including following step
It is rapid:
S1 provides the semiconductor substrate with gate trench；
S2 fills metal gates in the gate trench, and the height of the metal gates is less than the gate trench
Depth；And
S3 fills polysilicon gate in the gate trench, and the polysilicon gate is stacked on the metal gates,
To form compound grid；
S4 fills gate isolation in the gate trench, and forms the first conductive contact structure, conducting wire stack in institute
In the semiconductor substrate for stating gate trench side；
S5 forms interlayer dielectric layer in the semiconductor substrate and the gate isolation, and forms the second conduction and connect
Structure is touched in the interlayer dielectric layer, the conducting wire is buried in interior, the second conductive contact knot by the interlayer dielectric layer
Structure is contacted with the semiconductor substrate of the gate trench other side.
Fig. 3 A is please referred to, firstly, executing step S1, provides the semiconductor substrate 100 with gate trench 101, specific mistake
Journey includes:
Step 1: providing semi-conductive substrate 100, semiconductor substrate 100 can be well known to those skilled in the art
What ground to bearing semiconductor integrated circuit constituent element, such as silicon-on-insulator (silicon-on-insulator,
SOI), body silicon (bulk silicon), germanium, germanium silicon, GaAs or germanium on insulator etc..Semiconductor substrate in the present embodiment
100 include the semiconductor epitaxial layers (not shown) that epitaxial growth comes out on substrate 1001 and its surface.The semiconductor substrate 100
In can define be used to form buried channel array transistor (BCAT) at least one active area (it is not shown, be formed in institute
State in semiconductor epitaxial layers) and fleet plough groove isolation structure for keeping apart the active area with surrounding enviroment (do not scheme
Show), the active area can be the stereochemical structure of fin type, be also possible to planar structure.When semiconductor devices to be produced is
When memory, fleet plough groove isolation structure can be by all active area isolations at array arrangement, to make the storage battle array of memory
Column.The fleet plough groove isolation structure may include a shallow trench (not shown) being located in the semiconductor substrate 100 and filling
The dielectric material of the shallow trench, the dielectric material may include forming and being covered on the shallow trench by thermal oxidation technology
Lining oxide layer (line oxide) and on the surface of lining oxide layer and fill up the silica of the shallow trench, thus
The isolation performance of fleet plough groove isolation structure is improved, specific forming process includes: that (1) passes through thermal oxidation technology in semiconductor substrate
Pad oxide (not shown) is formed on 100 surface；(2) silicon nitride hard mask layer is formed (not by chemical vapor deposition process
Diagram), and further formed on silicon nitride hard mask layer graphically by photoetching processes such as photoresist coating, exposure, developments
Photoresist layer (not shown), the graphical photoresist layer cover each layer of the active area and its top, and expose active
The silicon nitride hard mask floor of 100 top of semiconductor bottom between area as isolated area；It (3) is to cover with the graphical photoresist layer
The semiconductor substrate 100 of film, pad oxide and partial depth to the silicon nitride hard mask layer exposed and below executes
Etching technics, to form shallow trench in the semiconductor substrate 100 between active area, the etching technics can lose for dry method
It carves；(4) the graphical photoresist layer is removed；(5) lining oxide layer can be formed by gas-phase deposition or thermal oxidation technology
On the side wall and bottom surface of (line oxide, not shown) Yu Suoshu shallow trench；(6) techniques such as chemical vapor deposition are used, to
Deposit silica on the surface of the shallow trench and the surface of silicon nitride hard mask layer, until silica fill up it is described shallow
Groove；(7) top surface planarization is carried out to the silica using CMP process, until the silica
Top surface flushed with the top surface of the silicon nitride hard mask layer, to form fleet plough groove isolation structure；(8) wet process can be used
The techniques such as etching remove the silicon nitride hard mask layer.Further, after depositing silica, or to the titanium dioxide
It further include being moved back using the high warm after silicon carries out top surface planarization, or after the removal silicon nitride hard mask layer
The high energy light such as fire, ultraviolet light (UV) or laser (laser) intensify technique etc. and execute densification to the silica
(densification), to increase the compactness of dielectric material, it is ensured that the isolation effect of fleet plough groove isolation structure, and strengthen
Its mechanical strength.The process temperatures of the high-temperature thermal annealing technique are, for example, 800 DEG C~1200 DEG C, are executing high-temperature thermal annealing work
Ozone (O can be also further passed through when skill3) and/or the strong reactivities gas such as carbon monoxide (CO).In addition, formed shallow trench every
After structure, ion implantation technology can be passed through and be formed in each active area and formed further combined with techniques such as annealing activation
Well region (not shown), wherein the doping type of the well region is determined by the conduction type for the BCAT transistor that need to be formed, such as sheet
In embodiment, if being formed by BCAT transistor is N-type transistor, the well region is P-doped zone.The doping of the well region
Depth can be adjusted according to actual state.It should be noted that above-mentioned pad oxide can form shallow trench isolation knot
Protect semiconductor substrate 100 and active area, the pad oxide that can continue to retain during structure, conduct in the subsequent process
The protective layer of the top surface of semiconductor substrate 100 and active area.
Step 2 sequentially forms on the surface of fleet plough groove isolation structure and pad oxide also please continue to refer to Fig. 3 A
Patterned hard mask layer (not shown), specific forming process include: that (1) can be by chemical vapor deposition (CVD), physics gas
Mutually the deposition techniques such as (PVD) or atomic layer deposition (ALD) are formed on the surface with fleet plough groove isolation structure and pad oxide
Hard mask layer, the material of the hard mask layer include silicon nitride, silicon oxynitride, siloxicon, carbonitride of silicium, metal nitride,
At least one of metal oxide and metal carbides, preferably silicon nitride (SiN), silicon nitride material is easy to get, at low cost, system
Make method maturation, and with pad oxide etching selection ratio with higher；(2) it can be coated by photoresist, be covered using grid
Exposure, the development of diaphragm plate (gate mask, when the semiconductor devices of production is memory, which is wordline mask plate)
Etc. a series of photoetching processes, the opening for defining grid (i.e. wordline) is formed；(3) it is with the photoresist layer with the opening
Exposure mask etches hard mask layer to pad oxide surface, grid (i.e. wordline) pattern in photoresist is transferred to hard mask layer
In；(4) photoresist is removed, and using hard mask layer as exposure mask, continues etching downwards, that is, be sequentially etched pad oxide and part is deep
The semiconductor substrate 100 (including active area and fleet plough groove isolation structure) of degree, to form grid in the semiconductor substrate 100
Pole groove 101.In the present embodiment, the bottom of gate trench 101, which is returned with thanks, to be extended downwardly into substrate 1001.The shape of gate trench 101
Shape can be fillet U-shaped, right-angled U or wide at the top and narrow at the bottom trapezoidal.Due to the electricity of buried channel array transistor (BCAT)
Characteristic can change according to the depth from the upper surface of semiconductor substrate (i.e. top surface) to the bottom surface of its buried gate,
Therefore, the depth for adjusting gate trench 101, can achieve the electrology characteristic of the buried channel array transistor (BCAT) of requirement,
To improve the electric property and reliability of finally formed semiconductor devices.
Step 3 can be removed also please continue to refer to Fig. 3 A by etching technics or CMP process etc.
Pad oxide, hard mask layer etc. on 100 surface of semiconductor substrate, and further progress is cleaned, it is clean active to expose
The side wall and bottom surface of area surface and gate trench 101, are prepared with the formation for compound grid.In the present embodiment, in institute
State the gate trench 101 there are two being arranged side by side in an active area of semiconductor substrate 100, two gate trench
Active area between 101 is being subsequently used for being formed the first source/drain region, the opposite side of two gate trench 101 it is active
Area is being subsequently used for being respectively formed the second source/drain region, it is possible thereby to make two BCAT in an active area, is conducive to improve
Device integration.
Please continue to refer to Fig. 3 A, in step s 2, metal gates 104 are filled in the gate trench 101, detailed process
Include:
Step 1 can use the techniques such as thermal oxide (dry oxygen or wet oxygen) technique, chemical vapor deposition, atomic layer deposition,
Gate dielectric layer 102 is covered on the side wall and bottom surface of the active area and gate trench 101, the gate dielectric layer 102
Material is preferably high K dielectric (dielectric constant K is greater than 7), and the material of high K dielectric is, for example, Ta2O5、TiO2、TiN、Al2O3、
Pr2O3、La2O3、LaAlO3、HfO2、ZrO2Or metal oxide of other components etc., with the metal gates 104 that will be formed
It is compatible, be conducive to the mobility for improving carrier, improve device performance.And preferably using atom layer deposition process (ALD) come
The gate dielectric layer 102 of high K dielectric material is prepared, to keep the quality of forming film and caliper uniformity of gate dielectric layer 102.
Step 2, by techniques such as physical vapour deposition (PVD), chemical vapor deposition, atomic layer depositions, in gate dielectric layer 102
Deposited metal barrier layer 103 on surface, it is preferred to use atom layer deposition process prepares metal barrier 103, to protect grid to be situated between
Matter layer 102 prevents 102 mass of gate dielectric layer to be deteriorated.Metal barrier 103 is also referred to as metal barrier or metal adhesion stops
Layer, it is intended to protect gate dielectric layer 102 not introduce metal impurities in the next steps, while improve gate dielectric layer 102 and metal
Adhesion strength between grid 104.For example, in the present embodiment, metal gates 104 include one or more workfunction layers.
In the case where no metal barrier 103, the metal material from those workfunction layers will diffuse to gate dielectric layer 102
It is interior, to cause manufacturing defect.In various embodiments, metal barrier 103 include the metal layers such as Ti or Ta, TiAlN,
Any multiple combinations in the metal nitride layers such as TaCN, TaSiN, TiN or TaN or metal and metal nitride.It should recognize
Know, in some cases, the metal barrier 103 of single layer may not provide enough protections to gate dielectric layer 102, need
The metal barrier 103 with the composite construction of multiple-level stack is formed in gate trench 101, is enhanced to gate dielectric layer 102
Protection, to avoid surface layer metal barrier 103 when being etched and being damaged, the material in metal gates 104 will pollute
It diffuses in gate dielectric layer 102, leads to device defects.
Step 3, by techniques such as vapor deposition, plating, chemical vapor deposition, atomic layer depositions, in the metal barrier
Deposited metal grid material on 103 surface, deposition of thick of the metal gate material on 101 bottom surface of first grid groove
Thickness needed for degree will at least reach the metal gates 104 needed to form.
Step 4, can be by being etched back to remove the metal gate material on the region other than gate trench 101, and makes
Metal gate material is only filled in gate trench 101, is used as metal gates 104, and this is etched back to technique and makes metal gate
The height of pole 104 is less than the depth of gate trench 101, and the height of metal barrier 103 is reduced to not higher than metal gate
Pole 104.Wherein, metal gates 104 are usually laminated construction, including the workfunction layers being covered on metal barrier 103
And the metal electrode layer that the workfunction layers are surrounded.Wherein the selection of workfunction layers is by the BCAT crystal that need to be formed
The conduction type decision of pipe, the workfunction metal when the BCAT transistor that need to be formed is P-type transistor, in metal gates 104
Layer is p-type workfunction metal material, and the p-type work function metal material may include TiN, TaN, Ru, Mo, Al, WN, ZrSi2、
MoSi2、TaSi2、NiSi2, other suitable p-type work function materials of W or their combination, when the BCAT transistor that need to be formed is N-type
When transistor, workfunction layers in metal gates 104 are N-shaped workfunction metal material, the N-shaped workfunction metal material
Material include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable N-shaped work function materials or they
Combination.Workfunction layers can be single layer, be also possible to multiple layers.The top surface of metal gates 104 is low in the present embodiment
In the top surface of the semiconductor substrate 100 of two sides, and then lower than the first source/drain region 1002 and the second source/drain region being subsequently formed
1003 top surface, thus make between workfunction layers and first source/drain region 1002 and the second source/drain region 1003 away from
From increase, it is beneficial to prevent workfunction layers and grid cause leakage occurs between the first source/drain region 1002 and the second source/drain region 1003
Electrode current reveals (gated-induce drain leakage, GIDL).The material of metal electrode layer may include Al, W, Cu
And/or other suitable metal materials.
Fig. 3 B is please referred to, in step s3, fills polysilicon gate 105 in the gate trench 101, detailed process packet
It includes:
Step 1, using atom layer deposition process deposited metal adhesion layer 1141, metal barrier 1142 and metallic silicon
Compound layer 1143.Wherein, the adhesion strength between metal gates 104 and polysilicon gate 105 can be enhanced in metal adhesion layers 1141,
Finally formed compound grid fracture is prevented, the material for belonging to adhesion layer 1141 can be the metals such as W, Ti or Ta；Metal barrier
1142 can prevent the metal in metal gates 104 to be diffused into polysilicon gate 105, and influence metal gates 104 and polycrystalline
The performance of silicon gate 105, the material of metal barrier 1142 can be the nitride metals such as TiAlN, TaCN, TaSiN, TiN or TaN
Object；Metal silicide layer 1143 can reduce the contact resistance between metal gates 104 and polysilicon gate 105, to reduce shape
At compound grid resistance value, metal silicide layer 1143 can be comprising in the metallic elements such as Ti, W, Co, Ni, Zr, Mo, Ta
At least one metal silicide.
Step 2, can be using techniques such as physical vapour deposition (PVD), chemical vapor deposition, atomic layer depositions, in gate dielectric layer
102, depositing polysilicon material on the surface of metal barrier 103, metal gates 104 and semiconductor substrate 100, the polycrystalline
Silicon materials may include at least one of the polysilicon adulterated and undoped polysilicon, the doping of the polysilicon of the doping
Ionic type is identical as the Doped ions type of the first source/drain region 1002 to be formed and the second source/drain region 1003.
Step 3 can be etched back the polycrystalline silicon material of deposition using dry etching or wet-etching technology,
To remove the polycrystalline silicon material on the region other than gate trench 101, and polycrystalline silicon material is made only to be filled in gate trench
In 101, as the polysilicon gate 105 being layered on metal gates 104.
Fig. 3 B to Fig. 3 G is please referred to, in step s 4, fills gate isolation 106 in the gate trench 101, and shape
It is laminated at the first conductive contact structure 109, conducting wire 111 in the semiconductor substrate 100 of 101 side of gate trench, specifically
Process includes:
Step 1: please refer to Fig. 3 B and 3C, using techniques such as physical vapour deposition (PVD), chemical vapor deposition, atomic layer depositions,
In semiconductor substrate 100 and polysilicon gate 105 deposit gate isolation 106, the material of gate isolation 106 include but
It is not limited to silica, silicon nitride and silicon oxynitride.
Step 2: please referring to Fig. 3 C, can be removed on 100 top surface of semiconductor substrate by CMP process
Extra gate isolation 106 and gate dielectric layer 102, it is described multiple to form the compound grid that is embedded in gate trench 101
Closing grid includes metal gates 104 and stacking polysilicon gate 105 thereon, and further with the compound grid, grid every
Absciss layer 106 is exposure mask, carries out LDD (lightly doped drain) ion note to the active area of compound grid (i.e. gate trench 101) two sides
Enter, Halo (halo) ion implanting and source and drain heavy doping ion injection etc., in the compound grid (i.e. gate trench 101)
The first source/drain region 1002 and the second source/drain region 1003 are respectively formed in the active area of two sides, as a result, compound grid and separation institute
State the first source/drain region 1002 of compound grid two sides and the major part of the second source/drain region 1003 composition BCAT structure.In this reality
It applies in example, due to forming two gate trench 101 in an active area, an active area can produce two BCAT,
And the first shared source/drain region 1002 of the two BCAT is formed in the active area between two gate trench 101, it is described to share
The first source/drain region 1002 can be with the drain region being electrically connected with the conducting wire 111 (i.e. the bit line of memory) being subsequently formed, second
Source/drain region 1003 can be with the source region being electrically connected with the second conductive contact structure being subsequently formed.In its of the utility model
It, can also be by etching technics between described two compound grids and on the outside of described two compound grids in his embodiment
Gate dielectric layer 102 and gate isolation 106 in surfaces of active regions perform etching, and are used to form first to be formed to expose
The opening on the surface of the active area of source/drain region 1002 and the second source/drain region 1003, then, with remaining gate dielectric layer 102 and
Gate isolation 106 is exposure mask, to the active area that exposes carry out LDD (lightly doped drain) ion implanting, Halo (halo) from
Son injection and the injection of source and drain heavy doping ion etc., to form the first source/drain region in the active area of the compound grid two sides
1002 and second source/drain region 1003.When gate trench 101 is U-lag, (that is, separation is multiple on the conducting direction along electric current
The source region of grid two sides is closed to the current flowing direction in drain region) U-shaped conducting channel can be formed, to improve conducting channel
Length.In this way, with the reduction of transistor size, even if the absolute distance between the source region and drain region of compound grid two sides
Reduction, however, being U-shaped channel due to being formed by conducting channel, so as to be effectively improved the short-channel effect of transistor arrangement.
Moreover, because compound grid is mainly formed by polysilicon gate and metal gates stacked together, therefore can improve compound
The field distribution of the overlapping region of grid and first source/drain region 1002 and the second source/drain region 1003, thereby, it is possible to compatibilities
The advantages of metal gates and polysilicon gate, in the case where guaranteeing that grid has low-resistance value, additionally it is possible to reduce grid and institute
The leakage current of the overlapping region of the first source/drain region 1002 and the second source/drain region 1003 is stated, to improve device efficiency and reliability.
In addition, the transistor arrangement of first source/drain region 1002 and the second source/drain region 1003 according to different conduction-types, described
The ion of corresponding conduction type is adulterated in one source/drain region 1002 and the second source/drain region 1003, such as the transistor arrangement is N
When transistor npn npn, then the Doped ions in the source/drain region are n-type doping ion, and the n-type doping ion is, for example, phosphorus (P)
Ion, arsenic (As) ion, antimony (Sb) ion；When the transistor arrangement is P-type transistor, then the doping in the source/drain region
Ion is p-type Doped ions, and the p-type Doped ions are, for example, boron (B) ion, boron fluoride (BF2 +) ion, gallium (Ga) ion,
Indium (In) ion.
Step 3: please referring to Fig. 3 D, hard mask layer 107 is formed in semiconductor substrate 100 and gate isolation 106, and
The hard mask layer 107 of 1002 top of the first source/drain region is opened by photoetching, etching technics, formation exposes the first source/drain region
The opening on 1002 surfaces.
It is exposure mask with the hard mask layer 107 with the opening Step 4: please referring to Fig. 3 D, etches first source/drain
Area 1002 forms contact trench 108, the bottom surface of contact trench 108 is higher than the top table of polysilicon gate 105 to certain depth
Face.And in the present embodiment, the contact trench 108 is connected to two gate trench 101 respectively in side wall.
Step 5: Fig. 3 D and 3E are please referred to, by using physical vapour deposition (PVD), chemical vapor deposition, atomic layer deposition etc.
Technique, the depositing polysilicon material on the surface of contact trench 108 and hard mask layer 107, until the polycrystalline silicon material of deposition
Fill up the contact trench 108, the polycrystalline silicon material may include in the polysilicon and undoped polysilicon of doping extremely
Few one kind.Further removed other than hard mask layer 107 and contact trench 108 using chemical-mechanical planarization (CMP) technique
Polycrystalline silicon material forms the first conductive contact structure 109.
Step 6: Fig. 3 F and 3G are please referred to, it can be using works such as rotary coating, chemical vapor deposition, physical vapour deposition (PVD)s
Skill forms sacrificial layer 110 and is covered in the gate isolation 106, the semiconductor substrate 100 and first conductive contact
In structure 109, and opening 110a is further formed in the sacrificial layer 110 by photoetching, etching etc., the width for the 110a that is open is small
The width of contact trench 108 shown in Fig. 3 D, to expose the portion top surface of first conductive contact structure 109；
The deposition thickness of the sacrificial layer 110 can determine that the height of conducting wire 110, material can be silica, silicon nitride, nitrogen oxidation
Silicon, the silicate glass (FSG) of Fluorin doped, low k dielectric and/or other suitable insulating materials.
Step 7: please refer to Fig. 3 F and 3G, by techniques such as vapor deposition, plating, chemical vapor deposition, atomic layer depositions,
Al, W, Cu and/or other suitable metal materials are filled up in the opening 110a, and further use chemical-mechanical planarization work
Skill removes the metal material at 110 top of sacrificial layer, to form conducting wire 111.
Step 8: please refer to Fig. 3 G and Fig. 3 H, sacrificial layer 110 is removed using the suitable technique such as etching, and further with
Conducting wire 111 is exposure mask, etches the first conductive contact structure 109, etching stopping is in the first source-drain area 1002 and the first conductive contact
The interface of structure 109, to form gap 108a, at this point, first conductive contact structure 109 and the conducting wire 111 are wide.
Referring to FIG. 4, the first conductive contact structure 109 is also possible to compound in the other embodiments of the utility model
Structure is mainly made of metal layer 1091 and the polysilicon layer 1092 being layered on metal layer 1091, it is possible thereby to reduce contact
Resistance, and avoid with conducting wire 111 be the first conductive contact structure 109 of mask etching when, remaining first conductive contact structure 109
Side wall the problem of sectional area becomes smaller due to laterally etched.In an embodiment of the utility model, metal layer 1091 and first
Successively there are metal silicide layer (not shown), metal barrier (not shown) and metal viscous between source-drain area 1002 from bottom to top
Attached layer (not shown), wherein the adhesion strength between metal layer 1091 and the first source-drain area 1002 can be enhanced in metal adhesion layers, prevents
Only 1002 poor contact of the first conductive contact structure 109 and the first source-drain area, the material of metal adhesion layers can be W, Ti or Ta
Equal metals；Metal barrier can prevent the metal in metal layer to be diffused into the first source-drain area 1002, and influence the first source and drain
The performance in area 1002, the material of metal barrier can be the metal nitrides such as TiAlN, TaCN, TaSiN, TiN or TaN；Metal
Silicide layer can reduce the contact resistance between metal layer and the first source-drain area 1002, and metal silicide layer, which can be, includes
The metal silicide of at least one of the metallic elements such as Ti, W, Co, Ni, Zr, Mo, Ta.In another implementation of the utility model
In example, metal adhesion layers 1093, metal barrier are sequentially formed between metal layer 1091 and polysilicon layer 1092 from bottom to top
1094, it is sequentially formed with metal silicide layer from bottom to top between metal silicide layer 1095, polysilicon layer 1092 and bit line 111
1096, metal barrier 1097, metal adhesion layers 1098, wherein metal layer 1091 and more can be enhanced in metal adhesion layers 1093
Adhesion strength between crystal silicon layer 1092, the case where preventing metal layer 1091 and 1092 poor contact of polysilicon layer or even crack, gold
Belonging to adhesion layer 1098 can be enhanced the adhesion strength between conducting wire 111 and polysilicon layer 1092, prevent bit line 111 and polysilicon layer
The material of the case where 1092 poor contacts are even cracked, metal adhesion layers 1093,1098 can be the metals such as W, Ti or Ta；Metal
Barrier layer 1094 can prevent the metal in metal layer 1091 to be diffused into polysilicon layer 1092, and metal barrier 1097 can be to prevent
Only the metal in conducting wire 111 is diffused into polysilicon layer 1092, the material of metal barrier 1094,1097 can be TiAlN,
The metal nitrides such as TaCN, TaSiN, TiN or TaN；Metal silicide layer 1095 can reduce metal layer 1091 and polysilicon layer
Contact resistance between 1092, and further the metal in barrier metal layer 1091 is spread into polysilicon layer 1092, metallic silicon
Compound layer 1096 can reduce the contact resistance between conducting wire 111 and polysilicon layer 1092 and further stop in conducting wire 111
Metal is spread into polycrystal layer 1092, and metal silicide layer 1095,1096 can be comprising gold such as Ti, W, Co, Ni, Zr, Mo, Ta
Belong to the metal silicide of at least one of element.
Fig. 3 H, 3I and Fig. 4 are please referred to, in step s 5, it is possible, firstly, to using rotary coating, chemical vapor deposition, object
The techniques such as physical vapor deposition further combined with CMP process, can form the interlayer dielectric layer 112 of top planar,
To be covered in the gate isolation 106, the first source/drain region 1002, the second source/drain region 1003, the first conductive contact knot
On structure 109 and conducting wire 111, interlayer dielectric layer 112 fills up gap 108a, and the conducting wire 111 and first conduction are connect
In touching structure 109 is buried in, the material of interlayer dielectric layer 112 described in the interlayer dielectric layer 112 can be silica, nitridation
Silicon, silicon oxynitride, the silicate glass (FSG) of Fluorin doped, low k dielectric and/or other suitable insulating materials.Then,
By techniques such as photoetching, etchings in the interlayer dielectric layer 112, (do not schemed with forming the contact hole of the second source/drain region 1003 of alignment
Show), the contact holes exposing goes out the top surface of the second source/drain region 1003, to expose first conductive contact structure 109
Portion top surface.Then, metal material is filled to the contact hole by the techniques such as being electroplated, sputtering, and then it is conductive to form second
Contact structures 113 (i.e. conductive contact plug) are filled in the contact hole of the interlayer dielectric layer 112, second conductive contact
The bottom surface of structure 113 is contacted with the top surface of the second source/drain region 1003.
The preparation method of the semiconductor devices of the utility model substantially replaces with existing single metal gates by more
Polysilicon gate is stacked in above metal gates and the compound grid of formation, so as to improve compound grid and source electrode, drain electrode weight
The advantages of field distribution in folded region, thereby, it is possible to compatible metal grid and polysilicon gates, is guaranteeing grid with low resistance
In the case where value, additionally it is possible to the leakage current of grid and source electrode, drain overlapping areas is reduced, to improve device efficiency and reliability.
Further, so that the first conductive contact structure below conducting wire (bit line i.e. in memory) is mainly by metal layer and polycrystalline
The composite construction of silicon layer stack can reduce contact resistance, improve device performance, the production especially suitable for memory.When this
When the preparation method of the semiconductor devices of utility model is applied to production memory, the compound grid of multiple active areas is aligned setting
And link together and be formed the wordline of memory, the alignment of conducting wire 111 of multiple active areas is arranged and links together with regard to shape
At the bit line of memory.For example, Fig. 3 A to 3I is please referred to, and in an embodiment of the utility model, the semiconductor substrate
With multiple active areas arranged in cell row (corresponding to word-line direction) and cell columns (corresponding to bit line direction), phase in 100
Fleet plough groove isolation structure is additionally provided between adjacent active area, i.e., all fleet plough groove isolation structures may include several being parallel to each other
And mutually intersect several, the array structure that thus all active area isolations are arranged at cell row and cell columns is used for
Make the storage array of memory.Along word-line direction arrangement each active area with two adjacent gate trench 101
Intersection.The compound grid in each gate trench is filled in as the corresponding wordline of corresponding cell row, two gate trench 101
Between active area on conducting wire 110 as the bit line in corresponding cell columns.
Fig. 3 A to 3I is please referred to, an embodiment of the present invention provides a kind of semiconductor devices, preferably using above-mentioned
It is prepared by the preparation method of the semiconductor devices of the utility model.The semiconductor devices includes: half with gate trench 101
Conductor substrate 100, metal gates 104, polysilicon gate 105, the first conductive contact structure 109, conducting wire 111, interlayer dielectric layer
112 and second conductive contact structure 113.
Wherein, 1002 He of the first source/drain region is respectively formed in the semiconductor substrate 100 of 101 two sides of gate trench
Second source/drain region 1103, the metal gates 104 are filled in the gate trench 101, and the height of the metal gates 104
Degree is less than the depth of the gate trench 101；The polysilicon gate 105 is filled in the gate trench 101, and is stacked in
On the metal gates 104.
In the present embodiment, the top surface of the polysilicon gate 105 is lower than the semiconductor on 101 side wall of gate trench
The top surface of substrate 100, the semiconductor devices further include gate isolation 106, and the gate isolation 106 is filled in institute
The gate trench 101 is stated in gate trench 101 and filled up, the metal gates 104 and the polysilicon gate 105 are buried
Inside.
In the present embodiment, the semiconductor devices further includes gate dielectric layer 102 and metal barrier 103, and the grid are situated between
Matter layer 102 is formed on the side wall and bottom wall of the gate trench 101, and the metal barrier 103 is formed in the gate medium
Between layer 102 and the metal gates 104 and it is enclosed on the bottom wall and side wall of the metal gates 104, the metal barrier
Layer 103 exposes the sidewall surfaces of the gate dielectric layer 102 of 104 top of metal gates, the polysilicon gate 105
Side wall is directly contacted with the gate dielectric layer 102 by the sidewall surfaces that the metal barrier 103 exposes.The gate dielectric layer
102 material is preferably high K dielectric (dielectric constant K is greater than 7), and the material of high K dielectric is, for example, Ta2O5、TiO2、TiN、Al2O3、
Pr2O3、La2O3、LaAlO3、HfO2、ZrO2Or metal oxide of other components etc., with the metal gates 104 that will be formed
It is compatible, be conducive to the mobility for improving carrier, improve device performance.Metal barrier 103 is intended to protect gate dielectric layer 102,
It avoids introducing metal impurities into gate dielectric layer 102, while improving the adhesion strength between gate dielectric layer 102 and metal gates 104.
Metal barrier 103 can be single layer structure, be also possible to the metal layers such as laminated construction, including Ti or Ta, TiAlN, TaCN,
The metal nitride layers such as TaSiN, TiN or TaN or at least one of metal and metal nitride.In the present embodiment, golden
Belong to the metal electrode that grid 104 may include one or more workfunction layers and be surrounded by the workfunction layers
Layer, wherein the selection of workfunction layers is determined by the conduction type for the BCAT transistor that need to be formed, when the BCAT that need to be formed is brilliant
When body pipe is P-type transistor, workfunction layers in metal gates 104 are p-type workfunction metal material, the p-type function
Letter metal material may include TiN, TaN, Ru, Mo, Al, WN, ZrSi2、MoSi2、TaSi2、NiSi2, W other suitable p-type function
Letter material or their combination, the work function gold when the BCAT transistor that need to be formed is N-type transistor, in metal gates 104
Belong to layer is N-shaped workfunction metal material, the N-shaped workfunction metal material include Ti, Ag, TaAl, TaAlC, TiAlN,
TaC, TaCN, TaSiN, Mn, Zr, other suitable N-shaped work function materials or their combination；The material of metal electrode layer can wrap
Include Al, W, Cu and/or other suitable metal materials.
Preferably, it is sequentially formed with metal adhesion layers from bottom to top between metal gates 104 and polysilicon gate 105
1141, metal barrier 1142 and metal silicide layer 1143.Wherein, metal gates can be enhanced in metal adhesion layers 1141
Adhesion strength between 104 and polysilicon gate 105 prevents finally formed compound grid fracture, belongs to the material of adhesion layer 1141
It can be the metals such as W, Ti or Ta；Metal barrier 1142 can prevent the metal in metal gates 104 to be diffused into polysilicon gate
In pole 105, and the performance of metal gates 104 and polysilicon gate 105 is influenced, the material of metal barrier 1142 can be
The metal nitrides such as TiAlN, TaCN, TaSiN, TiN or TaN；Metal silicide layer 1143 can reduce metal gates 104 and more
Contact resistance between polysilicon gate 105, to reduce the resistance value of the compound grid formed, metal silicide layer 1143 can be packet
Metal silicide containing at least one of the metallic elements such as Ti, W, Co, Ni, Zr, Mo, Ta.
In the present embodiment, first conductive contact structure 109 is formed on first source/drain region 1002, and described
The top surface of first conductive contact structure 109 is flushed with the top surface of the gate isolation 106, the first conductive contact knot
Gap is formed between structure 109 and the opposite side wall of the gate trench 101；Conducting wire 111 is formed in first conductive contact
In structure 109, and conducting wire 111 and the wide setting of first conductive contact structure 109；Interlayer dielectric layer 112 is covered in described
On gate isolation 106, the first source/drain region 1002, the second source/drain region 1003, conducting wire 111 and the first conductive contact structure 109,
The interlayer dielectric layer 112 fills up the gap of 109 side wall of the first conductive contact structure, and by the conducting wire 111 and described
In first conductive contact structure 109 is buried in.Second conductive contact structure 113 is formed in the interlayer dielectric layer 112, and institute
The bottom surface for stating the second conductive contact structure 113 is contacted with the top surface of second source/drain region 1003.
In one embodiment of the utility model, multiple active areas are formed in the semiconductor substrate 100 and (are not schemed
Show), it is arranged side by side in each active area there are two the gate trench 101, having between two gate trench 101
It is formed with the first source/drain region 1002 in source region, is respectively formed in the active area of the opposite side of two gate trench 101
Second source/drain region 1003, first conductive contact structure 109 are formed in 1002 top of the first source/drain region and bottom surface
It is contacted with the top surface of first source/drain region 1002, second conductive contact structure 113 is formed in second source/drain
Above area 1003 and bottom surface is contacted with the top surface of second source/drain region 1003, thus forms two in an active area
A BCAT improves device integration.When the semiconductor devices is memory, the multiple active area presses cell row, unit
Array arrangement is arranged into, the compound grid in each cell row is linked together, as a wordline of the memory, each unit
Conducting wire 111 on column is linked together, a bit line as the memory.
Referring to FIG. 4, first conductive contact structure 109 is composite junction in the other embodiments of the utility model
Structure, including metal layer 1091 and the polysilicon layer 1092 being stacked on above the metal layer 1091, the material of the conducting wire 111
Including metal.
In an embodiment of the utility model, successively have from bottom to top between metal layer 1091 and the first source-drain area 1002
Metal silicide layer (not shown), metal barrier (not shown) and metal adhesion layers (not shown), wherein metal adhesion layers
The adhesion strength between metal layer 1091 and the first source-drain area 1002 can be enhanced, prevent the first conductive contact structure 109 and first
1002 poor contact of source-drain area, the material of metal adhesion layers can be the metals such as W, Ti or Ta；Metal barrier can prevent gold
The metal belonged in layer is diffused into the first source-drain area 1002, and influences the performance of the first source-drain area 1002, the material of metal barrier
Material can be the metal nitrides such as TiAlN, TaCN, TaSiN, TiN or TaN；Metal silicide layer can reduce metal layer and
Contact resistance between one source-drain area 1002, metal silicide layer can be comprising the metals such as Ti, W, Co, Ni, Zr, Mo, Ta member
The metal silicide of at least one of element.
In another embodiment of the utility model, successively shape from bottom to top between metal layer 1091 and polysilicon layer 1092
At having between metal adhesion layers 1093, metal barrier 1094, metal silicide layer 1095, polysilicon layer 1092 and bit line 111
It is sequentially formed with metal silicide layer 1096, metal barrier 1097, metal adhesion layers 1098 from bottom to top, wherein metal is viscous
The adhesion strength between metal layer 1091 and polysilicon layer 1092 can be enhanced in attached layer 1093, prevents metal layer 1091 and polysilicon layer
The case where 1092 poor contacts are even cracked, metal adhesion layers 1098 can be enhanced between conducting wire 111 and polysilicon layer 1092
Adhesion strength, the case where preventing bit line 111 and 1092 poor contact of polysilicon layer or even crack, metal adhesion layers 1093,1098
Material can be the metals such as W, Ti or Ta；Metal barrier 1094 can prevent the metal in metal layer 1091 to be diffused into polysilicon
In layer 1092, metal barrier 1097 can prevent the metal in conducting wire 111 to be diffused into polysilicon layer 1092, metal barrier
1094,1097 material can be the metal nitrides such as TiAlN, TaCN, TaSiN, TiN or TaN；Metal silicide layer 1095 can
To reduce the contact resistance between metal layer 1091 and polysilicon layer 1092, and further the metal in barrier metal layer 1091 to
It is spread in polysilicon layer 1092, metal silicide layer 1096 can reduce the electricity of the contact between conducting wire 111 and polysilicon layer 1092
It hinders and further the metal in conducting wire 111 is stopped to spread into polycrystal layer 1092, metal silicide layer 1095,1096 can be packet
Metal silicide containing at least one of the metallic elements such as Ti, W, Co, Ni, Zr, Mo, Ta.
In addition, the utility model also provides a kind of electronic equipment, the semiconductor devices including the utility model.This is practical new
The electronic equipment of type can be the various mobile terminals such as mobile phone, wearable device, laptop, tablet computer, described to wear
Wearing equipment includes that the wrists such as intelligent glasses, helmet and wrist-watch, bracelet wear equipment.
Foregoing description is only the description to the utility model preferred embodiment, not to any limit of the scope of the utility model
Fixed, any change, the modification that the those of ordinary skill in the utility model field does according to the disclosure above content belong to right and want
Seek the protection scope of book.
Claims (7)
1. a kind of semiconductor devices characterized by comprising
Semiconductor substrate with gate trench；
Metal gates are filled in the gate trench, and the height of the metal gates is less than the depth of the gate trench；
And
Polysilicon gate is filled in the gate trench, and the polysilicon gate is stacked on the metal gates.
2. semiconductor devices as described in claim 1, which is characterized in that the top surface of the polysilicon gate is lower than the grid
The top surface of semiconductor substrate on the trenched side-wall of pole, the semiconductor devices further include: gate isolation is filled in described
In gate trench, the gate isolation fills up the gate trench, and the metal gates and the polysilicon gate are covered
In being embedded in.
3. semiconductor devices as described in claim 1, which is characterized in that it further include gate dielectric layer and metal barrier, it is described
Gate dielectric layer is formed on the side wall and bottom wall of the gate trench, and the metal barrier is formed in the gate dielectric layer and institute
It states between metal gates, be enclosed on the bottom wall and side wall of the metal gates and expose and is above the metal gates described
Gate dielectric layer surface, the side that the side wall of the polysilicon gate is directly exposed with the gate dielectric layer by the metal barrier
Wall surface contact.
4. semiconductor devices as claimed in claim 2, which is characterized in that further include:
First conductive contact structure is formed in the semiconductor substrate of the gate trench side；
Conducting wire is formed on first conductive contact structure；
Interlayer dielectric layer is covered in the gate isolation and the semiconductor substrate, and the interlayer dielectric layer is led described
In line and first conductive contact structure are buried in；And
Second conductive contact structure is formed in the interlayer dielectric layer, the bottom surface of second conductive contact structure and institute
State the surface contact of the semiconductor substrate of the gate trench other side.
5. semiconductor devices as claimed in claim 4, which is characterized in that being formed at least one in the semiconductor substrate has
Source region is arranged side by side in the active area there are two the gate trench, shape in the active area between two gate trench
At there is the first source/drain region, the second source/drain region, institute are respectively formed in the active area of the opposite side of two gate trench
State the top surface that the first conductive contact structure is formed in the first source/drain region top and bottom surface and first source/drain region
Contact, second conductive contact structure is formed in above second source/drain region and bottom surface and second source/drain region
Top surface contact.
6. semiconductor devices as claimed in claim 4, which is characterized in that first conductive contact structure and the grid ditch
Gap is formed between the opposite side wall of slot, the interlayer dielectric layer fills up the gap.
7. the semiconductor devices as described in any one of claim 4 to 6, which is characterized in that first conductive contact structure
For composite construction, including metal layer and it is stacked on the polysilicon layer of the metal layer, the material of the conducting wire includes gold
Belong to.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821504075.3U CN208655649U (en) | 2018-09-13 | 2018-09-13 | Semiconductor devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821504075.3U CN208655649U (en) | 2018-09-13 | 2018-09-13 | Semiconductor devices |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN208655649U true CN208655649U (en) | 2019-03-26 |
Family
ID=65793089
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201821504075.3U Active CN208655649U (en) | 2018-09-13 | 2018-09-13 | Semiconductor devices |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN208655649U (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110690293A (en) * | 2019-10-12 | 2020-01-14 | 武汉新芯集成电路制造有限公司 | Flash memory device and method of manufacturing the same |
| CN113629144A (en) * | 2020-05-08 | 2021-11-09 | 长鑫存储技术有限公司 | Semiconductor device and method for manufacturing the same |
| CN115188767A (en) * | 2021-04-02 | 2022-10-14 | 长鑫存储技术有限公司 | AND gate structure and manufacturing method thereof |
| WO2023216284A1 (en) * | 2022-05-10 | 2023-11-16 | 长鑫存储技术有限公司 | Semiconductor structure and preparation method therefor |
-
2018
- 2018-09-13 CN CN201821504075.3U patent/CN208655649U/en active Active
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110690293A (en) * | 2019-10-12 | 2020-01-14 | 武汉新芯集成电路制造有限公司 | Flash memory device and method of manufacturing the same |
| CN113629144A (en) * | 2020-05-08 | 2021-11-09 | 长鑫存储技术有限公司 | Semiconductor device and method for manufacturing the same |
| CN113629144B (en) * | 2020-05-08 | 2023-07-07 | 长鑫存储技术有限公司 | Semiconductor device and method for manufacturing the same |
| CN115188767A (en) * | 2021-04-02 | 2022-10-14 | 长鑫存储技术有限公司 | AND gate structure and manufacturing method thereof |
| WO2023216284A1 (en) * | 2022-05-10 | 2023-11-16 | 长鑫存储技术有限公司 | Semiconductor structure and preparation method therefor |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN208655649U (en) | Semiconductor devices | |
| US10515907B2 (en) | Three-dimensional memory device containing hydrogen diffusion blocking structures and method of making the same | |
| US8633529B2 (en) | Vertical transistors | |
| CN101471379B (en) | Semiconductor device and process for manufacturing same | |
| US9059213B2 (en) | Embedded DRAM for extremely thin semiconductor-on-insulator | |
| US10515897B2 (en) | Three-dimensional memory device containing hydrogen diffusion blocking structures and method of making the same | |
| CN110896077A (en) | Semiconductor device and method for manufacturing the same | |
| CN110098175A (en) | Semiconductor devices and its manufacturing method | |
| CN108133934A (en) | Semiconductor device | |
| CN103681678B (en) | Semiconductor device with buried bit line and method of fabricating the same | |
| CN103050407B (en) | Embedded Transistor | |
| CN105140222B (en) | Integrated circuit and its manufacturing method | |
| KR20220033587A (en) | Semiconductor devices | |
| CN108878529B (en) | Semiconductor device and method for manufacturing the same | |
| US11758716B2 (en) | Electronic devices including vertical memory cells and related methods | |
| KR20040018806A (en) | Method of forming semiconductor device having metal silicide layer | |
| CN110896076A (en) | Semiconductor device and method for manufacturing the same | |
| CN111261632A (en) | Semiconductor grid structure and preparation method thereof | |
| CN208655648U (en) | Semiconductor devices | |
| US11631675B2 (en) | Semiconductor memory structure and method for forming the same | |
| US20240096897A1 (en) | Transistor isolation regions and methods of forming the same | |
| US9893145B1 (en) | On chip MIM capacitor | |
| CN209401624U (en) | Semiconducting gate structure | |
| WO2023161760A1 (en) | Stacked field-effect transistors | |
| US20060286756A1 (en) | Semiconductor process and method for reducing parasitic capacitance |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |