CN212570997U - Semiconductor memory device with a plurality of memory cells - Google Patents

Abstract

The utility model discloses a semiconductor memory device, including a semiconductor substrate, word line structure, the position is in the semiconductor substrate, the bit line structure, the position is in on the word line structure and stride word line structure, spacer structure are located directly over the word line structure and in between the bit line structure, storage node contact structure are located the bit line structure with in the space that the spacer structure was defined out and with the semiconductor substrate is connected, storage node contact structure salient in the bit line structure with position on the top surface of spacer structure is contact pad and contact pad isolation structure, is located spacer structure top and bit line structure top and in between the contact pad, wherein the contact pad isolation structure contains the skin of silicon nitride material and the inlayer of silicon oxide material.

Description

Semiconductor memory device with a plurality of memory cells

Technical Field

Embodiments of the present disclosure relate to a semiconductor memory device, and more particularly, to a semiconductor memory device having a special isolation structure between storage node contact pads and a method of fabricating the same.

Background

Semiconductor devices have been widely used in the electronics industry due to their small size, versatility, and/or low manufacturing cost characteristics. The semiconductor device may be classified into a semiconductor memory device storing logic data, a semiconductor logic device processing an operation of the logic data, and a hybrid device having functions of both the memory device and the logic device.

The semiconductor devices may include vertically stacked layer structure patterns and contact plugs or interconnection structures electrically connecting the stacked patterns to each other. As semiconductor devices continue to shrink and increase integration, the spacing between such patterns and/or the spacing between patterns and contact plugs also continues to decrease. As such, parasitic capacitance between patterns and/or between a pattern and a contact plug increases, and contact resistance between a pattern and an interconnect structure also increases, resulting in deterioration of performance of a semiconductor device, such as a reduction in operating speed.

SUMMERY OF THE UTILITY MODEL

In view of the above-mentioned conventional problems encountered by semiconductor devices, the present invention provides a novel semiconductor memory device, which is characterized in that a special isolation structure is provided between the storage node pads, which can reduce the k value of the whole device and the parasitic capacitance thereof.

One aspect of the present invention is to provide a semiconductor memory device, which includes a semiconductor substrate, a word line structure located in the semiconductor substrate and extending in a first direction, a bit line structure located on the word line structure and extending across the word line structure and the spacer structure in a second direction, a storage node contact structure located directly above the word line structure and between the bit line structures and located in a space defined by the bit line structure and the spacer structure and connected to the semiconductor substrate, the portions of the storage node contact structures protruding above the top surfaces of the bit line structures and the spacer structures are contact pads, and contact pad isolation structures located above the spacer structures and above the bit line structures and between the contact pads, the contact pad isolation structure comprises an outer layer made of silicon nitride and an inner layer made of silicon oxide.

Another aspect of the present invention is to provide a semiconductor memory device, which includes a semiconductor substrate, a word line structure located in the semiconductor substrate and extending in a first direction, a bit line structure located on the word line structure and extending across the word line structure and the spacer structure in a second direction, a storage node contact structure located directly above the word line structure and between the bit line structures and located in a space defined by the bit line structure and the spacer structure and connected to the semiconductor substrate, the parts of the storage node contact structures protruding out of the top surfaces of the bit line structures and the spacer structures are contact pads and contact pad isolation structures, the contact pad isolation structures are positioned above the spacer structures and the bit line structures and between the contact pads, and the contact pad isolation structures are internally provided with holes.

These and other objects of the present invention will become more apparent to those skilled in the art after a reading of the following detailed description of the preferred embodiment illustrated in the various figures and drawings.

Drawings

The accompanying drawings are included to provide a further understanding of embodiments of the invention, and are incorporated in and constitute a part of this specification. The drawings depict some embodiments of the invention and, together with the description, serve to explain its principles.

In these figures:

FIGS. 1, 3, 6, and 10 are plan views illustrating a semiconductor memory device according to various embodiments of the present disclosure;

FIG. 1A, FIG. 2A, FIG. 3A, FIG. 4A, FIG. 5A, FIG. 6A, FIG. 7A, FIG. 8A, FIG. 9A and FIG. 10A are cross-sectional views taken along line A-A' in FIG. 1 during a fabrication process; and

fig. 1B, 2B, 3B, 4B, 5B, 6B, 7B, 8B, 9B and 10B are cross-sectional views taken along a line B-B' in fig. 1 during a manufacturing process.

It should be noted that all the figures in this specification are schematic in nature, and that for the sake of clarity and convenience, various features may be shown exaggerated or reduced in size or in proportion, where generally the same reference signs are used to indicate corresponding or similar features in modified or different embodiments.

Wherein the reference numerals are as follows:

1a first doped region

1b second doped region

100 semiconductor substrate

102 spacer wall

104 spacer structure

106 storage node contact structure

106a contact pad

108 device isolation layer

110 gate insulating layer

112 gate hard mask pattern

114 insulating interlayer

116 recessed region

118 polysilicon layer

120 silicide layer

122 metal layer

124 hard mask layer

126 bitline contact spacer

130 polysilicon layer

132 silicide layer

134 barrier layer

136 metal layer

138 silicon nitride liner (outer layer)

140 silicon oxide layer (inner layer)

142 contact pad isolation structure

144 silicon nitride capping layer

146 silicon nitride liner

148 silicon oxide layer

150 (first) silicon nitride layer

152 contact pad isolation structure

154 gap

154a hollow

156 (second) silicon nitride layer

158 contact pad isolation structure

ACT active region

BL bit line structure

D1 first direction

D2 second direction

Third direction D3

WL word line structure

Detailed Description

Reference will now be made in detail to the exemplary embodiments of the present invention, which will reference features described in order for a reader to understand and achieve a technical effect. It will be understood by the reader that the description herein is by way of illustration only and is not intended to be limiting. The various embodiments of the disclosure and the various features of the embodiments that are not mutually inconsistent can be combined or rearranged in various ways. Modifications, equivalents, or improvements to the disclosure may be apparent to those skilled in the art without departing from the spirit and scope of the disclosure, and are intended to be included within the scope of the disclosure.

It should be readily understood by the reader that the meaning of "on …", "above …" and "above …" in this case should be read in a broad manner such that "on …" not only means "directly on" something "but also includes the meaning of" on "something with intervening features or layers therebetween, and" on … "or" above … "not only means" on "something" or "above" but also includes the meaning of "on" or "above" something with no intervening features or layers therebetween (i.e., directly on something).

Moreover, spatially relative terms such as "below …," "below …," "below," "above …," "above," and the like may be used herein for ease of description to describe the relationship of one element or feature to another element or feature, as illustrated in the figures.

As used herein, the term "substrate" refers to a material to which a subsequent material is added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. In addition, the substrate may comprise a wide range of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, and the like.

As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. A layer may extend over the entirety of the underlying or overlying structure or may have an extent that is less than the extent of the underlying or overlying structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located between any horizontal pair of surfaces at the top and bottom surfaces or between the top and bottom surfaces of the continuous structure. The layers may extend horizontally, vertically and/or along inclined surfaces. The substrate may be a layer, which may include one or more layers, and/or may have one or more layers thereon, above, and/or below. The layer may comprise a plurality of layers. For example, the interconnect layer may include one or more conductors and contact layers (where contacts, interconnect lines, and/or vias are formed) and one or more dielectric layers.

In the drawings of this specification, fig. 1, fig. 3, fig. 6, and fig. 10 are plan views illustrating a semiconductor memory device according to various embodiments of the present disclosure, fig. 1A, fig. 2A, fig. 3A, fig. 4A, fig. 5A, fig. 6A, fig. 7A, fig. 8A, fig. 9A, and fig. 10A are cross-sectional views taken along a line a-a 'in fig. 1 in a manufacturing process, and fig. 1B, fig. 2B, fig. 3B, fig. 4B, fig. 5B, fig. 6B, fig. 7B, fig. 8B, fig. 9B, and fig. 10B are cross-sectional views taken along a line B-B' in fig. 1 in the manufacturing process.

Please refer to fig. 1 first. The semiconductor memory device of the present invention is fabricated on a semiconductor substrate 100, such as a silicon substrate, a germanium substrate and/or a silicon germanium substrate. The semiconductor substrate 100 has a memory cell region, which is a memory cell for arranging a semiconductor memory device, or is referred to as a storage node, and a peripheral region around the memory cell region. The plurality of storage nodes are arranged in a matrix pattern in the storage unit area and can store charges to generate a distinctive storage state. The peripheral area is used for setting peripheral circuits of the memory device, such as column decoders, row decoders, sense amplifiers, or I/O control modules. Since the features of the present invention are independent of the peripheral region, only the components and features in the memory cell region are shown in the figure. Active regions ACT are defined in the memory cell region of the semiconductor substrate 100, and each active region ACT is separated by a surrounding device isolation layer. In the process, the device isolation layer may be formed by performing a photolithography process on the semiconductor substrate 100 to form respective separated active regions ACT, and filling the recess between the active regions ACT with an isolation material, such as silicon oxide. In an example, the active area ACT has a stripe shape in a plan view and has a long axis extending to the third direction D3. The plurality of active regions ACT are uniformly arranged in a staggered manner on a plane.

Refer back to fig. 1. The semiconductor substrate 100 is provided with a plurality of word line structures WL parallel to each other at a predetermined interval and extending through the memory cell regions in a first direction D1. The semiconductor substrate 100 further has a plurality of bit line structures BL disposed parallel to each other at a predetermined interval and extending through the memory cell region in a second direction D2, wherein the second direction D2 is preferably orthogonal to the first direction D1, an angle between the third direction D3 and the first direction D1 is preferably between 45 degrees and 90 degrees, and an angle between the third direction D3 and the second direction D2 is preferably between 0 degrees and 45 degrees. The word line structure WL is usually buried in the semiconductor substrate 100 and serves as an access transistor for controlling switching of a gate and access of charges, and the bit line structure BL is usually provided on the semiconductor substrate 100 so as to straddle the word line structure WL and connected to the active region ACT for writing and reading. Spacers 102 are formed around the bit line structures BL to isolate the bit line structures BL from surrounding devices.

Refer back to fig. 1. A plurality of spacer structures 104 are disposed between the bit line structures BL and the bit line structures BL on the semiconductor substrate 100, and are substantially located right above the word line structures WL and spaced apart from each other. In the memory cell region, the spacer structure 104 and the bit line structure BL may together define a storage node region on the semiconductor substrate 100, on which a storage node contact structure 106 is disposed. In practice, a charge storage element such as a capacitor is disposed on the storage node contact structure 106, but these elements are not essential and will not be shown in the following figures for simplicity.

After the plane layout of the semiconductor memory device of the present invention is described, the relative positions and connection relationships of the components of the semiconductor memory device in the vertical direction in different embodiments of the present invention will be described with reference to the following sectional views. Referring to fig. 1A and 1B, cross-sectional structures of a memory cell region including a word line structure WL, a bit line structure BL and a storage node contact structure 106 are illustrated, wherein fig. 1A is a cut through the spacer structure 104 and the storage node contact structure 106 along a second direction D2 according to a sectional line a-a 'in fig. 1, and fig. 1B is a cut through the bit line structure BL and the storage node contact structure 106 along a first direction D1 according to a sectional line B-B' in fig. 1.

As shown in fig. 1A and 1B. First, a device isolation layer 108 defining an active region ACT is formed in the semiconductor substrate 100. The semiconductor substrate 100 may include a silicon substrate, a germanium substrate, and/or a silicon germanium substrate. The device isolation layer 108 may be formed by performing a photolithography process on the semiconductor substrate 100 to form respective separated active regions ACT, and filling the recesses between the active regions ACT with an isolation material, such as silicon oxide. In an example, the active area ACT has a stripe shape in a plan view and has a long axis extending to the third direction D3. The plurality of active regions ACT are uniformly arranged in a staggered manner on a plane.

A plurality of word line structures WL are formed in the semiconductor substrate 100, extending in a first direction D1. In an example, the active region ACT and the device isolation layer 108 may be patterned via a photolithography process to form a gate recess region extending in the first direction D1, and the gate insulating layer 110 is formed in the gate recess region. Thereafter, word line structures WL located on the gate insulating layers 110 may be respectively formed in the corresponding gate recess regions. The material of the word line structure WL may be a metal, such as tungsten, aluminum, titanium, and/or tantalum. The bottom surface of the gate recess region may be set higher than the bottom surface of the device isolation layer 108. The top surface of the word line structure WL may be set lower than the top surface of the device isolation layer 108. After the word line structure WL is formed, a gate hard mask pattern 112, such as a silicon nitride layer, is then formed in the gate recess region remaining on the word line structure WL.

Reference is again made to fig. 1A and 1B. After the gate hard mask pattern 112 is formed, first and second doping regions 1A and 1b, which may be formed through an ion implantation process and may include dopants of a conductivity type opposite to that of the active region ACT, may be formed in the active region ACT at both sides of the word line structure WL, respectively, wherein the cross-sectional portion of fig. 1A is cut through only the second doping region 1b of the active region ACT. The bottom surfaces of the first and second impurity-doped regions 1a and 1b may be positioned at a predetermined depth downward from the top surface of the active region ACT. The first doped region 1a is located in the middle of the active region ACT, which is then electrically connected to the bit line structure BL. The second doping regions 1b are located at both ends of the active region ACT, which are then electrically connected to the storage node contact structures 106. In addition, an insulating interlayer 114 may be formed on the surface of the semiconductor substrate 100 to isolate the active region ACT from the components above. The insulating interlayer 114 may be formed of a single insulating layer or a plurality of insulating layers, such as a silicon nitride layer, and/or a silicon oxynitride layer, etc.

According to an example, the semiconductor substrate 100 and the insulating interlayer 114 may be patterned via a photolithography process to form a recess region 116 exposing the first doping region 1 a. In some embodiments, the recessed region 116 may be formed by an anisotropic etching process. In this case, portions of device isolation layer 108 adjacent to first doped region 1a may be etched together. The bottom surface of the recess region 116 may be higher than the bottom surface of the first doped region 1a (as indicated by the dotted line), and a portion of the device isolation layer 108 may be exposed from the recess region 116.

Reference is again made to fig. 1A and 1B. The semiconductor substrate 100 has a bit line structure BL extending in the second direction D2. The bit line structure BL may sequentially form a polysilicon layer 118, a silicide layer 120, a metal layer 122, and a hard mask layer 124 on the semiconductor substrate 100 from bottom to top. In an example, the polysilicon layer 118 may be doped polysilicon, the metal layer 122 may be a tungsten layer, an aluminum layer, a titanium layer, or a tantalum layer, etc., and the hard mask layer 124 may be a silicon nitride layer. A portion of polysilicon layer 118 is formed in recess region 116 as a bit line contact directly contacting first impurity region 1 a. In addition, the minimum width of the recess region 116 may be greater than the width of each bit line structure BL. The sidewall of the bit line structure BL is formed with an insulating structure to prevent the bit line structure BL from being electrically connected to the surrounding components, which may include a bit line contact spacer 126 formed in the recess 116 and a spacer 102 covering the sidewall of the bit line structure BL. The material of the bit line contact spacer 126 may include silicon oxide, silicon nitride, silicon oxynitride, or a composite layer thereof. The material of the spacer 102 may be silicon oxide, silicon nitride, or a composite structure thereof.

In the illustrated example, the spacer structure 104 is formed directly above the word line structure WL and between the bit line structure BL and the bit line structure BL, such that the spacer structure 104 and the bit line structure BL are spaced apart from each other on the semiconductor substrate 100 and define a plurality of spaces, each corresponding to a storage node region, each located above the second doped region 1b of the active region ACT, and the spaces are predetermined to form the storage node contact structures 106. The spacer structure 104 may be formed using silicon nitride. In an example, the storage node contact structure 106 may include, from bottom to top, a polysilicon layer 130, a silicide layer 132, a barrier layer 134, and a metal layer 136. The polysilicon layer 130 of the storage node contact structure 106 may be doped polysilicon, which directly contacts the second doped region 1b in the active region ACT through the insulating interlayer 114. In an example, the bottom surface of the polysilicon layer 130 of the storage node contact structure 106 may be lower than the top surface of the semiconductor substrate 100 and higher than the bottom surface of the polysilicon layer 118 of the bit line structure BL. Silicide layer 132 may include titanium silicide, cobalt silicide, nickel silicide, tungsten silicide, platinum silicide, molybdenum silicide, and/or the like. Metal layer 136 may be a metal such as tungsten, aluminum, titanium, or tantalum. Barrier layer 134 may comprise a nitride of a metal material such as tungsten, aluminum, titanium, or tantalum. In the illustrated example, the portion of the storage node contact structure 106 protruding above the top surfaces of the bit line structure BL and the spacer structure 104 is generally referred to as a storage node contact pad, which is hereinafter referred to as a contact pad 106 a. In practice, a charge storage element such as a capacitor is disposed above the contact pad 106a of the storage node contact structure 106, but this element is not essential, and for simplicity of illustration, it will not be shown in the following figures. Only the features up to the contact pad 106a will be described and illustrated.

Please refer to fig. 2A and fig. 2B. After the storage node contact structure 106 is formed, a silicon nitride liner 138 is formed on the contact pad 106a, the spacer structure 104 and the bit line structure BL. The silicon nitride liner 138 may be uniformly and conformally formed and covered over the entire substrate surface using Atomic Layer Deposition (ALD) or the like. Next, a silicon oxide layer 140, such as Tetraethoxysilane (TEOS), is deposited over the silicon nitride liner 138. The silicon oxide layer 140 may be formed by a Chemical Vapor Deposition (CVD) process, etc., and fills the space between the contact pads 106a and covers the entire substrate surface. In addition, a Chemical Mechanical Polishing (CMP) process may be performed to planarize the surface of the silicon oxide layer 140 to facilitate subsequent processes.

Please refer to fig. 3A and fig. 3B. After the formation of the silicon nitride liner 138 and the silicon oxide layer 140, an etch-back process is performed to remove the excess silicon nitride liner 138 and the silicon oxide layer 140 on the top surface of the contact pad 106a to expose the contact pad 106 a. Thus, the contact pad isolation structure 142 between the contact pads 106a can be formed. In the present invention, the contact pad isolation structure 142 is formed by an outer layer (i.e., 138) of silicon nitride and an inner layer (i.e., 140) of silicon oxide, wherein the outer layer 138 is located on the top surface of the spacer structure 104 and the sidewall of the contact pad 106a, and the top surfaces of the outer layer 138, the inner layer 140 and the contact pad 106a are flush. Further, in the illustrated example, the outer layer 138 of the contact pad isolation structure 142 is disposed on the sidewall around the contact pad in a ring shape, as shown in the plan view of fig. 3. The present invention provides a contact pad isolation structure 142 with two layers of different materials and surrounding the contact pad 106a, which can reduce the total k value of the material between the contact pads 106a, thereby reducing the parasitic capacitance and improving the device performance. Finally, a silicon nitride capping layer 144 may be formed over the contact pad 106a and the contact pad isolation structure 142, which serves as a passivation layer to protect the underlying contact pad 106a structure during processing.

The following examples will illustrate another variation of the contact pad isolation structure of the present invention. Please refer to fig. 4A and fig. 4B. Following the steps of fig. 1A and 1B after the formation of the storage node contact structure 106, a silicon nitride liner layer 146 and a silicon oxide layer 148 may be sequentially formed on the surfaces of the contact pad 106a, the spacer structure 104 and the bit line structure BL. The silicon nitride liner 146 and the silicon oxide layer 148 may be uniformly and conformally formed over the entire substrate surface using Atomic Layer Deposition (ALD) or the like. This embodiment is different from the previous embodiments in that the silicon oxide layer 148 is formed in the space between the contact pads 106a in a conformal manner rather than in a filled manner, so that there is a space between the contact pads 106 a.

Please refer to fig. 5A and 5B. After the formation of the silicon nitride liner 146 and the silicon oxide layer 148, an etch-back process is then performed to remove a portion of the silicon oxide layer 140, leaving only the portion of the silicon oxide layer 148 on the sidewall of the contact pad 106 a. It should be noted that in this embodiment, unlike the previous embodiment, the etch-back process does not remove any portion of the silicon nitride liner 146, and the silicon oxide layer 148 after the etch-back process is preferably lower than the top surface of the contact pad 106 a.

Please refer to fig. 6A and fig. 6B. After the etch back process, a silicon nitride layer 150 is formed to cover the silicon oxide layer 148 and the silicon nitride liner layer 146 and fill the space between the contact pads 106a, such that the silicon nitride liner layer 146, the silicon oxide layer 148 and the silicon nitride layer 150 together form a contact pad isolation structure 152 between the contact pads 106 a. In the present invention, the contact pad isolation structure 152 is composed of an outer layer (i.e., 146 and 150, both of which are made of the same material) of silicon nitride and an inner layer (i.e., 148) of silicon oxide, wherein the silicon oxide inner layer 148 of the contact pad isolation structure 152 is distributed around each contact pad 106a in a ring shape as shown in the plan view of fig. 6. Similarly, in the present invention, the pad isolation structures 152 of two different materials surrounding the pads 106a can reduce the total k value of the material between the pads 106a, thereby reducing the parasitic capacitance and improving the device performance.

The following examples will illustrate yet another variation of the contact pad isolation structure of the present invention. Please refer to fig. 7A and fig. 7B. Following the sequential steps of forming the conformal silicon nitride liner 146 and the silicon oxide layer 148 in fig. 4A and 4B, an etch-back process is performed to remove a portion of the silicon oxide layer 148, leaving only the portion of the silicon oxide layer 148 on the sidewall of the contact pad 106 a. It is noted that in this embodiment, unlike the embodiments of fig. 4A and 4B described above, the top surface of the silicon oxide layer 148 after the etch back is preferably flush with the top surface of the silicon nitride liner layer 146.

Please refer to fig. 8A and 8B. After the etch back process, a silicon nitride layer 150 is also formed to cover the silicon oxide layer 148 and the silicon nitride liner 146 and fill the space between the contact pads 106 a. Unlike the previous embodiments, in the present embodiment, an etch-back process is performed to remove the portion of the silicon nitride layer 150 covering the silicon oxide layer 148 and the silicon nitride liner layer 146, so that the silicon oxide layer 148 is exposed.

Please refer to fig. 9A and 9B. After the silicon oxide layer 148 is exposed, an etching process is performed to remove the exposed silicon oxide layer 148, thereby forming a gap 154 between the silicon nitride liner 146 and the silicon nitride layer 150. Next, please refer to fig. 10A and 10B. After the formation of void 154, another silicon nitride layer 156 is then formed overlying silicon nitride liner 146, silicon nitride layer 150, and void 154 such that void 154 becomes void 154 a. Thus, the silicon nitride liner 146, the (first) silicon nitride layer 150, the (second) silicon nitride layer 156, and the void 154a together form a contact pad isolation structure 158 between the contact pads 106 a. Finally, an etch back process may optionally be performed to remove the (second) silicon nitride layer 156 over the silicon nitride liner 146 and the (first) silicon nitride layer 150. In the present invention, the contact pad isolation structure 158 is formed of silicon nitride (i.e., 146,150,156, which are all the same material) and an inner cavity 154a, wherein the cavity 154a of the contact pad isolation structure 158 is distributed in a ring shape around each contact pad 106a as shown in the plan view of fig. 10. Similarly, in the present invention, the contact pad isolation structure 158 having the void 154a surrounding the contact pad 106a can reduce the total k value of the material between the contact pads 106a, thereby reducing the parasitic capacitance and improving the device performance.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (8)

1. A semiconductor memory device, comprising:

a semiconductor substrate;

a word line structure located in the semiconductor substrate and extending in a first direction;

a bit line structure located above the word line structure and extending across the word line structure in a second direction;

spacer structures directly above the wordline structures and between the bitline structures;

the storage node contact structure is positioned in a space defined by the bit line structure and the spacer structure and is connected with the semiconductor substrate, and the part of the storage node contact structure, which protrudes out of the top surfaces of the bit line structure and the spacer structure, is a contact pad; and

and a contact pad isolation structure located above the spacer structure and above the bit line structure and between the contact pads, wherein the contact pad isolation structure comprises an outer layer of silicon nitride material and an inner layer of silicon oxide material.

2. The semiconductor memory device of claim 1, wherein the outer layer is located on a top surface of the spacer structure and on sidewalls of the contact pad.

3. The semiconductor memory device of claim 1, wherein top surfaces of the outer layer, the inner layer, and the storage node contact structure are flush.

4. The semiconductor memory device of claim 1, further comprising a silicon nitride capping layer over the storage node contact structure and the contact pad isolation structure.

5. The semiconductor memory device of claim 1, wherein said inner layers are located inside said outer layers, each of said inner layers being arranged in a circular pattern around one of said contact pads.

6. A semiconductor memory device, comprising:

a semiconductor substrate;

a word line structure located in the semiconductor substrate and extending in a first direction;

a bit line structure located above the word line structure and extending across the word line structure in a second direction;

spacer structures directly above the wordline structures and between the bitline structures;

the storage node contact structure is positioned in a space defined by the bit line structure and the spacer structure and is connected with the semiconductor substrate, and the part of the storage node contact structure, which protrudes out of the top surfaces of the bit line structure and the spacer structure, is a contact pad; and

and the contact pad isolation structures are positioned above the spacer structures and the bit line structures and are arranged between the contact pads, wherein the contact pad isolation structures are internally provided with holes.

7. The semiconductor memory device of claim 6, wherein each of the voids is distributed in a ring pattern around one of the contact pads.

8. The semiconductor memory device according to claim 6, wherein a material of the contact pad isolation structure is silicon nitride.

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