CN210778577U

CN210778577U - Semiconductor device and contact pad layout, contact pad structure and mask plate combination thereof

Info

Publication number: CN210778577U
Application number: CN201921636137.0U
Authority: CN
Inventors: 童宇诚; 曾依蕾; 詹益旺
Original assignee: Fujian Jinhua Integrated Circuit Co Ltd
Current assignee: Fujian Jinhua Integrated Circuit Co Ltd
Priority date: 2019-09-27
Filing date: 2019-09-27
Publication date: 2020-06-16
Anticipated expiration: 2029-09-27

Abstract

The utility model provides a semiconductor device and a contact pad layout, a contact pad structure and a mask plate combination thereof, wherein a first edge layout area is arranged at one side of a main layout area where a main contact pad pattern is positioned, and the area of each first edge contact pad pattern in the first edge layout area is larger than that of each main contact pad pattern, thereby forming a main contact pad of a core area and a virtual contact pad at the boundary of the core area or the boundary area between the core area and a peripheral area based on the contact pad layout, enabling the top surface area of the virtual contact pad to be larger than that of the main contact pad, further increasing the size of an electrical structure connected on the virtual contact pad when the electrical structure is connected on the main contact pad and the virtual contact pad, improving the dense/sparse effect of circuit patterns between the core area and the peripheral area, and improving the consistency of the electrical structure connected on the main contact pad, meanwhile, the problem of abnormal electrical structure connected with the main contact pad at the boundary of the core area can be avoided.

Description

Semiconductor device and contact pad layout, contact pad structure and mask plate combination thereof

Technical Field

The utility model relates to the field of semiconductor technology, in particular to semiconductor device and contact pad territory, contact pad structure and mask plate combination thereof.

Background

Various techniques have been used to integrate more circuit patterns in a limited area of a semiconductor substrate or wafer. Due to the difference in the pitches of circuit patterns, an integrated circuit is generally divided into a device Dense region (Dense), a device sparse region (ISO), and a device isolated region, where the device Dense region is a region with a higher device density (i.e., devices are denser), the device sparse region is a region with a lower device density (i.e., devices are sparser), and the device isolated region is a region where the relatively sparse region and the Dense region are separately arranged. As the critical dimension of semiconductor devices is continuously reduced, the density of circuit patterns and/or the height of the devices is continuously increased, which is influenced by the resolution limit of an exposure tool (optical exposure tool) and the effect of density difference between a device dense region and a device sparse region (i.e., the dense/sparse effect of circuit patterns), and the difficulty in performing a photolithography process and/or an etching process is also increased (e.g., the process margin is reduced), thereby causing the performance of the manufactured semiconductor devices to be affected.

For example, in the case of a Dynamic Random Access Memory (DRAM) device, a large number of memory cells (memory cells) are grouped to form an array memory area, and a peripheral circuit area is present beside the array memory area, where the peripheral circuit area includes other transistor elements, contact structures, and the like, the array memory area is used as a device dense area of the DRAM for storing data, and the peripheral circuit area is used as a device sparse area of the DRAM for providing input and output signals and the like required by the array memory area. Each memory cell in the array memory region may be formed by a Metal Oxide Semiconductor (MOS) transistor and a capacitor (capacitor) structure connected in series. Wherein a capacitor is located within the array storage region, wherein the capacitor is stacked over a bit line and electrically coupled to a corresponding storage node contact of the capacitor, the storage node contact being electrically coupled to an active region therebelow. As semiconductor technology is continuously developed, critical dimensions of devices are continuously reduced, gaps between memory cells of a DRAM device become narrower, and when a storage node Contact is formed through a Self Aligned Contact (SAC) process, Contact holes formed inside an array storage region are not uniform due to the resolution limit of an exposure tool (optical exposure tool 1) and the effect of density difference between a device dense region and a device sparse region, Contact holes at the boundary of the device dense region are abnormal, which may cause a decrease in Contact area between a capacitor formed above and a Contact plug in the Contact hole and an increase in Contact resistance, possibly causing failure of some storage bits due to the problem of disconnection or short circuit of the Contact plug, and a problem of collapse of the capacitor at the boundary of the array storage region, which affect and limit the improvement of DRAM performance.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a semiconductor device and contact pad territory, contact pad structure and mask plate combination thereof to solve among the semiconductor devices such as current dynamic random access memory because of the intensive/sparse effect of optics proximity effect and circuit pattern and lead to the electrical structure that connects up on the contact plug in nuclear core region inside inconsistent and the electrical structure that connects up on the contact plug on nuclear core region boundary unusual problem.

In order to solve the above technical problem, the utility model provides a semiconductor device's contact pad territory, the contact pad territory includes:

the touch screen comprises a main layout area, a touch screen body and a touch screen, wherein a plurality of main contact pad patterns are arranged in the main layout area, the shapes and the sizes of the main contact pad patterns are similar, all the main contact pad patterns are arranged in a staggered manner in a chessboard shape, and a fourth interval is formed between the main contact pad patterns;

the first edge layout area is distributed on the outer side of one edge of the main layout area, at least one first edge contact pad pattern is arranged in the first edge layout area, the area of each first edge contact pad pattern is larger than that of each main contact pad pattern, and a first edge distance is formed between the first edge layout area and the main layout area;

wherein the first edge contact pad pattern is different from the main contact pad pattern, and the first edge pitch is different from the fourth pitch.

Based on same utility model conceive, the utility model discloses still provide an utilization the utility model discloses a semiconductor device's contact pad territory contact pad structure that forms, include:

the main contact pads are arranged in a staggered manner in a checkerboard manner, the shape and the size of each main contact pad are similar, and a fourth interval is formed between every two adjacent main contact pads;

at least one first edge contact pad distributed outside one edge of all the main contact pad arrangement regions, wherein the top surface area of each first edge contact pad is larger than that of each main contact pad, and a first edge distance is formed between the first edge contact pad next to the main contact pad and the main contact pad;

wherein a size of the first edge contact pad is different from a size of the main contact pad, and the first edge pitch is different from the fourth pitch.

Based on the same utility model discloses think, the utility model discloses still provide a semiconductor device, include:

a semiconductor substrate having a core region with a plurality of core elements formed therein;

the interlayer dielectric layer covers the semiconductor substrate;

the contact pad structure of a semiconductor device according to the present invention, formed in the interlayer dielectric layer;

a plurality of contact plugs formed in the interlevel dielectric layer, each contact plug disposed in alignment with a corresponding contact pad in the contact pad structure to electrically connect the corresponding contact pad with the active region of the core device.

Based on same utility model think, the utility model discloses still provide one kind and be used for the preparation the utility model discloses a semiconductor device's contact pad structure's mask plate combination, include:

the first mask plate is provided with a plurality of parallel first lines, a first interval area is arranged between every two adjacent first lines, the line width of at least one first line on the outermost side of the first mask plate is larger than that of other first lines, and the line width of at least one first interval area on the outermost side of the first mask plate is larger than that of other first interval areas;

the second mask plate is provided with a plurality of second stripes which are parallel to each other and are intersected with each first stripe, a second spacing area is arranged between every two adjacent second stripes, the line width of at least one second stripe on the outermost side of the second mask plate is larger than that of other second stripes, and the line width of at least one second spacing area on the outermost side of the second mask plate is larger than that of other second spacing areas;

when the first mask plate and the second mask plate are isotropic mask plates and the second mask plate and the first mask plate are aligned and overlapped, the overlapping area of the first lines and the second lines is an area for forming contact pads; when the first mask plate and the second mask plate are opposite mask plates and the second mask plate and the first mask plate are aligned and overlapped, the overlapping area of the first line and the second spacing area is an area for forming a contact pad.

Compared with the prior art, the technical scheme of the utility model following beneficial effect has:

by arranging the first edge layout area at one side of the main layout area where the main contact pad pattern is located, and the area of each first edge contact pad pattern in the first edge layout area is larger than the area of each main contact pad pattern, when the main contact pad of the core area is formed based on the contact pad layout, the first edge contact pad pattern can be used for forming a corresponding virtual contact pad at the boundary of the core area or in the boundary area between the core area and the peripheral area, and the area of the top surface of the virtual contact pad is larger than the area of the top surface of the main contact pad, so that the size of a subsequent electrical structure connected on the virtual contact pad can be increased, the dense/sparse effect of circuit patterns between the core area and the peripheral area can be improved when the electrical structures are connected on the main contact pad and the virtual contact pad, and the consistency of the electrical structures connected on the main contact pad in the core area can be improved, meanwhile, the problem of abnormal electrical structure connected with the main contact pad at the boundary of the core area can be avoided, and the performance of the finally formed semiconductor device is improved.

Drawings

Fig. 1 is a schematic structural diagram of a contact pad layout according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of a layout of a contact pad according to another embodiment of the present invention;

fig. 3 is a schematic structural diagram of a layout of a contact pad according to another embodiment of the present invention;

fig. 4A is a schematic structural diagram of a touch pad structure according to an embodiment of the present invention;

fig. 4B is a schematic structural diagram of a touch pad structure according to another embodiment of the present invention;

fig. 5A is a schematic structural diagram of a first mask plate in a mask plate assembly according to an embodiment of the present invention;

fig. 5B is a schematic structural diagram of a second mask plate in the mask plate assembly according to an embodiment of the present invention;

fig. 6 is a schematic structural diagram of a superposition of two mask plates when the first mask plate and the second mask plate in the mask plate assembly of the present invention are both positive mask plates;

fig. 7 is a schematic structural diagram illustrating a structure of two mask plates stacked when a first mask plate in a mask plate assembly of the present invention is a positive mask plate and a second mask plate is a negative mask plate;

fig. 8A to 8D are schematic structural diagrams illustrating a process of transferring a pattern in a first mask plate or a second mask plate to a layer to be etched according to an embodiment of the present invention;

fig. 9A to 9D are schematic structural diagrams illustrating a process of transferring a pattern in a first mask plate or a second mask plate to a layer to be etched according to another embodiment of the present invention;

fig. 10A is a schematic top view of a semiconductor device according to an embodiment of the present invention;

fig. 11 to 12 are schematic cross-sectional views along aa' in fig. 9A in a method for manufacturing a semiconductor device according to an embodiment of the present invention.

Detailed Description

The memory and the forming method thereof proposed by the present invention will be further described in detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in simplified form and are not to precise scale, and are provided for convenience and clarity in order to facilitate the description of the embodiments of the present invention.

Referring to fig. 1, an embodiment of the present invention provides a contact pad layout of a semiconductor device, where the contact pad layout includes a main layout area 10 and a first edge layout area 11. The main layout area 10 has a plurality of main contact pad patterns 101, each of the main contact pad patterns 101 has a similar shape and size, all the main contact pad patterns 101 are arranged in a checkerboard shape in a staggered manner, a fourth distance D4 is provided between every two adjacent rows of the main contact pad patterns 101, a fifth distance D5 is provided between every two adjacent rows of the main contact pad patterns 101, D4 may be equal to D5, and D4 may not be equal to D5. The first edge layout area 11 is distributed outside one edge of the main layout area 10, and a plurality of first edge contact pad patterns arranged in two rows along the direction of the one edge of the main layout area 10 are disposed in the first edge layout area 11, that is, in the embodiment, a row of first edge contact pad patterns 111 and a row of first edge contact pad patterns 112 are disposed in the first edge layout area 11, and a sixth distance D6 is provided between the two rows of first edge

contact pad patterns

111, 112. The first edge contact pad patterns 112 in a row are relatively close to the main layout area 10, and the shape and size of each first edge contact pad pattern 112 in the row may be the same or not identical, the first edge contact pad patterns 111 in a row are relatively far from the main layout area 10, and the shape and size of each first edge contact pad pattern 111 in the row may be the same or not identical. Each of the first edge

contact pad patterns

111, 112 is aligned with (e.g., arranged in a column alignment with) a corresponding one of the main contact pad patterns 101 in the main layout area 10, and the first edge distance D1 is between the row of the first edge contact pad pattern 112 closest to the main layout area 10 and the row of the main contact pad pattern 101 closest to the first edge contact pad pattern 112 (i.e., the first edge distance D1 is between the first edge layout area 11 and the main layout area 10). Each of the first edge

contact pad patterns

111, 112 has an area greater than that of each of the main contact pad patterns 101, each of the first edge

contact pad patterns

111, 112 is different from the main contact pad patterns 101 (e.g., each of the first edge

contact pad patterns

111, 112 has an area greater than that of the main contact pad pattern 101), the first edge spacing D1 is different from the fourth spacing D4, the sixth spacing D6 is different from the fourth spacing D4 and the first edge spacing D1, e.g., D6 is greater than D1, and D1 is greater than D4.

Optionally, with continuing reference to fig. 1, the contact pad layout of the present embodiment further includes a second edge layout region 12, the second edge layout region 12 is distributed outside an adjacent side of the one side of the main layout region 10, a plurality of second edge contact pad patterns 121 and/or 122 are disposed in the second edge layout region 12, each of the second edge

contact pad patterns

121 and 122 is different from the main contact pad pattern 101, and an area of each of the second edge

contact pad patterns

121 and 122 is greater than an area of each of the main contact pad patterns 101. The second edge layout area 12 and the main layout area 10 have a second edge separation distance D2 therebetween, the second edge separation distance D2 being different from the fourth separation distance D4 and different from the fifth separation distance D5, and may also be different from the first edge separation distance D1. In addition, each of the second edge

contact pad patterns

121 and 122 in the second edge patterning region 12 is aligned with the corresponding main contact pad pattern 101 and the first edge

contact pad patterns

111 and 112 in the main patterning region 10, for example, all the second edge

contact pad patterns

121 and 122 in the second edge patterning region 12 are further arranged in two rows along the direction of the adjacent edge, one row near the main patterning region 10 is the second edge contact pad pattern 121, and one row far from the main patterning region 10 is the second edge contact pad pattern 122, and the second edge

contact pad patterns

121 and 122 in each row may not be completely the same. And the distance between the column of the second edge contact pad patterns 121 nearest to the main layout area 10 and the column of the main contact pad patterns 101 nearest to the main layout area is the second edge distance D2, there is a third distance D3 between the two columns of the second edge

contact pad patterns

121, 122, and the third distance D3 is greater than the second edge distance D2 and is also greater than the fifth distance D5. Optionally, the shapes of the second edge contact pad patterns 122 in a column away from the main layout area 10 in the second edge layout area 12 include at least two of a long bar shape, a U shape laid down to the left, a U shape laid down to the right, an L shape laid down to the left, an L shape laid down to the right, and a comb shape having at least two comb teeth.

Referring to fig. 2, another embodiment of the present invention provides a contact pad layout of a semiconductor device, wherein the contact pad layout includes a main layout area 10, a first edge layout area 11, and a second edge layout area 12. The main layout area 10 has a plurality of main contact pad patterns 101, each of the main contact pad patterns 101 has a similar shape and size, all the main contact pad patterns 101 are arranged in a checkerboard shape in a staggered manner, a fourth distance D4 is provided between every two adjacent rows of the main contact pad patterns 101, a fifth distance D5 is provided between every two adjacent rows of the main contact pad patterns 101, D4 may be equal to D5, and D4 may not be equal to D5. The first edge pattern area 11 is disposed outside one edge of the main pattern area 10, and a strip having a saw-toothed edge is disposed in the first edge pattern area 11 as the first edge contact pad pattern 111. Optionally, the serrated edge faces the main layout area 10, each serration 111a in the serrated edge is aligned with a corresponding main contact pad pattern 101 in the main layout area 10 (e.g., each serration 111a and a corresponding main contact pad pattern 101 are aligned in a column), and the spacing between the serration 111a and the aligned nearest neighboring main contact pad pattern 101 is the first edge spacing D1. That is, in this embodiment, only one row of the first edge pad patterns 111 is disposed in the first edge layout area 11, and the row of the first edge pad patterns 111 is connected as a whole. The shapes and sizes of the respective serrations may or may not be all the same, and the pitches of the serrations 111a are not all the same. The area of each of the serrations may be smaller than, equal to, or larger than the area of each of the primary contact pad patterns 101, and the first edge interval D1 is different from the fourth interval D4. The second edge layout area 12 is disposed outside an adjacent side of the one side of the main layout area 10, a plurality of second edge contact pad patterns 121 and/or 122 are disposed in the second edge layout area 12, each of the second edge

contact pad patterns

121 and 122 is larger than an area of each of the main contact pad patterns 101. The second edge layout area 12 and the main layout area 10 have a second edge separation distance D2 therebetween, the second edge separation distance D2 being different from the fourth separation distance D4 and different from the fifth separation distance D5, and may also be different from the first edge separation distance D1. In addition, the second edge

contact pad patterns

121 and 122 in the second edge patterning region 12 are aligned with the main contact pad patterns 101 in the main patterning region 10, and the remaining second edge

contact pad patterns

121 and 122 are aligned with the first edge contact pad patterns 111, for example, the second edge

contact pad patterns

121, 122, and the third distance D3 is greater than the second edge distance D2 and is also greater than the fifth distance D5. In this embodiment, the second edge contact pad patterns 121 are in a horizontal strip structure, and the length thereof extends along the row direction of the main layout area 10, and the second edge contact pad patterns 122 are in a vertical strip structure, and the length thereof extends along the column direction of the main layout area 10.

Referring to fig. 3, another embodiment of the present invention provides a contact pad layout of a semiconductor device, wherein the contact pad layout includes a main layout area 10, a first edge layout area 11, and a second edge layout area 12. The structure in the main layout area 10 in this embodiment may be the same as the structure in the layout area 10 in the embodiment shown in fig. 1 or fig. 2, and is not described herein again. The first edge pad area 11 is disposed outside one edge of the main pad area 10, two rows of structures are disposed in the first edge pad area 11, one row near the main pad area 10 is disposed with a plurality of first edge contact pad patterns 112, one row far from the main pad area 10 is disposed with a long strip having a saw-toothed edge as the first edge contact pad pattern 111, optionally, the saw-toothed edge faces the main pad area 10, each saw tooth 111a in the saw-toothed edge and the corresponding first edge contact pad pattern 112 are aligned with the corresponding main contact pad pattern 101 in the main pad area 10 (for example, each saw tooth 111a, the first edge contact pad pattern 112 and the corresponding main contact pad pattern 101 are aligned in a column), and the distance between the first edge contact pad pattern 112 and the aligned nearest main contact pad pattern 101 is the first edge distance D1 (i.e., one row of the first edge contact pad pattern 112 and the row of the nearest main contact pad in the main contact pad pattern 101 is aligned with the first edge contact pad pattern 112) The row spacing between patterns 101 is the first edge spacing D1), and the row spacing between a row of first edge pad patterns 112 and a row of first edge pad patterns 111 with jagged edges is the sixth spacing D6. The first edge contact pad patterns 111 are connected as a whole, and the shapes and sizes of the serrations 111a may or may not be identical, and the pitches of the serrations 111a may or may not be identical. The area of each of the serrations 111a may be smaller than, equal to, or larger than the area of each of the main contact pad patterns 101, the first edge interval D1 is different from the fourth interval D4, and the sixth interval D1 is different from the first edge interval D1. The second edge layout area 12 is disposed outside an adjacent side of the one side of the main layout area 10, a plurality of second edge contact pad patterns 121 and/or 122 are disposed in the second edge layout area 12, each of the second edge

contact pad patterns

121, 122, and the third distance D3 is greater than the second edge distance D2 and is also greater than the fifth distance D5. In this embodiment, the second edge contact pad patterns 121 are all in a horizontal strip structure, and the length thereof extends along the row direction of the main layout area 10, and the shapes of the second edge contact pad patterns 122 include at least two of a long strip shape, a U shape laid down to the left, a U shape laid down to the right, an L shape laid down to the left, an L shape laid down to the right, and a comb shape having at least two comb teeth.

The utility model discloses an in the contact pad territory of semiconductor device of each embodiment, main version district is corresponding to the effective area of the core region of semiconductor device or the whole region of the core region of semiconductor device, and each main contact pad pattern is arranged in making the main contact pad in the core region of semiconductor device, and first edge version district and second edge version district correspond respectively the border department of the corresponding side of core region or the border region between the core region of semiconductor device that corresponds to semiconductor device respectively and the peripheral region of the semiconductor device of corresponding side, first edge contact pad pattern and second edge contact pad pattern all are used for making the border department of the corresponding side of core region of semiconductor device or virtual contact pad in the border region. Because the area of each first edge contact pad pattern in the first edge layout area is greater than the area of each main contact pad pattern, and the area of each second edge contact pad pattern in the second edge layout area is greater than the area of each main contact pad pattern, when the main contact pad of the core area is formed based on the contact pad layout of the embodiments of the present invention, the first edge contact pad pattern and the second edge contact pad pattern can be utilized to form a corresponding virtual contact pad, and the area of the top surface of the formed virtual contact pad is greater than the area of the top surface of the formed main contact pad, thereby increasing the size of the subsequent electrical structure connected on the virtual contact pad, improving the dense/sparse effect of the circuit patterns between the core area and the peripheral area when the electrical structure is connected on the main contact pad and the virtual contact pad, and improving the consistency of the electrical structure connected on the main contact pad inside the core area, meanwhile, the problem of abnormal electrical structure connected with the main contact pad at the boundary of the core area can be avoided, and the performance of the finally formed semiconductor device is improved.

Referring to fig. 1 to 3 and 4A, based on the same concept of the present invention, an embodiment of the present invention further provides a touch pad structure formed by using the touch pad layout of the semiconductor device shown in any one of fig. 1 to 3, wherein the touch pad structure includes: a plurality of main contact pads 101a and at least one first edge contact pad 111 b. Each of the main contact pads 101a is fabricated based on the corresponding main contact pad pattern 101 in the main layout area 10, and is located in the core area I of the semiconductor device and arranged in a checkerboard pattern, the shape and the size of each of the main contact pads 101a are similar, and the main contact pads 101a have a fourth distance D4 therebetween, and each of the main contact pads 101a is used for being connected to an effective electrical structure such as a capacitor (e.g., 705b in fig. 11). Each of the first edge contact pads 111b is formed based on the first edge contact pad pattern 111 or the first edge

contact pad patterns

111 and 112, and is distributed outside one side of all the main contact pad arrangement regions, and the top surface area of each of the first edge contact pads 111b is larger than the top surface area of each of the main contact pads (further, the cross-sectional area of each of the first edge contact pads 111b is larger than the cross-sectional area of each of the main contact pads), and a first edge distance D1 is provided between the first edge contact pad 111b (formed based on the first edge contact pad pattern 111) next to the main contact pad 101a and the main contact pad 101 a. Wherein the first edge contact pad 111b has a different size than the main contact pad 101a, and the first edge separation distance D1 is different from the fourth separation distance D4. In this embodiment, each of the first edge contact pads 111b is distributed at the boundary of the core region I, and electrically connects at least the outermost two source/drain regions S/D1 at the boundary of the core region I together (for example, as shown in fig. 11, each of the first edge contact pads 501b crosses over the word line at the boundary of the core region I and the two source/drain regions S/D1 at both sides thereof). The first edge contact pad 111b may be used as a dummy contact pad. Since the top surface area of each of the first edge contact pads 111b is larger than the top surface area of each of the main contact pads 101a, the size of the subsequent electrical structure connected to the first edge contact pad 111b can be increased relative to the size of the electrical structure connected to the main contact pad 101a (for example, the size of the capacitor 705b shown in fig. 11 is larger than that of the capacitor 705a) to reduce the contact resistance between the first edge contact pad 111b and the connected electrical structure, and enhance the reliability of the device, and more importantly, when the corresponding electrical structures are connected to the main contact pad 101a and the first edge contact pad 111b, the size of the connected electrical structure connected to the first edge contact pad 111b can be increased relatively to improve the dense/sparse effect of the circuit pattern between the core area I and the peripheral area II, so as to improve the consistency between the connected electrical structures connected to all the main core contact pads 101a in the core area I, meanwhile, the problem of abnormal electrical structure connected to the main contact pad 101a at the boundary of the core region I (i.e., each main contact pad 101a next to each first edge contact pad 111b) can be avoided, and the performance of the finally formed semiconductor device is improved.

Referring to fig. 1 to 3 and 4B, another embodiment of the present invention further provides a touch pad structure formed by using the touch pad layout of the semiconductor device shown in any one of fig. 1 to 3, wherein the touch pad structure includes: a plurality of main contact pads 101a and at least one first edge contact pad 111 b. Each of the main contact pads 101a is fabricated based on the corresponding main contact pad pattern 101 in the main layout area 10, and is located in the core area I of the semiconductor device and arranged in a checkerboard pattern, the shape and the size of each of the main contact pads 101a are similar, and the main contact pads 101a have a fourth distance D4 therebetween, and each of the main contact pads 101a is used for being connected to an effective electrical structure such as a capacitor (e.g., 705b in fig. 11). Each of the first edge contact pads 111b is formed based on the first edge contact pad pattern 111 or the first edge

contact pad patterns

111 and 112, and is distributed outside one side of all the main contact pad arrangement regions, and the top surface area of each of the first edge contact pads 111b is larger than the top surface area of each of the main contact pads (further, the cross-sectional area of each of the first edge contact pads 111b is larger than the cross-sectional area of each of the main contact pads), and a first edge distance D1 is provided between the first edge contact pad 111b (formed based on the first edge contact pad pattern 111) next to the main contact pad 101a and the main contact pad 101 a. Wherein the first edge contact pad 111b has a size different from that of the main contact pad 101a, and the first edge distance D1 is different from the fourth distance D4. In this embodiment, each of the first edge contact pads 111b is distributed on the boundary region III between the core region I and the peripheral region II, and is electrically connected to at least one source/drain region S/D1 at the boundary of the core region I (for example, as shown in fig. 12, each of the first edge contact pads 501b extends from the boundary region III to an outermost source/drain region S/D1 at the boundary of the core region I, so as to connect the shallow trench isolation structure STI401a of the boundary region III and the source/drain region S/D1 next to the shallow trench isolation structure STI401a together). The first edge pad 111b may be a dummy pad. Since the top surface area of each of the first edge contact pads 111b is larger than the top surface area of each of the main contact pads 101a, the size of the subsequent electrical structure connected to the first edge contact pad 111b can be increased relative to the size of the electrical structure connected to the main contact pad 101a (as shown in fig. 11, the size of the capacitor 705b is larger than that of the capacitor 705a), so that when the main contact pad 101a and the first edge contact pad 111b are connected to the corresponding electrical structures, respectively, the relative increase in the size of the electrical structure connected to the first edge contact pad 111b can be utilized to improve the dense/sparse effect of the circuit pattern between the core region I and the peripheral region II, thereby improving the uniformity between the electrical structures connected to all the main contact pads 101a in the core region I, and simultaneously avoiding the electrical structure connected to the main contact pad 101a at the boundary of the core region I (i.e. the main contact pad 101a next to the first edge contact pad 111b) The abnormal structure of the semiconductor device improves the performance of the finally formed semiconductor device. In addition, it should be noted that, in other embodiments of the present invention, the first edge contact pads 111b may be located on the boundary region III as a whole. In the case that each first edge contact pad 111b is at least partially formed on the interface region III, on one hand, the occupied area of the first edge contact pad 111b and the electrical structure connected thereto on the core region I can be reduced as much as possible, which is beneficial to improving the utilization rate of the effective area of the core region, and is further beneficial to improving the density of devices; on the other hand, the size of the first edge contact pad 111b and the electrical structures connected thereto may be increased as much as possible, so that the uniformity among the electrical structures connected to all the primary contact pads 101a in the core region I may be improved.

It should be noted that, when the contact pad structure in each embodiment of the present invention is manufactured based on the contact pad layout shown in fig. 1, the number of the first edge contact pads 111b is multiple, and the first edge contact pads 111b are arranged in two rows along the direction of the one edge of the arrangement region of the main contact pad 101a (i.e., the region within the boundary of the core region I, which may be referred to as the central region or the inner region of the core region I), each of the first edge contact pads 111b is aligned with the corresponding main contact pad 101a, and the distance between the one row of first edge contact pads 111b closest to the arrangement region of the main contact pad 101a (i.e., the first edge contact pad 111b formed based on the first edge contact pad pattern 112) and the nearest one row of main contact pads 101a is the first edge distance D1. When the contact pad structure in various embodiments of the present invention is manufactured based on the contact pad layout shown in fig. 2 or fig. 3, the first edge contact pad 111b includes a long strip (not shown) having a serrated edge, that is, corresponding to the first edge contact pad pattern 111 in fig. 2 or fig. 3, optionally, the serrated edge is disposed facing the arrangement region of the main contact pad 101a, each sawtooth in the long serrated edge is aligned with the corresponding main contact pad 101a, and the distance between the sawtooth and the nearest main contact pad 101a aligned with the long sawtooth is the first edge distance D1.

In addition, optionally, referring to fig. 1 to fig. 3, the contact pad structure of the various embodiments of the present invention may further include a plurality of second edge contact pads (not shown), the second edge contact pads are formed based on the second edge

contact pad patterns

121, 122 in the second edge patterning region 12, the second edge contact pads are distributed outside the adjacent side of the one side of all the main contact pad arrangement regions, and the top surface area of each of the second edge contact pads is larger than the top surface area of each of the main contact pads (further, the cross-sectional area of each of the second edge contact pads is larger than the cross-sectional area of each of the main contact pads), a second edge distance D2 is provided between the second edge contact pads (i.e. the second edge contact pads formed based on the second edge contact pad patterns 121) next to the main contact pads, the second edge contact pad shape is different than the first edge contact pad shape, and the second edge separation distance D2 is different than the fourth separation distance D4. Optionally, each of the second edge contact pads is aligned with a corresponding main contact pad, for example, all of the second edge contact pads are arranged in two columns along the direction of the adjacent edge, and a distance between a column of the second edge contact pads nearest to the main contact pad arrangement region and a column of the main contact pads nearest to the main contact pad arrangement region is the second edge distance D2, a third distance D3 is provided between two columns of the second edge contact pads, and the third distance D3 is greater than the second edge distance D2. Optionally, the cross-sectional shapes (or top surface shapes) of the second edge contact pads in a column away from the main contact pad arrangement region in all the second edge contact pads include at least two of a long bar shape, a U shape laid down to the left, a U shape laid down to the right, an L shape laid down to the left, an L shape laid down to the right, and a comb shape having at least two comb teeth.

In addition, referring to fig. 4A and 4B, in the contact pad structure of the semiconductor device according to various embodiments of the present invention, the main contact pad 101a, the first edge contact pad 101B and the second edge contact pad may be formed simultaneously with the contact pad 105 in the peripheral region II, the main contact pad 101a is connected to the corresponding active region AA1 (i.e., the corresponding source/drain region S/D1) in the core region I through the corresponding contact plug 103a, the first edge contact pad 101B and the second edge contact pad are connected to the corresponding active region AA1 (i.e., the corresponding source/drain region S/D1) at the boundary of the core region I or connected to the shallow trench isolation structure 100a in the boundary region III through the corresponding contact plug 103B, and the contact pad 105 is connected to the corresponding source/drain region S/D2 in the peripheral region II through the contact plug 103 c. Wherein, each contact pad is formed by adopting the same filling process; each contact pad and the contact plug contacted with the contact pad can be separately manufactured or can be formed by the same metal filling process, wherein when each contact pad and the contact plug contacted with the contact pad are separately manufactured, the interlayer dielectric layer 102 can be deposited firstly and etched, filled with metal and flattened to form the contact plugs 103a, 103b and 103c together, then the interlayer dielectric layer 104 is deposited secondly and etched, filled with metal and flattened to form the main contact pad 101a, the first edge contact pad 111b, the second edge contact pad and the contact pad 105 together, when each contact pad and the contact plug contacted with the contact pad are formed by the same metal filling process, a thicker interlayer dielectric layer (for example, the thickness of the interlayer dielectric layer is equal to the sum of the thicknesses of the interlayer dielectric layer 102 and the interlayer dielectric layer 104) can be deposited at one time, and then a channel communicated with each contact pad and the contact plug contacted with the contact pad is formed by the corresponding etching process and, then, each channel is filled with metal and planarized, so that the contact plugs 103a, 103b, and 103c and the main contact pad 101a, the first edge contact pad 111b, the second edge contact pad, and the contact pad 105 are formed together, at this time, the main contact pad 101a and the contact plug 103a contacting therewith are integrally formed, the first edge contact pad 111b and the contact plug 103b contacting therewith are integrally formed, the second edge contact pad and the contact plug 103b contacting therewith are integrally formed, and the contact pad 105 and the contact plug 103c contacting therewith are integrally formed.

Referring to fig. 1 to 3 and fig. 4A to 4B, based on the same concept, an embodiment of the present invention further provides a semiconductor device, including: semiconductor substrate 100, interlevel dielectric layer and contact pad structure for a semiconductor device according to the present invention. The semiconductor substrate is provided with a core area I, a peripheral area II and a junction area III located between the core area I and the peripheral area II, a plurality of core elements are formed in the core area I, each core element is formed on a corresponding active area AA1, a shallow trench isolation Structure (STI)100b is formed between adjacent active areas AA1, each core element can be an MOS transistor and is provided with a buried gate formed in the corresponding active area AA1 and source and drain areas S/D1 located on two sides of the buried gate. The interlayer dielectric layer is provided with an interlayer dielectric layer 102 and an interlayer dielectric layer 104 which are sequentially covered on the semiconductor substrate 100. A Shallow Trench Isolation (STI)100a for isolating the core region I and the peripheral region II is formed in the boundary region III. The contact pad structure is formed in the interlayer dielectric layer 104, and includes at least a main contact pad 101a and a first edge contact 111b, and may further include a second edge contact pad. The semiconductor device also includes contact plugs underlying respective contact pads and electrical structures (e.g., capacitors or resistors, etc.) overlying respective contact pads. Each

contact plug

103a, 103b, 103c is formed in the interlayer dielectric layer 102, each contact plug 103a is aligned with the bottom of the corresponding main contact pad 101a and the corresponding active area AA1 (i.e., the corresponding source drain region S/D1) of the core element to electrically connect the corresponding main contact pad 101a and the active area AA1 of the core element, the top of each contact plug 103b is aligned with the bottom of the corresponding first edge contact pad 111b or second edge contact pad, and the bottom of each contact plug 103b is aligned with the active area AA1 (i.e., the corresponding source drain region S/D1) at the boundary of the core area I or the STI 100a in the boundary region III to connect the corresponding first edge contact pad 111b or second edge contact pad and the active area AA1 at the boundary of the core area I or the STI 100a in the boundary region III.

Referring to fig. 5A and 5B, based on the same concept of the present invention, the present invention further provides a mask plate assembly for manufacturing the contact pad structure of the semiconductor device, including: a first mask plate 20 and a second mask plate 30. The first mask plate 20 has a plurality of parallel first lines 201, a first spacer 202 is disposed between two adjacent first lines 201, a line width of at least one outermost first line 201 of the first mask plate 20 is greater than that of the other first lines 201, and a line width of at least one outermost first spacer 202 of the first mask plate 20 is greater than that of the other first spacers 202. For example, the two outermost first lines 201 (i.e., the outermost first line 201a and the second first line 201b) of the first mask 20 each have a line width greater than that of the other first lines 201, the line width of the first line 201a is greater than that of the first line 201b, the line width D6 of the first space 202 (i.e., the outermost one of the first spaces 202 of the first mask 20) between the

first lines

201a and 201b is greater than that of the other first spaces 202, and the line width D1 of the first space 202 between the first line 201b and the other adjacent first line 201 is different from the line width D4 of the other first spaces 202 except the first spaces 202 between the

first lines

201a and 201 b. The second mask plate 30 has a plurality of second stripes 301 which are parallel and vertically intersected with each first stripe 201, a second spacing region 302 is arranged between two adjacent second stripes 301, the line width of at least one second stripe 301 at the outermost side of the second mask plate 30 is greater than that of the other second stripes 301, the line width of at least one second spacing region 302 at the outermost side of the second mask plate 30 is greater than that of the other second spacing regions 302, for example, the line widths of two second stripes at the outermost side of the second mask plate 30 (i.e. the outermost first second stripe 301a and the outermost second stripe 301b) are both greater than that of the other second stripes 301, the line width of the second stripe 301 is greater than that of the second stripe 301b, the line width of the second spacing region 302 between the second stripes 301a and 301b (i.e. the outermost second spacing region 302 of the second mask plate 30) is greater than that of the other second spacing regions 302, and a line width of the second spacer region 302 between the second line 301b and another adjacent second line 301 is different from a line width of the other second spacer regions 302 except the second spacer region 302 between the second lines 301a, 301 b. Alternatively, in the second mask plate 30, the line widths of the end portions 303 of all the other second lines 301 except the first second line 301a and the second line 301b are greater than the line width of the middle area of the second line 301.

Referring to fig. 6, when the first mask plate 20 and the second mask plate 30 are isotropic mask plates and the second mask plate 30 and the first mask plate 20 are aligned and overlapped, the overlapped area of each first line 201 and each second line 301 is an area for forming a contact pad, so that the overlapped area of the first line 201a and each second line 301 except the second lines 301a and 301b defines each first edge contact pad pattern 111 in the first edge layout area 11 in fig. 1, and the overlapped area of the first line 201b and each second line 301 except the second lines 301a and 301b defines each first edge contact pad pattern 112 in the first edge layout area 11 in fig. 1; the overlapping area of the second line 301a and each of the first lines 201 except the first lines 201a and 201b defines each of the second edge contact pad patterns 122 in the second edge layout region 12 in fig. 1, the overlapping area of the second line 301b and each of the first lines 201 except the first lines 201a and 201b defines each of the second edge contact pad patterns 121 in the second edge layout region 12 in fig. 1, the overlapping area of each of the first lines 201 except the first lines 201a and 201b and each of the second lines 301 except the second lines 301a and 301b defines the main layout region 10 and each of the main contact pad patterns 101 therein in fig. 1, the first space region 202 between the first line 201b and the first line 201 adjacent to the inside thereof defines a first edge distance D1 between the first edge layout region 11 and the main layout region 10, and the line width of the first space region 202 between the first line 201b and the first line 201 adjacent to the outside thereof defines a line width of the first space region 202 between the first line 201b and the first line 201 adjacent to the outside thereof A sixth distance D6 between two rows of the first edge contact pad patterns 111, 112 in the first edge layout region 11, the remaining first spacing regions 202 define a fourth distance D4 between the two rows of the main contact pad patterns, the second spacing regions 302 between the second lines 301b and the adjacent second lines 301 on the inner side thereof define a second edge distance D2 between the second edge layout region 12 and the main layout region 10, the line width of the second spacing regions 302 between the second lines 301b and the adjacent second lines 301a on the outer side thereof define a third distance D3 between two columns of the second edge contact pad patterns 121, 122 in the second edge layout region 12, and the remaining second spacing regions 302 define a fifth distance D5 between two columns of the main contact pad patterns. Wherein, the meaning that the first mask plate 20 and the second mask plate 30 are isotropic mask plates is: for example, when both the masks are negative masks, the mask structure for etching the lower film layer is formed by using the corresponding portions of the first and second lines of the first and

second masks

20 and 30 respectively after photolithography as the mask structure for etching the lower film layer.

Referring to fig. 7, when the first mask plate 20 and the second mask plate 30 are opposite mask plates and the second mask plate 30 and the first mask plate 20 are aligned and overlapped, an overlapping area of each first line 201 and each second spacer region 302 is an area for forming a contact pad, so that the overlapping area of the first line 201a and each second spacer region 302 defines each first edge contact pad pattern 111 in the first edge layout region 11 in fig. 3, and the overlapping area of the first line 201b and each second spacer region 302 defines each first edge contact pad pattern 112 in the first edge layout region 11 in fig. 3; the second lines 301a define a third pitch D3 in the second edge layout region 12 in fig. 3, the second lines 301b define a second edge pitch D2 between the second edge layout region 12 and the main layout region 10 in fig. 3, ends 203 of the respective first lines 201 exposed outside the second lines 301a define respective second edge contact pad patterns 122 in the second edge layout region 12 in fig. 3, portions of the respective first lines 201 exposed by the second partition regions 302 between the second lines 301a and the second lines 301b define respective second edge contact pad patterns 121 in the second edge layout region 12 in fig. 3, portions of the respective first lines 201 exposed by the remaining second partition regions 302 define respective main contact pad patterns 101 in the main layout region 10 in fig. 3, and the second lines 301 other than the second lines 301b and the second lines 301a define a fifth column D5 between the main contact pad patterns 101 in the main layout region 10 in fig. 3, the first lines 201 other than the first lines 21b and 201a define a fourth distance D4 between the two rows of the main contact pad patterns 101 in the main layout area 10 in fig. 3. Wherein the meaning that the first mask plate 20 and the second mask plate 30 are opposite mask plates is: the two mask plates have opposite pattern development properties, one of which retains a portion corresponding to the lines thereof, and the other of which retains a portion corresponding to the space therebetween. For example, when the first mask plate is a negative mask plate and the second mask plate 30 is a positive mask plate, the portion corresponding to the first spacing region is correspondingly reserved after the first mask plate 20 is subjected to photolithography as a mask structure for etching the lower film layer, and the portion corresponding to the second line is correspondingly reserved after the second mask plate 30 is subjected to photolithography as a mask structure for etching the lower film layer; when the first mask plate 20 is a positive mask plate and the second mask plate 30 is a negative mask plate, the portion corresponding to the first line that is reserved after the first mask plate 20 is photoetched is used as a mask structure for etching the lower film layer, and the portion corresponding to the second spacing region that is reserved after the second mask plate 30 is photoetched is used as a mask structure for etching the lower film layer.

Referring to fig. 5A and 7, alternatively, at least two ends 203 of the first lines 201 are connected to one side of the first mask plate 20, so that the shapes of the outermost columns of second edge contact pad patterns in the defined second edge layout area are not completely the same and include at least two of a long bar shape, a U shape laid down to the left, a U shape laid down to the right, an L shape laid down to the left, an L shape laid down to the right, and a comb shape having at least two comb teeth.

Referring to fig. 6 and 7, optionally, when the second mask plate 30 and the first mask plate 20 are aligned and overlapped, the ends of all the second lines 301 (including the outermost second line 301b) except the outermost first second line 301a of the second mask plate 30 do not exceed the outermost first line 201a of the first mask plate 20. Referring to fig. 7, when the first mask plate 20 and the second mask plate 30 are opposite mask plates and the second mask plate 30 and the first mask plate 20 are aligned and overlapped, the outermost first second line 301 of the second mask plate 30 exposes the end 203 of at least one first line 201.

It should be noted that, in the embodiments of the present invention, the first mask plate 20 and the second mask plate 30 may be mask plates capable of transferring the patterns of the first stripe and the first spacer, the second stripe and the second spacer to the layer for forming the contact pad structure by one photolithography process, or may be mask plates capable of transferring the patterns of the first stripe and the first spacer, the second stripe and the second spacer to some auxiliary layers (for example, a hard mask layer on the layer for forming the contact pad structure) by a double patterning process or a multiple patterning process, respectively, so as to form the required patterns of the first stripe and the first spacer in some auxiliary layers (for example, the hard mask layer on the layer for forming the contact pad structure), where the auxiliary layer having the pattern of the first stripe and the first spacer is the first mask plate 20, and the auxiliary layer having the pattern of the second stripe and the second spacer is the first mask plate 30, of course, in some embodiments of the present invention, the overlapped patterns with the first stripe, the first spacer, the second stripe and the second spacer aligned with each other may also be formed in the same auxiliary layer (e.g. a hard mask layer on a layer for forming a contact pad structure) by a double patterning or multiple patterning process, and the auxiliary layer may be regarded as a mask assembly formed by aligning and overlapping the first mask 20 and the second mask 30. In order to more clearly understand how to form the first mask plate 20 or the second mask plate 30 by the double pattern forming or the multiple pattern forming process, the following description will be made in detail with reference to fig. 8A to 8D and fig. 9A to 9D.

Referring to fig. 8A to 8D, in an embodiment of the present invention, the specific steps of forming the first mask plate 20 or the second mask plate 30 by the double patterning process include:

first, referring to fig. 8A, a semiconductor substrate 800 is provided, an etch stop layer 801 (e.g., silicon oxide, etc.), an interlayer dielectric layer 802 (a layer for forming a contact pad), a hard mask layer 803 (e.g., silicon nitride, etc.), a first auxiliary layer 804 (e.g., an organic dielectric layer, etc.), a bottom anti-reflection layer 805, and a photoresist layer 806 are sequentially formed on the semiconductor substrate 800, and the photoresist layer 806 may be patterned by a single photolithography process to form corresponding patterns;

then, referring to fig. 8B, with the patterned photoresist layer 806 as a mask, the bottom anti-reflection layer 805 and the first auxiliary layer 804 are etched to the top surface of the hard mask layer 803, so as to transfer the pattern in the patterned photoresist layer 806 to the first auxiliary layer 804, and the remaining bottom anti-reflection layer 805 and the first auxiliary layer 804 form a plurality of cores, and then the patterned photoresist layer 806 is removed;

next, referring to fig. 8B and 8C, covering the second auxiliary layer 807 on the bottom anti-reflection layer 805, the first auxiliary layer 804 and the hard mask layer 803, and etching the second auxiliary layer 807 to form sidewalls 807a on sidewalls of each core (i.e., the bottom anti-reflection layer 805 and the first auxiliary layer 804), and then removing each core (i.e., the bottom anti-reflection layer 805 and the first auxiliary layer 804), where all the sidewalls 807a and the spaces thereof constitute a plate layer that is the first mask 20 or the second mask 30, for example, in the case of the first mask 20, the sidewalls 807a are the first lines 201 in the first mask 20, and the spaces between adjacent sidewalls 807a are the first lines 201 in the first spacer mask 20.

Then, referring to fig. 8C and 8D, the hard mask layer 803 and the interlayer dielectric layer 802 are etched using the spacers 807a as masks, so as to form trenches extending along the first direction (i.e., corresponding to the first lines 201 in the first mask plate 20) in the interlayer dielectric layer 802 at positions corresponding to the spaces between the spacers 807 a.

It should be noted that, when the first mask plate 20 and the second mask plate 30 are both formed by the method shown in fig. 8A to 8D, a trench extending along a first direction (i.e., corresponding to the first line 201 in the first mask plate 20) and a trench extending along a second direction perpendicular to the first direction (i.e., corresponding to the second line 301 in the second mask plate 30) are formed in the interlayer dielectric layer 802, and a junction of the trenches in the two directions is a position for forming the contact pad.

Referring to fig. 9A to 9D, in another embodiment of the present invention, the specific steps of forming the first mask plate 20 or the second mask plate 30 by the double patterning process include:

first, referring to fig. 9A, a semiconductor substrate 800 is provided, an etch stop layer 801 (e.g., silicon oxide, etc.), an interlayer dielectric layer 802 (a layer for forming a contact pad), a hard mask layer 803 (e.g., silicon nitride, etc.), a first auxiliary layer 804 (e.g., an organic dielectric layer, etc.), a bottom anti-reflection layer 805, and a photoresist layer 806 are sequentially formed on the semiconductor substrate 800, and the photoresist layer 806 may be patterned by a single photolithography process to form corresponding patterns;

then, referring to fig. 9B, with the patterned photoresist layer 806 as a mask, the bottom anti-reflection layer 805 and the first auxiliary layer 804 are etched to the top surface of the hard mask layer 803, so as to transfer the pattern in the patterned photoresist layer 806 to the first auxiliary layer 804, and the remaining bottom anti-reflection layer 805 and the first auxiliary layer 804 form a plurality of cores, and then the patterned photoresist layer 806 is removed;

next, referring to fig. 9B and 9C, the second auxiliary layer 807 and the third auxiliary layer 809 are sequentially covered on the bottom anti-reflection layer 805, the first auxiliary layer 804 and the hard mask layer 803, the top of the third auxiliary layer 809 is planarized until the top surface of the bottom anti-reflection layer 805 is exposed, and the second auxiliary layer 807 on the sidewall of each core (i.e., the bottom anti-reflection layer 805 and the first auxiliary layer 804) is etched and removed to form an opening 808. At this time, the remaining board layer structure composed of the second auxiliary layer 807, the third auxiliary layer 809, the bottom anti-reflection layer 805, the first auxiliary layer 804 and the opening 808 is the first mask blank 20 or the second mask blank 30, for example, when the first mask blank 20 is used, the opening 808 is the first line 201 in the first mask blank 20, and the stacked structure formed by the second auxiliary layer 807 and the third auxiliary layer 809 on each side of the opening 808 or the stacked structure formed by the bottom anti-reflection layer 805 and the first auxiliary layer 804 film layer is the first spacer 202 in the first mask blank 20.

Then, the same method may be adopted to fabricate a second mask plate 30 on the formed first mask plate 20, or fabricate the first mask plate 20 on the formed second mask plate 30, so as to form a mask plate combination which aligns and overlaps the first mask plate 20 and the second mask plate 30, and then etch the hard mask layer 803 and the interlayer dielectric layer 802 using the mask plate combination as a mask, so as to form a trench for fabricating a contact pad in the interlayer dielectric layer 802.

The following describes in detail a method for manufacturing a semiconductor device having a contact pad layout according to the present invention, taking a semiconductor device as an example of a dynamic random access memory, with reference to fig. 10A to 12.

First, referring to fig. 10A and 10B, a semiconductor substrate 400 having a plurality of core devices (i.e., memory transistors) is provided, which includes the following steps: first, a semiconductor substrate 400a including a core region I, a peripheral region II and a junction region III is provided. In this embodiment, the core region I is a storage region, the core element to be formed in the core region I includes a selection element, a data storage element is connected to the core element subsequently, the selection element is, for example, a MOS transistor or a diode, the data storage element is, for example, a capacitor, a variable resistor, or the like, and one selection element and the corresponding data storage element constitute a storage unit. Peripheral circuitry (e.g., NMOS and PMOS transistors, diodes, or resistors) may be formed in the peripheral region II to control the memory cells. A plurality of shallow trench isolation structures 401b are formed in the semiconductor substrate 400a in the core region I, a shallow trench isolation structure 401a is formed in the semiconductor substrate 400a in the boundary region III, the shallow trench isolation structure 401a defines a boundary between the core region I and the peripheral region II on a two-dimensional plane, and the shallow trench isolation structure 401b defines an active region AA1 corresponding to each core element in the core region I. The active areas AA1 are distributed in a stripe shape on a two-dimensional plane and extend along a first direction, and the active areas AA1 may be arranged in a staggered arrangement on the surface of the semiconductor substrate 400 a. Then, the embedded word lines WL are formed in the semiconductor substrate 400a, and the embedded word lines WL are typically embedded at a predetermined depth in the semiconductor substrate 400a, extend along a second direction (i.e., the row direction) and pass through the shallow trench isolation structure 401b and the active area AA1, and the second direction is not perpendicular to the first direction of the active area AA 1. The embedded word lines WL serve as gates to control the switching of the memory cells, and are usually surrounded by gate dielectric layers (not shown) at the sidewalls and bottom, and the top of the embedded word lines WL are capped by the gatesLayer 402 is buried inside. Since the embedded word line WL is not the focus of the present invention, the related fabrication process can refer to the known technical solutions in the art, and will not be described in detail herein. In addition, the gate dielectric layer may include silicon oxide or other suitable dielectric materials, the buried word line WL may include aluminum, tungsten, copper, titanium-aluminum alloy, polysilicon or other suitable conductive materials, and the gate cap layer 402 may include silicon nitride, silicon oxynitride, silicon carbide nitride or other suitable insulating materials. Furthermore, a second type dopant, such as a P-type or N-type dopant, may be doped into the active regions AA1 on both sides of the buried word line WL to form a source region and a drain region (collectively defined as S/D1), one of the AA1 on both sides of the buried word line WL is located at the center of the AA1 corresponding to the predetermined bit line contact structure, and the other is located at the end of the active region AA1 corresponding to the predetermined storage node contact structure. The word lines WL and S/D1 may constitute or define a plurality of MOS memory transistors formed on the core region I of the semiconductor device. In addition, source and drain regions (collectively defined as S/D2) corresponding to the peripheral transistors may be formed in the peripheral region II together with the S/D1. After the S/D1 and S/D2 are formed, an etching stop layer 403 may be further formed on the semiconductor substrate 400a, the etching stop layer 303 covers the S/D1 and S/D2, and the material thereof includes, for example, silicon nitride (SiN) and/or silicon oxide (SiO)₂) And the like. Then, a plurality of bit line contacts (not shown) and bit lines BL located above the bit line contacts are formed on the S/D1 of the core region I serving as the drain region, and the bit line contacts may be formed by first etching the S/D1 between two adjacent WLs formed in one active region AA1 to form a recess, and then forming a metal silicide in the recess. The bit lines BL are parallel to each other and extend along a third direction (i.e., a column direction) perpendicular to the buried word lines WL, and simultaneously cross the active regions AA1 and the buried word lines WL. Each bit line BL includes, for example, a semiconductor layer (e.g., polysilicon, not shown), a barrier layer (e.g., comprising Ti or TiN, not shown), a metal layer (e.g., tungsten, aluminum, or copper, not shown), and a mask layer (e.g., comprising silicon oxide, silicon nitride, or silicon carbonitride, not shown) stacked in sequence. In addition, in the semiconductor substrate 400a, at least one gate structure G1 is formed on the peripheral region II, which includes a gate dielectric layer (not shown) and a gate layer (not shown) stacked in sequence. In one embodiment, the gate layer of the gate structure G1 is formed together with the semiconductor or metal layer of the bit line BL. Further, different processes or the same process may be used to form the sidewalls 404 respectively surrounding the bit lines BL and the gate structures G1. For example, the sidewall of the gate structure G1 may be formed by first forming the sidewall 404 of the gate structure G1 to include silicon oxide or silicon oxynitride (SiON), and then forming the sidewall 405 of the bit line BL to include silicon nitride. In addition, in the manufacturing process of the sidewall of the gate structure G1, an etching back (etching back) process may be performed to make the overall height of the gate structure G1 lower than the bit lines BL.

Then, the contact pad layout shown in fig. 1 to 3 or the mask plate combination shown in fig. 5A to 7 of the present invention may be adopted to form the storage node contact structure. The specific process is as follows:

first, referring to fig. 11 or 12, after providing a semiconductor substrate 400 having a bit line BL, a source region and a drain region S/D1 of a core device, an interlayer dielectric layer 500 is formed on the semiconductor substrate 400, wherein the interlayer dielectric layer may be made of silicon oxide, silicon nitride, or low-K dielectric. Specifically, the semiconductor substrate 400 is covered with the interlayer dielectric layer 500 completely by a deposition process, the interlayer dielectric layer 500 fills the space between the bit lines BL, and the bit lines BL, the gate structure G1 and the sidewalls 404 thereof are buried therein, and then the interlayer dielectric layer 500 is planarized by a chemical mechanical polishing process or the like, so as to form the interlayer dielectric layer 500 having a flat top surface as a whole. Wherein the top surface of the planarized interlevel dielectric layer 500 is not lower than at least the top surface of each bit line BL.

Next, referring to fig. 11 or 12, a series of processes including deposition of auxiliary layers, photolithography, and etching are performed to form a mask combination pattern (not shown) on the interlayer dielectric layer 400, where the mask combination pattern is any one of the contact pad layouts in fig. 1 to 3, where the mask combination pattern is aligned with the overlapped mask combination pattern shown in fig. 6 or 7, so as to define the position of each storage node contact structure, and then the mask combination pattern is used as an etching mask to anisotropically etch the interlayer dielectric layer 500, so as to form a contact hole (not shown) penetrating the interlayer dielectric layer 500 and exposing the corresponding S/D1 serving as a source region below the interlayer dielectric layer and a contact hole (not shown) exposing the source region S/D2 or the gate G1 in the peripheral region II. The contact holes corresponding to the first edge contact pad pattern and the second edge contact pad pattern in the contact pad layout may be formed at the boundary of the core region I (at this time, the tops of the contact holes are connected together and cross at least one word line WL at the outermost side of the boundary of the core region I), or at least partially formed on the STI401a of the boundary region III; contact holes corresponding to the main contact pad patterns in the contact pad layout are formed in the core region I.

Next, with reference to fig. 11 or 12, after forming the contact holes, an ashing process or a wet cleaning process or other suitable processes may be performed to remove the film layer above the interlayer dielectric layer 500, and each contact hole is sequentially filled with a barrier metal layer (not shown) and a conductive metal layer (not shown), wherein the barrier metal layer may cover the inner walls of the contact holes and the top surface of the interlayer dielectric layer 500 with a uniform thickness, the barrier metal layer may reduce or prevent the metal material disposed in the contact holes from diffusing into the interlayer dielectric layer 500, and the barrier metal layer may be formed of Ta, TaN, TaSiN, Ti N, TiSiN, W, WN, or any combination thereof, and may be formed by using a Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), or Physical Vapor Deposition (PVD) (e.g., sputtering); the conductive metal layer may be formed from refractory metal(s) (e.g., cobalt, iron, nickel, tungsten, and/or molybdenum). In addition, the conductive metal layer may be formed using a deposition process having good step coverage properties, for example, using Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), or Physical Vapor Deposition (PVD) (e.g., sputtering). The formed conductive metal layer also covers the surface of the interlayer dielectric layer 500 around the contact hole, and then a Chemical Mechanical Polishing (CMP) process may be used to perform a CMP on the top surface of the deposited conductive metal layer until the top surface of the interlayer dielectric layer 500 is exposed, so as to form the main contact pad 501a, the

peripheral contact pads

501d and 501e, and the first edge contact pad (or the second edge contact pad) 501b in the interlayer dielectric layer 500. The primary contact pad 501a serves as a storage node contact structure in the core region I for connection with a capacitor structure subsequently formed over the core region I. The first edge contact pad (or the second edge contact pad) 501b is formed by at least two contact plugs connected at the top in the boundary of the core region I (as shown in fig. 11), or formed by a contact plug in the boundary region III and a contact plug top in the boundary of the core region I being connected together (as shown in fig. 12), or formed by a contact structure with a larger size in the boundary region III (not shown) as a dummy storage node contact structure at the boundary of the core region I or in the boundary region III for connecting with a capacitor structure subsequently formed at the boundary of the core region I or above the boundary region III, and the first edge contact pad (or the second edge contact pad) 501b is aligned parallel to the bit line BL. The cross-sectional structure of the first edge contact pad (or the second edge contact pad) 501b is, for example, an inverted U-shaped electrical contact structure or a comb-shaped electrical contact structure. The peripheral contact pad 501D serves as a contact structure of the gate structure G1 in the peripheral region II and is used for leading out the gate structure G1, and the peripheral contact pad 501e serves as a contact structure of the source region or the drain region S/D2 in the peripheral region II and is used for leading out the source region or the drain region S/D2 in the peripheral region II. The main contact pad 501a, the

peripheral contact pads

501d and 501e, and the first edge contact pad (or the second edge contact pad) 501b may be formed integrally, or may be formed by a pad and a contact plug connected thereunder.

Thereafter, with reference to fig. 11 or 12, a corresponding capacitor structure may be formed on the core region I by a conventional capacitor structure forming method in the art, and the specific process is not described in detail herein. Each main contact pad 501a of the core area I is connected with a capacitor 705a, and a first edge contact pad or a second edge contact pad 501b of the boundary area III and/or the boundary area I is connected with a capacitor 705b, each capacitor includes a lower electrode layer 701, a capacitor dielectric layer 702 and an upper electrode layer 703, and there are a bottom support layer 600, a middle support layer 601 and a top support layer 602 stacked laterally and spacedly between the capacitors, wherein the bottom support layer 600 is used for bottom support of a subsequently formed lower electrode layer, and is also used for isolating internal elements of the semiconductor substrate 400 from elements such as capacitors above. The formation process of the bottom supporting layer 600 may also be a thermal oxidation process. The material of the bottom support layer 600, the middle support layer 601 and the top support layer 602 includes, but is not limited to, silicon nitride. In other embodiments of the present invention, in order to better support the lower electrode layer, more than two intermediate support layers 601 may be stacked between the bottom support layer 600 and the top support layer 602. The capacitor 705b has a first width W1 and the capacitor 705a has a second width W2, optionally W1 is greater than W2, e.g., W1-1.3W 2-2.3W 2. Alternatively, all of the capacitors may be in a hexagonal close-packed arrangement. Further, the lower electrode layer 701 has a cylindrical structure, and may be a polysilicon electrode or a metal electrode. When the lower electrode layer 701 is a metal electrode, a stacked structure of titanium nitride (TiN) and Ti may also be employed. When the lower electrode layer 701 is a polysilicon electrode, it may be formed using a polysilicon material that is zero-doped and/or doped. The capacitance dielectric layer 702 covers the inner surface and the outer surface of the cylindrical structure of the lower electrode layer 701, so that two opposite surfaces of the lower electrode layer 701 are fully utilized to form a capacitor with a large electrode surface area. Preferably, the capacitor dielectric layer 702 may be a high-K dielectric layer such as a metal oxide. Further, the capacitor dielectric layer 702 has a multi-layer structure, such as a two-layer structure of haar-zirconia. The upper electrode layer 703 may have a single-layer structure or a multi-layer structure, and when the upper electrode layer 703 has a single-layer structure, it may be, for example, a polysilicon electrode or a metal electrode, and when the upper electrode layer 703 is a metal electrode, it may be formed, for example, by titanium nitride (TiN). The upper electrode layer 703 can constitute a capacitor with the capacitor dielectric layer 702 and the lower electrode layer 701 both inside the cylindrical structure and outside the cylindrical structure. In addition, in the edge region of the core region I (i.e. the boundary region of the capacitor hole array), due to the existence of the lateral support layers (i.e. the middle support layer 601 and the top support layer 602), the capacitor dielectric layer 702 and the upper electrode layer 703 both have uneven-profile sidewall structures corresponding to the middle support layer 601 and the top support layer 602 outside the cylindrical structure cylinder of the lower electrode layer 701, so that the portion of the upper electrode layer 703 on the edge region of the core region I (i.e. the boundary region of the capacitor hole array) corresponding to the middle support layer 601 and the top support layer 602 protrudes in a direction away from the lower electrode layer 701, making the boundary of the capacitor array in the core region I uneven. In addition, in this embodiment, the capacitor dielectric layer 702 and the upper electrode layer 703 also sequentially extend to cover the surface of the bottom supporting layer 600 remaining on the peripheral region II.

Referring to fig. 11 or fig. 12, a top electrode filling layer 704 may be formed on the surface of the top electrode layer 703 by a chemical vapor deposition process, and the top electrode filling layer 704 fills the gap between the top electrode layers 703, that is, the top electrode filling layer 704 fills the gap between adjacent cylindrical structures and covers the above-formed structure. Preferably, the material of the upper electrode filling layer 704 includes undoped or boron doped polysilicon. Thereby completing the fabrication of the capacitor array.

It can be understood that, because the top surface areas of the first edge contact pad and the second edge contact pad 501b are larger, a sufficient process margin can be provided for manufacturing the capacitor 705b, and the width of the capacitor hole corresponding to the capacitor 705b is larger, so as to prevent the capacitor hole corresponding to the capacitor 705b from being abnormally deformed or collapsed, and meanwhile, the capacitor 705b and the corresponding first edge contact pad or second edge contact pad 501b have larger contact areas, thereby reducing contact resistance and facilitating improvement of electrical performance of the device. In addition, because the width of the capacitor hole corresponding to the capacitor 705b is relatively large, the density difference of the circuit patterns in the peripheral region II and the core region I can be buffered, so that the optical proximity effect can be improved when the photolithography process and/or the etching process of the capacitor hole is performed, the sparse/dense load effect of the circuit patterns in the peripheral region II and the core region I is reduced, the capacitor hole in the core region I is protected, the consistency between the capacitor hole within the boundary of the core region and the capacitor filled in the capacitor hole of the core region is ensured, and the problem that the capacitor hole above the main contact pad in the core region is abnormal to cause the failure of a subsequently formed capacitor structure is prevented.

It should be noted that, in the present specification, the embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other. Moreover, the above description is only for the description of the preferred embodiments of the present invention, and not for any limitation of the scope of the present invention, and any modification and modification made by those skilled in the art according to the above disclosure all belong to the protection scope claimed in the technical solution of the present invention.

In addition, it should be further noted that the terms "first", "second", third "and the like in the description are used for distinguishing various components, elements, steps and the like in the description, and are not used for indicating a logical relationship or a sequential relationship between the various components, elements, steps and the like unless otherwise specified or indicated.

Claims

1. A contact pad layout of a semiconductor device, the contact pad layout comprising:

2. A contact pad layout as claimed in claim 1, wherein a strip having a jagged edge is provided in the first edge layout region as the first edge contact pad pattern.

3. The contact pad layout of claim 2, wherein the serrated edge faces the master layout region, each of the serrations of the serrated edge being arranged in alignment with a corresponding master contact pad pattern in the master layout region.

4. The contact pad layout of claim 1, wherein a plurality of first edge contact pad patterns are disposed in the first edge layout area in two rows in a direction of the one edge of the main layout area, and each of the first edge contact pad patterns is aligned with a corresponding main contact pad pattern in the main layout area, and a distance between a row of first edge contact pad patterns closest to the main layout area and a nearest row of main contact pad patterns is the first edge distance.

5. The contact pad layout of claim 1, wherein the contact pad layout further comprises a second edge layout region, the second edge layout region is distributed outside an adjacent side of the one side of the main layout region, a plurality of second edge contact pad patterns are disposed in the second edge layout region, an area of each second edge contact pad pattern is larger than an area of each main contact pad pattern, and a second edge distance is provided between the second edge layout region and the main layout region;

wherein the second edge contact pad pattern is different from the first edge contact pad pattern, and the second edge pitch is different from the fourth pitch.

6. A touch pad layout according to claim 5, wherein said second edge spacing is different from said first edge spacing.

7. The touch pad layout of claim 5, wherein each of the second edge touch pad patterns in the second edge layout regions is not identical.

8. The contact pad layout of claim 5, wherein each of the second edge contact pad patterns in the second edge layout region is aligned with a corresponding primary contact pad pattern in the main layout region.

9. The contact pad layout of claim 8, wherein the second edge layout region includes second edge contact pad patterns arranged in two columns in the direction of the adjacent edge, and a distance between a column of the second edge contact pad patterns nearest to the main layout region and a column of the main contact pad patterns nearest to the main layout region is the second edge distance, and a third distance is provided between the two columns of the second edge contact pad patterns, and the third distance is greater than the second edge distance.

10. The contact pad layout of claim 9, wherein the shape of the second edge contact pad pattern in a column of the second edge layout area away from the main layout area comprises at least two of a bar shape, a U shape laid down to the left, a U shape laid down to the right, an L shape laid down to the left, an L shape laid down to the right, and a comb shape having at least two comb teeth.

11. A contact pad structure formed using the contact pad layout of the semiconductor device according to any one of claims 1 to 10, comprising:

12. The contact pad structure of claim 11 wherein said first edge contact pad is an elongated strip having a serrated edge.

13. The contact pad structure of claim 12, wherein the serrated edge is disposed facing the primary contact pad, each serration in the serrated edge being aligned with a respective primary contact pad.

14. The contact pad structure of claim 11, wherein the first edge contact pads are plural in number and arranged in two rows along the direction of the one edge of the main contact pad arrangement region, each of the first edge contact pads is arranged in alignment with a corresponding main contact pad, and a distance between a row of first edge contact pads closest to the main contact pad arrangement region and a nearest row of main contact pads is the first edge spacing.

15. The contact pad structure of claim 11, further comprising: a plurality of second edge contact pads distributed outside an adjacent one of the one sides of all the main contact pad arrangement regions, wherein a top surface area of each of the second edge contact pads is larger than a top surface area of each of the main contact pads, and a second edge distance is provided between the second edge contact pad next to the main contact pad and the main contact pad;

wherein the second edge contact pad has a shape different from the shape of the first edge contact pad, and the second edge spacing is different from the fourth spacing.

16. The contact pad structure of claim 15, wherein each of the second edge contact pads is aligned with a corresponding primary contact pad.

17. The contact pad structure of claim 16, wherein all of the second edge contact pads are arranged in two columns along the direction of the adjacent side, and the second edge contact pad in one column nearest to the main contact pad arrangement region is spaced from the main contact pad in the other column by the second edge spacing, and two columns of the second edge contact pads have a third spacing therebetween, the third spacing being greater than the second edge spacing.

18. The contact pad structure of claim 17, wherein the cross-sectional shape of the second edge contact pads in a column of all of the second edge contact pads away from the main contact pad arrangement area includes at least two of a bar shape, a left-falling U shape, a right-falling U shape, a left-falling L shape, a right-falling L shape, and a comb shape having at least two comb teeth.

19. A semiconductor device, comprising:

the interlayer dielectric layer covers the semiconductor substrate;

the contact pad structure of the semiconductor device according to any one of claims 11 to 18, formed in the interlayer dielectric layer;

20. A mask assembly for fabricating a contact pad structure of a semiconductor device according to any one of claims 11 to 18, comprising:

21. The mask blank combination of claim 20, wherein the first mask blank has at least two first lines at ends that are connected together at one side of the first mask blank.

22. The mask assembly of claim 20, wherein when the second mask and the first mask are aligned and overlapped, the tail ends of all the second lines except for the outermost first second line of the second mask do not exceed the outermost first line of the first mask; the first second line on the outermost side of the second mask plate exposes the tail end of at least one first line.

23. The mask blank combination of claim 20, wherein in the second mask blank, the line width of the end of the other second line is greater than the line width of the middle region of the other second line.