CN210778544U - Mask plate combination and semiconductor device - Google Patents

Abstract

The utility model provides a mask blank combination, semiconductor device, through the utility model provides a mask blank combination, define the formation position of contact plug, so that the top of the partial active area of nuclear core region boundary department does not have contact plug, and the top of the active area of other active areas of nuclear core region boundary department and the inside active area of nuclear core region all has contact plug, therefore, follow-up existing technology of adopting again forms corresponding electrical structure in the inside of nuclear core region and boundary department, make the partial electrical structure of nuclear core region boundary department not become virtual structure because of its below with the contact plug of active area contact, the semiconductor device that can avoid making out leads to the problem that can not pass through relevant test because of the electrical structure's of nuclear core region boundary department problem, the performance and the qualification rate of the semiconductor device who makes have then been improved.

Description

Mask plate combination and semiconductor device

Technical Field

The utility model relates to the field of semiconductor technology, in particular to mask plate combination, semiconductor device.

Background

Various techniques have been used to integrate more circuit patterns in a limited area of a semiconductor substrate or wafer. Due to the difference in the pitches of circuit patterns, an integrated circuit is generally divided into a device Dense region (Dense), a device sparse region (ISO), and a device isolated region, where the device Dense region is a region with a higher device density (i.e., devices are denser), the device sparse region is a region with a lower device density (i.e., devices are sparser), and the device isolated region is a region where the relatively sparse region and the Dense region are separately arranged. As the critical dimension of semiconductor devices is continuously reduced, the density of circuit patterns and/or the height of the devices is continuously increased, which is influenced by the resolution limit of an exposure tool (optical exposure tool) and the effect of density difference between a device dense region and a device sparse region (i.e., the dense/sparse effect of circuit patterns), and the difficulty in performing a photolithography process and/or an etching process is also increased (e.g., the process margin is reduced), thereby causing the performance of the manufactured semiconductor devices to be affected.

For example, in the case of a Dynamic Random Access Memory (DRAM) device, a large number of memory cells (memory cells) are grouped to form an array memory area, and a peripheral circuit area is present beside the array memory area, where the peripheral circuit area includes other transistor elements, contact structures, and the like, the array memory area is used as a device dense area of the DRAM for storing data, and the peripheral circuit area is used as a device sparse area of the DRAM for providing input and output signals and the like required by the array memory area. Each memory cell in the array memory region may be formed by a Metal Oxide Semiconductor (MOS) transistor and a capacitor (capacitor) structure connected in series. Wherein a capacitor is located within the array storage region, wherein the capacitor is stacked over a bit line and electrically coupled to a corresponding storage node contact of the capacitor, the storage node contact being electrically coupled to an active region therebelow. With the continuous development of semiconductor technology, the critical dimension of devices is continuously decreasing, the gap between memory cells of a DRAM device becomes narrower, when a storage node Contact is formed through a Self Aligned Contact (SAC) process, due to the resolution limit of an exposure tool (optical exposure tool 1) and the effect of density difference between a device dense region and a device sparse region, after a capacitor is connected to a Contact plug of an array storage region, the problem of capacitor collapse or partial failure at the boundary of the array storage region is easy to occur, which affects the performance of the manufactured DRAM device, and there is a high possibility that the manufactured DRAM device cannot pass through related tests, thereby reducing the yield of the manufactured DRAM device.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a mask plate combination, semiconductor device to can improve the performance and the qualification rate of the semiconductor device of manufacturing.

In order to solve the technical problem, the utility model provides a mask plate combination for make contact plug, the mask plate combination includes:

the first mask plate is provided with a plurality of parallel first shading stripes, and a first light-transmitting area is arranged between every two adjacent first shading stripes;

the second mask plate is provided with a plurality of second light shading stripes which are parallel and intersected with each first stripe, and a second light transmitting area is arranged between every two adjacent second light shading stripes;

and the third mask plate is provided with a shading block and a third light transmission area which is complementary with the shading block, the shading block covers at least one first shading stripe at the boundary of the first mask plate and a part of the first light transmission area nearest to the first shading stripe, at least two second shading stripes at the boundary of the second mask plate and a part of the second light transmission area between the two second shading stripes are covered, and the overlapping area of the third light transmission area, the first light transmission area and the second light transmission area is an area for forming a contact plug.

Based on same utility model the design, the utility model discloses still provide an adopt the mask plate combination semiconductor device of making, include:

a semiconductor substrate having a core region formed therein, the core region having therein active regions of a plurality of core elements;

the interlayer dielectric layer is formed on the semiconductor substrate;

a plurality of contact plugs formed in the interlayer dielectric layer and contacting the active regions of the corresponding core elements;

wherein no contact plug is over a portion of the active region at the core region boundary.

Compared with the prior art, the technical scheme of the utility model following beneficial effect has:

through the utility model provides a mask plate combination, define the position of formation of contact plug, so that the top of the partial active area of nuclear core region boundary department does not have the contact plug, and the top of the active area of other active areas of nuclear core region boundary department and the inside active area of nuclear core region all has the contact plug, therefore, follow-up existing technology of adopting again is when the inside of nuclear core region and boundary department form corresponding electrical structure, make the partial electrical structure of nuclear core region boundary department not become virtual structure because of its below with the contact plug of active area contact, the semiconductor device that can avoid making leads to the problem that can not pass through relevant test because of the problem of the electrical structure of nuclear core region boundary department, the performance and the qualification rate of the semiconductor device who makes have then improved.

Drawings

Fig. 1 is a schematic structural diagram of a first mask plate according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of a second mask plate according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram of a first mask plate according to an embodiment of the present invention;

fig. 4A is a schematic structural diagram of the first mask plate and the active region of the core region after pattern alignment overlay according to an embodiment of the present invention (where some layers affecting the observation of the pattern alignment overlay effect are omitted);

fig. 4B is a schematic diagram of the structure after pattern alignment and overlay of the second mask plate, the first mask plate and the active region of the core region according to the embodiment of the present invention (in which some layers affecting the observation of the pattern alignment and overlay effect are omitted);

fig. 4C is a schematic structural diagram of the third mask plate, the second mask plate, the first mask plate and the core region after pattern alignment and superposition of the active regions according to the embodiment of the present invention (in which some layers that affect the observation of the pattern alignment and superposition effect are omitted);

fig. 5 is a schematic diagram of the distribution of contact plugs fabricated on the core region using the mask plate combination according to the embodiment of the present invention, wherein there is no contact plug above the portion of the active region at the boundary of the core region;

fig. 6 is a schematic cross-sectional view of an embodiment of the present invention at the boundary of the core region and along line aa' in fig. 5;

fig. 7 is a schematic cross-sectional view of a semiconductor device at a core region boundary according to an embodiment of the present invention.

Detailed Description

The memory and the forming method thereof proposed by the present invention will be further described in detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in simplified form and are not to precise scale, and are provided for convenience and clarity in order to facilitate the description of the embodiments of the present invention.

Referring to fig. 1 to 3, an embodiment of the present invention provides a mask plate assembly for manufacturing a contact plug, the mask plate assembly including: a first mask plate 10, a second mask plate 20, and a third mask plate 30.

Referring to fig. 1, the first mask plate 10 has a plurality of parallel first light-shielding stripes, and a first light-transmitting area 102 is between two adjacent first light-shielding stripes. In this embodiment, the first light-shielding stripe 101a at the boundary of the first mask plate 10 (i.e., at the boundary extending along the length of the first light-shielding stripe) has a first width W1, the second light-shielding stripe 101b has a width smaller than W1, the remaining first light-shielding stripes 101c have a second width W2, the first width W1 is greater than the second width W2, for example, W1>1.5 × W2, and the width of the second first light-shielding stripe 101b is larger than W2, thereby, in the photoetching and etching process of transferring the pattern on the first mask plate 10 to the corresponding film layer, the width of the first light-shielding pattern 101a, the second first light-shielding pattern 101b, and the remaining first light-shielding patterns 101c in the first mask blank 10 may be gradually varied to improve the pattern density/sparseness effect between the core region and the peripheral region of the semiconductor device, thereby improving the pattern transfer effect of the first mask blank 10. In other embodiments of the present invention, the width of the second first light-shielding stripe 101b may be equal to that of the first light-shielding stripe 101 a. In addition, optionally, the width of the first light-transmitting region 102 between the first light-shielding stripe 101a and the second light-shielding stripe 101b is greater than the width of the remaining first light-transmitting region 102, thereby being beneficial to providing sufficient process margin for the fabrication of the contact plug at the boundary of the core region of the semiconductor device.

Referring to fig. 2, the second mask plate 20 has a plurality of second light-shielding stripes 201 parallel to and perpendicularly intersecting each of the first stripes 101a, 101b, and 101c, and a second light-transmitting area 202 is between two adjacent second light-shielding stripes 201. The width of the second light-blocking stripes 201 shown in fig. 2 is substantially the same, but in other embodiments of the invention, optionally, at least one second shading stripe (not shown) at the boundary of the second mask plate 20 (i.e. at the boundary extending along the length of the second shading stripe) has a third width (not shown), the remaining second light-shielding stripes have a fourth width (not shown), which is greater than the fourth width, e.g. the third width is greater than 1.5 times the fourth width, thereby, in the photoetching and etching process for transferring the patterns on the second mask plate 20 to the corresponding film layers, the width gradient of the second light-shielding stripes in the second mask plate 20 can be utilized to improve the pattern density/sparsity effect between the core region and the peripheral region of the semiconductor device, and improve the pattern transfer effect of the second mask plate 20. In other embodiments of the present invention, optionally, the width of the second light-transmitting region 202 between the first second light-shielding stripe and the second light-shielding stripe at the boundary of the second mask plate 20 (i.e. at the boundary extending along the length of the first light-shielding stripe) is greater than the width of the rest of the second light-transmitting regions 202, thereby being beneficial to provide sufficient process margin for the fabrication of the contact plug at the boundary of the core region of the semiconductor device.

Referring to fig. 3, the third mask plate 30 has a light shielding block 301 and a third light-transmitting region 302 complementary to the light shielding block 301. The light shielding block 301 may have a serrated edge facing the core region for masking a portion of the region at the boundary of the core region where the contact hole is to be formed.

It should be noted that fig. 1 to 3 respectively show only the patterns of one corner area of the first mask plate 10, the second mask plate 20 and the third mask plate 30, and those skilled in the art should be able to correspondingly extend the areas shown in fig. 1 to 3 to obtain a complete mask plate with a substantially rectangular shape. In addition, the light shielding block 301 is in a closed ring structure or a non-closed ring structure with at least one opening on the complete third mask plate 30, the jagged edges of the light shielding block 301 facing the center of the third mask plate 30 are asymmetric, that is, the light shielding blocks 301 on the upper side and the lower side of the third mask plate 30 are asymmetric, and the light shielding blocks 301 on the left side and the right side of the third mask plate 30 are asymmetric.

Referring to fig. 4C and fig. 5, when the mask set of the present embodiment is used to fabricate a contact plug on a semiconductor substrate having a core region I, a boundary region III and a peripheral region II, the light shielding block 301 covers at least one first light shielding stripe at the boundary of the first mask plate 10 and a portion of the first light transmitting region nearest to the first light shielding stripe, and covers at least two second light shielding stripes 201 at the boundary of the second mask plate 20 and a portion of the second light transmitting region 202 between the two second light shielding stripes. And, the overlapping regions of the third light-transmitting region 302, the first light-transmitting region 102, the second light-transmitting region 202 and the core region I are regions CT where contact plugs are formed. Optionally, the shape of the region CT of the contact plug formed includes at least one of a square, a circle, an ellipse, a triangle, a rectangle, a polygon and a heart according to the shape of the first light-shielding stripe and the shape of the second light-shielding stripe.

In addition, in order to take account of the device density, performance, yield and the like as much as possible, the number of the second light shielding stripes 201 covered by the light shielding block 301 is 2-5 times that of the first light shielding stripes covered by the light shielding block 301.

Referring to fig. 1 to 3, fig. 4A to 4C and fig. 5 to 6, an embodiment of the present invention further provides a method for manufacturing a contact plug, wherein the method for manufacturing a contact plug is implemented by using the mask plate assembly of the present invention, and specifically includes the following steps:

first, referring to fig. 4A and fig. 6, a semiconductor substrate 400 having a plurality of active regions AA1 is provided, and an interlayer dielectric layer 500 and a first mask layer P1 are sequentially formed on the semiconductor substrate 400, wherein the semiconductor substrate 400 further has a core region I, a peripheral region II, and an interface region III between the core region I and the peripheral region II, a shallow trench isolation structure 400b defining each active region AA1 is formed in the core region I, a shallow trench isolation structure 400a defining the core region I and the peripheral region II is formed in the interface region II, and the first mask layer P1 may be silicon oxide, silicon nitride, silicon oxynitride, or the like.

Next, referring to fig. 1, fig. 4A and fig. 6, the pattern on the first mask plate in the mask plate assembly is transferred onto the first mask layer P1 by using a process of photolithography and etching, that is, the first mask layer P1 is patterned by using the first mask plate 10. Specifically, a bottom anti-reflection layer (not shown) and a photoresist layer (not shown) are first sequentially covered on the first mask layer P1, and the photoresist layer is exposed and developed using the first mask plate 10 to transfer the pattern on the first mask plate 10 onto the first mask layer P1, after which the bottom anti-reflection layer and the photoresist layer may be removed. A plurality of first lines are formed in the patterned first mask layer P1, wherein each first line corresponds to a corresponding first light-shielding stripe on the first mask plate 10, and a trench (not labeled) between adjacent first lines corresponds to a corresponding first light-transmitting region 102 on the first mask plate 10 and exposes a corresponding interlayer dielectric layer 500. Specifically, for example, the outermost first stripe P11 at the boundary of the core area I (i.e., at the boundary of the core area I extending in the length direction of the first stripe) corresponds to the first light-shielding stripe 101a at the boundary of the first mask blank 10, the second first stripe P12 corresponds to the second first light-shielding stripe 101b at the boundary of the first mask blank 10, and the remaining first stripes P10 correspond to the remaining first light-shielding stripes 101c inside the first mask blank 10.

Then, referring to fig. 2, fig. 4B and fig. 6, a second mask layer P2 is covered on the first mask layer P1 and the interlayer dielectric layer 500, and the patterns on the second mask plate 20 in the mask plate assembly are transferred onto the second mask layer P2 by using a photolithography and etching process to form a plurality of corresponding second lines P20, that is, the second mask plate 20 is used to pattern the second mask layer P2. The specific process is substantially the same as the process for patterning the first mask layer P1 using the first mask plate, and is not described in detail herein. Each second line P20 corresponds to a corresponding second light-shielding stripe 201 on the second mask plate 20, a trench (not labeled) between adjacent second lines P20 corresponds to a corresponding second light-transmitting region 202 on the second mask plate 20, each second line P20 vertically intersects all the first lines P11, P12, P10 and covers the first lines P11, P12, P10 and corresponding portions of the trenches between the adjacent first lines in the line width region, and the trenches between the adjacent second lines P20 expose the corresponding first lines P11, P12, P10 and the interlayer dielectric layer 500 in the trenches between the adjacent first lines in the trench width region. All the first lines and the second lines overlap at this time to define grooves CTa (not labeled) arranged in a checkerboard shape. The material of the second mask layer P2 is different from the material of the first mask layer P1, so that the etching process can retain the first lines between the adjacent second lines.

Next, referring to fig. 3, fig. 4C and fig. 6, a third mask layer P3 is covered on the second mask layer P2, the first mask layer P1 and the interlayer dielectric layer 500, wherein the material of the third mask layer P3 is different from the material of the second mask layer P2 and the material of the first mask layer P1, so that the exposed first line and the second line can be retained after the third mask layer P3 is subsequently patterned, and optionally, the material of the third mask layer P3 is photoresist; and transferring the pattern on the third mask plate 30 in the mask plate combination to the third mask layer P3 by adopting a photolithography process, namely patterning the third mask layer P3 by using the third mask plate 30, wherein the remaining third mask layer P3 (i.e. the patterned third mask layer P3) corresponds to the light shielding block 301 of the third mask plate 30, and the trench CTa region (i.e. the exposed interlayer dielectric layer 500 region) jointly exposed by the remaining third mask layer P3, the remaining second mask layer P2 and the first mask layer P1 is a region in which a contact plug is to be formed. The remaining third mask layer P3 covers both trenches defined by the intersections of the first lines and the second lines in the border region III and covers the part of the trenches defined by the intersections of the first lines and the second lines outermost at the boundaries in the core region I in all directions. In addition, in this embodiment, the word line WL may overlap the second line P20, and the first lines P10 to P12 may overlap the bit line BL. Thus, the first mask plate 10 may be a bitline mask plate, and the second mask plate 20 may be a wordline mask plate.

Next, referring to fig. 4C, 5 and 6, the exposed interlayer dielectric layer 500 is etched by using the remaining third mask layer P3, the second mask layer P2 and the first mask layer P1 as masks until the active area AA1 in the semiconductor substrate 400 is exposed, so as to form a contact hole exposing the corresponding active area AA 1. In the present embodiment, due to the masking effect of the third mask layer P3, contact holes are formed in a portion of the active area AA1 at the boundary of the core area I extending along the length direction of the first line (as shown by the solid line bounding box CT on the AA 'line in fig. 5), and no contact holes are formed in another portion of the active area AA1 (as shown by the dashed line bounding box dCT on the AA' line in fig. 5).

Thereafter, referring to fig. 5 and 6, contact plugs CT are formed in the respective contact holes, and the bottom of each contact plug CT contacts the corresponding active area AA 1. As can be seen in fig. 6, there is no contact plug over the portion of the active area AA1 of the core region at the boundary along the length extension of the first or second lines, as shown at dCT in fig. 6. Furthermore, in some embodiments, the contact plugs CT at the boundaries on opposite sides of the core region I are asymmetrically distributed, for example, the contact plugs at the upper and lower boundaries of the core region I are asymmetrically distributed, and/or the contact plugs CT at the left and right boundaries of the core region I are asymmetrically distributed.

From the utility model discloses an among the contact plug manufacturing method can see out, the shape and the size of the shading piece of adjustment third mask slice, the crossing slot position of injecing of the first lines that third mask layer after can adjusting the patterning covers and second lines to reach the requirement that makes the active area top contactless plug of some special position of the border department of nuclear core region. Therefore, in the actual production process, the areas which are easy to cause problems at the boundary of the core area can be collected according to historical production data, so that the contact plugs are not formed in the areas, the electrical structures (such as capacitors or resistors and the like) connected to the original positions of the contact plugs in the areas become virtual structures, the virtual structures do not participate in the tests in subsequent tests such as yield tests, the test passing rate can be improved, and the purpose of improving the product yield is finally achieved.

Next, a semiconductor device is taken as an example of a dynamic random access memory, and how to manufacture the semiconductor device of the present invention by the above method for manufacturing a contact plug is described in detail with reference to fig. 1 to 3, fig. 4A to 4C, and fig. 5 and 7. Namely, the utility model discloses a manufacturing method of semiconductor device specifically includes following process:

first, referring to fig. 4A and fig. 7, a semiconductor substrate 400 having a plurality of core devices (i.e., memory transistors) is provided, which includes the following steps: first, a semiconductor substrate 400a including a core region I, a peripheral region II and a junction region III is provided. In this embodiment, the core region I is a storage region, the core element to be formed on the core region I includes a selection element, a data storage element is connected to the core element, the selection element is, for example, a MOS transistor or a diode, and the data storage element is, for example, a capacitor, a variable resistor, or the likeA selection element and a corresponding data storage element constitute a memory cell. Peripheral circuitry (e.g., NMOS and PMOS transistors, diodes, or resistors) may be formed in the peripheral region II to control the memory cells. A plurality of shallow trench isolation structures 401b are formed in the semiconductor substrate 400a in the core region I, a shallow trench isolation structure 401a is formed in the semiconductor substrate 400a in the boundary region III, the shallow trench isolation structure 401a defines a boundary between the core region I and the peripheral region II on a two-dimensional plane, and the shallow trench isolation structure 401b defines an active region AA1 corresponding to each core element in the core region I. The active areas AA1 are distributed in a stripe shape on a two-dimensional plane and extend along a first direction, and the active areas AA1 may be arranged in a staggered arrangement on the surface of the semiconductor substrate 400 a. Then, the embedded word lines WL are formed in the semiconductor substrate 400a, and the embedded word lines WL are typically embedded at a predetermined depth in the semiconductor substrate 400a, extend along a second direction (i.e., the row direction) and pass through the shallow trench isolation structure 401b and the active area AA1, and the second direction is not perpendicular to the first direction of the active area AA 1. The buried word line WL serves as a gate to control the switching of the memory cell, and is usually surrounded by a gate dielectric layer (not shown) at the sidewall and bottom, and the top of the buried word line WL is buried by the gate cap layer 402. Since the embedded word line WL is not the focus of the present invention, the related fabrication process can refer to the known technical solutions in the art, and will not be described in detail herein. In addition, the gate dielectric layer may include silicon oxide or other suitable dielectric materials, the buried word line WL may include aluminum, tungsten, copper, titanium-aluminum alloy, polysilicon or other suitable conductive materials, and the gate cap layer 402 may include silicon nitride, silicon oxynitride, silicon carbide nitride or other suitable insulating materials. Furthermore, a second type dopant, such as a P-type or N-type dopant, may be doped into the active regions AA1 on both sides of the buried word line WL to form a source region and a drain region (collectively defined as S/D), one of the AA1 on both sides of the buried word line WL is located at a position corresponding to a predetermined bit line contact structure at the center of AA1, and the other is located at a position corresponding to a predetermined storage node contact structure at the end of the active region AA 1. The word lines WL and S/D may constitute or define a plurality of MOS memories formed on a core region I of the semiconductor deviceA transistor. In addition, source and drain regions (not shown) corresponding to the peripheral transistors may be formed in the peripheral region II together with the S/D. After the S/D is formed, an etch stop layer 403 may be further formed on the semiconductor substrate 400a, the etch stop layer 303 covers the S/D and the shallow trench isolation structures 401a and 401b, and the material thereof includes, for example, silicon nitride (SiN) and/or silicon oxide (SiO)₂) And the like. Then, a plurality of bit line contacts (not shown) and bit lines BL located above the bit line contacts are formed on the S/ds of the core region I serving as the drain regions, and the bit line contacts may be formed by first etching the S/ds between two adjacent WLs formed in one active region AA1 to form a recess, and then forming a metal silicide in the recess. The bit lines BL are parallel to each other and extend along a third direction (i.e., a column direction) perpendicular to the buried word lines WL, and simultaneously cross the active regions AA1 and the buried word lines WL. Each bit line BL includes, for example, a semiconductor layer (e.g., polysilicon, not shown), a barrier layer (e.g., comprising Ti or TiN, not shown), a metal layer (e.g., tungsten, aluminum, or copper, not shown), and a mask layer (e.g., comprising silicon oxide, silicon nitride, or silicon carbonitride, not shown) stacked in sequence.

Then, referring to fig. 4A and 7, after providing a semiconductor substrate 400 having bit lines BL, source and drain regions S/D of core devices, an interlayer dielectric layer 500 is formed on the semiconductor substrate 400, wherein the interlayer dielectric layer may be made of silicon oxide, silicon nitride, or low-K dielectric. Specifically, the interlayer dielectric layer 500 is first completely covered on the semiconductor substrate 400 through a deposition process, the interlayer dielectric layer 500 is made to fill the space between the bit lines BL and bury the bit lines BL therein, and then the interlayer dielectric layer 500 is planarized through a chemical mechanical polishing process or the like, so that the interlayer dielectric layer 500 having a flat top surface as a whole is formed. Wherein the top surface of the planarized interlayer dielectric layer 500 is at least higher than the top surface of each bit line BL.

Next, referring to fig. 1 to 3, 4A to 4C, 5 and 7, a first mask layer P1 having a pattern of the first mask blank 10, a second mask layer P2 having a pattern of the second mask blank 10 and a third mask layer P3 having a pattern of the third mask blank 30 are sequentially formed on the interlayer dielectric layer 500 by the above-mentioned method for manufacturing a contact plug. The second mask layer P2 is formed on the first mask layer P1 and the exposed interlayer dielectric layer 500, the third mask layer P3 is formed on the second mask layer P2 and the exposed first mask layer P1 and the exposed interlayer dielectric layer 500, a first line in the first mask layer P1 and a second line in the second mask layer P2 vertically intersect to define grooves arranged in a checkerboard shape, and the third mask layer P3 masks all the grooves in the boundary region III and a part of the grooves at the boundary of the core region I to define the position of each effective storage node contact structure.

Then, with reference to fig. 4C, fig. 5 and fig. 7, the third mask layer P3, the second mask layer P2 and the first mask layer P1 are used as masks to anisotropically etch the interlayer dielectric layer 500 to form contact holes penetrating the interlayer dielectric layer 500 and exposing the corresponding underlying S/D used as source regions, and at this time, contact holes (not shown) exposing the corresponding regions in the peripheral region II can be formed at the same time. The size of the contact hole at the boundary of the core region I may be larger than the size of the contact hole inside the core region I. In other embodiments of the present invention, the contact hole may also be formed in the area of the border of the interface region III near the core region I, and the contact plug in the contact hole in the subsequent interface region III may be connected together with the top of the corresponding contact plug at the border of the core region I.

Continuing with fig. 5 and 7, after forming the contact holes, an ashing process or a wet clean or other suitable process may be performed, to remove the third mask layer P3, the second mask layer P2 and the first mask layer P1 over the interlayer dielectric layer 500, and sequentially filling a barrier metal layer (not shown) and a conductive metal layer (not shown) in each contact hole, the barrier metal layer may cover the inner wall of the contact hole and the top surface of the interlayer dielectric layer 500 with a uniform thickness, the barrier metal layer may reduce or prevent the metal material disposed in the contact hole from being diffused into the interlayer dielectric layer 500, it may be formed of Ta, TaN, TaSiN, Ti N, TiSiN, W, WN, or any combination thereof, may be formed using processes such as Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), or Physical Vapor Deposition (PVD) (e.g., sputtering); the conductive metal layer may be formed from refractory metal(s) (e.g., cobalt, iron, nickel, tungsten, and/or molybdenum). In addition, the conductive metal layer may be formed using a deposition process having good step coverage properties, for example, using Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), or Physical Vapor Deposition (PVD) (e.g., sputtering). The formed conductive metal layer also covers the surface of the interlayer dielectric layer 500 around the contact hole, and then a Chemical Mechanical Polishing (CMP) process may be used to perform CMP on the top surface of the deposited conductive metal layer until the top surface of the interlayer dielectric layer 500 is exposed, so as to form a contact plug CT located in the interlayer dielectric layer 500. Fig. 7 shows a portion of the active area AA1 at the boundary of the core I without contact plugs (for these locations contact plugs would be formed in the prior art but not in the present invention, i.e., for comparison with the dashed box column dCT in fig. 7), and another portion of the active area AA1 with contact plugs CT. The contact plug CT serves as a storage node contact structure in the core region I for connection with a capacitor subsequently formed over the core region I.

Thereafter, with reference to fig. 7, a corresponding capacitor can be formed on the core region I by a conventional capacitor forming method in the art, and the detailed process is not described herein. A capacitor 705 is formed above each S/D of the core region I, at the boundary of the core region I, the capacitor 705, the bottom of which is electrically connected to the corresponding S/D through the corresponding contact plug CT, is an effective capacitor and subsequently participates in the test and the device operation, and the capacitor, between the bottom and the corresponding S/D, without the contact plug CT is a dummy capacitor and subsequently does not participate in the device related test and the device operation, thereby improving the yield of the product. In this embodiment, each capacitor 705 includes a lower electrode layer 701, a capacitance dielectric layer 702, and an upper electrode layer 703, and a bottom support layer 600, a middle support layer 601, and a top support layer 602 are stacked between the capacitors 705 in a laterally supported and spaced manner, where the bottom support layer 600 is used for bottom support of a subsequently formed lower electrode layer, and is also used for isolating internal elements of the semiconductor substrate 400 from elements such as capacitors above. The formation process of the bottom supporting layer 600 may also be a thermal oxidation process. The material of the bottom support layer 600, the middle support layer 601 and the top support layer 602 includes, but is not limited to, silicon nitride. In other embodiments of the present invention, in order to better support the lower electrode layer, more than two intermediate support layers 601 may be stacked between the bottom support layer 600 and the top support layer 602. Alternatively, all of the capacitors 705 may be in a hexagonal close-packed arrangement. Further, the lower electrode layer 701 has a cylindrical structure, and may be a polysilicon electrode or a metal electrode. When the lower electrode layer 701 is a metal electrode, a stacked structure of titanium nitride (TiN) and Ti may also be employed. When the lower electrode layer 701 is a polysilicon electrode, it may be formed using a polysilicon material that is zero-doped and/or doped. The capacitance dielectric layer 702 covers the inner surface and the outer surface of the cylindrical structure of the lower electrode layer 701, so that two opposite surfaces of the lower electrode layer 701 are fully utilized to form a capacitor with a large electrode surface area. Preferably, the capacitor dielectric layer 702 may be a high-K dielectric layer such as a metal oxide. Further, the capacitor dielectric layer 702 has a multi-layer structure, such as a two-layer structure of haar-zirconia. The upper electrode layer 703 may have a single-layer structure or a multi-layer structure, and when the upper electrode layer 703 has a single-layer structure, it may be, for example, a polysilicon electrode or a metal electrode, and when the upper electrode layer 703 is a metal electrode, it may be formed, for example, by titanium nitride (TiN). The upper electrode layer 703 can constitute a capacitor with the capacitor dielectric layer 702 and the lower electrode layer 701 both inside the cylindrical structure and outside the cylindrical structure. In addition, in the edge region of the core region I (i.e. the boundary region of the capacitor hole array), due to the existence of the lateral support layers (i.e. the middle support layer 601 and the top support layer 602), the capacitor dielectric layer 702 and the upper electrode layer 703 both have uneven-profile sidewall structures corresponding to the middle support layer 601 and the top support layer 602 outside the cylindrical structure cylinder of the lower electrode layer 701, so that the portion of the upper electrode layer 703 on the edge region of the core region I (i.e. the boundary region of the capacitor hole array) corresponding to the middle support layer 601 and the top support layer 602 protrudes in a direction away from the lower electrode layer 701, making the boundary of the capacitor array in the core region I uneven. In addition, in this embodiment, the capacitor dielectric layer 702 and the upper electrode layer 703 sequentially extend to cover the surface of the bottom supporting layer 600 remaining on the peripheral region II, and in addition, an upper electrode filling layer 704 covers the surface of the upper electrode layer 703, and the upper electrode filling layer 704 fills the gap between the upper electrode layers 703, that is, the upper electrode filling layer 704 fills the gap between adjacent tubular structures and covers the above-formed structure. Preferably, the material of the upper electrode filling layer 704 includes undoped or boron doped polysilicon.

Referring to fig. 7, the present invention also provides a semiconductor device manufactured by the above method, including: a semiconductor substrate 400, an interlayer dielectric layer 500, and a plurality of contact plugs CT. The semiconductor substrate 400 has a core area I, a peripheral area II and a boundary area III between the core area I and the peripheral area II, the core area I is formed with a shallow trench isolation structure 400b defining each active area AA1, and the boundary area II is formed with a shallow trench isolation structure 400a defining the core area I and the peripheral area II. An interlevel dielectric layer 500, which may be silicon dioxide, silicon nitride, or a low-K dielectric (dielectric constant K less than 3), is formed on the semiconductor substrate 400. A plurality of contact plugs CT are formed in the interlayer dielectric layer 500 and contact the active regions AA1 of the corresponding core devices. Wherein there is no contact plug over a portion of the active area AA1 at the boundary of the core area I. Furthermore, in some embodiments, the contact plugs CT at the boundaries on opposite sides of the core region I are asymmetrically distributed, for example, the contact plugs at the upper and lower boundaries of the core region I are asymmetrically distributed, and/or the contact plugs CT at the left and right boundaries of the core region I are asymmetrically distributed.

Alternatively, the semiconductor device may be a memory, which further includes a plurality of word lines WL, source and drain regions S/D, bit line contacts (not shown), and a plurality of bit lines BL (not shown). Each word line WL is a buried word line, is formed in the semiconductor substrate 400, and intersects with the active region AA 1. Source and drain regions S/D are formed in the active regions AA1 at both sides of the word line. Bit line contacts are formed on the drain regions, and each bit line is formed on a corresponding one of the bit line contacts and intersects each of the word lines. The interlayer dielectric layer 500 buries the semiconductor substrate 400, the word line WL, the source and drain regions S/D, the bit line contact portion, and the bit line therein. At the boundary of the core region I, there is no contact plug above the part of the active region between at least two outermost bit lines BL, and/or (alternatively, or both) there is no contact plug above the part of the active region between at least two word lines WL.

To sum up, the technical scheme of the utility model, through the utility model provides a mask plate combination, define the formation position of contact plug, so that the top of the partial active area of nuclear core region boundary department does not have contact plug, and the top of the active area of other active areas of nuclear core region boundary department and the inside active area of nuclear core region all has contact plug, therefore, follow-up existing technology of adopting again when the inside of nuclear core region and boundary department form corresponding electrical structure, make the partial electrical structure of nuclear core region boundary department not become virtual structure because of its below with the contact plug of active area contact, the semiconductor device that can avoid making out leads to the problem that can not pass through relevant test because of the electrical structure's of nuclear core region boundary department problem, the performance and the qualification rate of the semiconductor device who makes have improved then.

It should be noted that, in the present specification, the embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other. Moreover, the above description is only for the description of the preferred embodiments of the present invention, and not for any limitation of the scope of the present invention, and any modification and modification made by those skilled in the art according to the above disclosure all belong to the protection scope claimed in the technical solution of the present invention.

In addition, it should be further noted that the terms "first", "second", third "and the like in the description are used for distinguishing various components, elements, steps and the like in the description, and are not used for indicating a logical relationship or a sequential relationship between the various components, elements, steps and the like unless otherwise specified or indicated. The term "and/or" as used herein means either or both.

Claims (12)

1. A mask blank assembly for making contact plugs, the mask blank assembly comprising:

the first mask plate is provided with a plurality of parallel first shading stripes, and a first light-transmitting area is arranged between every two adjacent first shading stripes;

the second mask plate is provided with a plurality of second light shading stripes which are parallel and intersected with each first stripe, and a second light transmitting area is arranged between every two adjacent second light shading stripes;

and the third mask plate is provided with a shading block and a third light transmission area which is complementary with the shading block, the shading block covers at least one first shading stripe at the boundary of the first mask plate and a part of the first light transmission area nearest to the first shading stripe, at least two second shading stripes at the boundary of the second mask plate and a part of the second light transmission area between the two second shading stripes are covered, and the overlapping area of the third light transmission area, the first light transmission area and the second light transmission area is an area for forming a contact plug.

2. The mask assembly of claim 1, wherein the shape of the area where the contact plug is formed includes at least one of a circle, an ellipse, a polygon, and a heart.

3. The mask plate combination according to claim 1, wherein the number of the second light shielding stripes covered by the light shielding block is 2-5 times that of the first light shielding stripes covered by the light shielding block.

4. The mask assembly of claim 1, wherein at least one of the first light-shielding stripes at the boundary of the first mask has a first width, and the remaining first light-shielding stripes have a second width, the first width being greater than the second width.

5. The mask assembly of claim 4, wherein the first width is greater than 1.5 times the second width.

6. The mask assembly of claim 1, wherein at least one of the second light-shielding stripes at the boundary of the second mask has a third width, and the remaining second light-shielding stripes have a fourth width, the third width being greater than the fourth width.

7. The mask assembly of claim 6, wherein the third width is greater than 1.5 times the fourth width.

8. The reticle assembly of claim 1, wherein edges of the light blocking blocks facing the third reticle center are asymmetric.

9. A semiconductor device manufactured by using the mask blank assembly according to any one of claims 1 to 8, comprising:

a semiconductor substrate having a core region formed therein, the core region having therein active regions of a plurality of core elements;

the interlayer dielectric layer is formed on the semiconductor substrate;

a plurality of contact plugs formed in the interlayer dielectric layer and contacting the active regions of the corresponding core elements;

wherein no contact plug is over a portion of the active region at the core region boundary.

10. The semiconductor device of claim 9, wherein the contact plugs at the boundaries of the opposing sides of the core region are asymmetrically distributed.

11. The semiconductor device according to claim 9, further comprising:

a plurality of word lines formed in the semiconductor substrate and crossing the active regions;

a source region and a drain region formed in the active region at both sides of the word line;

a bit line contact formed on the drain region;

a plurality of bit lines formed on the bit line contacts, the bit lines crossing the word lines;

the interlayer dielectric layer buries the semiconductor substrate, the word line, the source region, the drain region, the bit line contact portion and the bit line.

12. The semiconductor device of claim 11, wherein at the boundary of the core region, there is no contact plug over a portion of the active region between at least two bit lines and there is no contact plug over a portion of the active region between at least two word lines.

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