JP4921981B2 - Manufacturing method of semiconductor memory cell - Google Patents

Description

Detailed Description of the Invention

  The present invention relates to a semiconductor memory cell, in particular, a semiconductor memory cell having a contact hole capacitor, and a manufacturing method thereof.

  In the future, the demand for large high density memory zones in semiconductor components will become very large. The overall occupancy on the chip surface available by such an embedded memory zone is already about 50% of the total chip surface and will further increase.

  Therefore, high density is required in the semiconductor memory cell in order to reduce the overall size of the semiconductor component by making the memory zone as small as possible. As a result, the manufacturing cost can be reduced.

  For this reason, the semiconductor industry tends to move away from conventional 6-transistor semiconductor memory cells to 1-transistor, 2-transistor, and 3-transistor (1T, 2T, 3T) semiconductor memory cells. As a result, the leakage current can be reduced, the degree of integration can be increased, the production yield can be improved, and so-called soft errors can be hardly generated.

  However, compared with the 6-transistor semiconductor memory cell, the 1-transistor, 2-transistor, and 3-transistor semiconductor memory cells require a capacitor or capacitor for storing electric charge, and the stored electric charge needs to be refreshed at a predetermined time interval. There is. Since the refresh rate of the embedded 1T, 2T, and 3T semiconductor memory cells can be considerably higher than that of a conventional dynamic random access memories (DRAM), a small storage capacitor can be used.

  1 to 3 show schematic equivalent circuit diagrams of a one-transistor, two-transistor, and three-transistor semiconductor memory cell, respectively. BL indicates a bit line, WL indicates a word line, AT indicates each selection transistor, and the storage capacitor C can be driven through each selection transistor.

  In FIG. 2, a two-transistor semiconductor memory cell is further provided with an inverted word line WL / and an inverted bit line BL /. The inverted word line WL / and the inverted bit line BL / drive the storage capacitor C via a further selection transistor AT.

In Figure 3, third storage capacitor C in the transistor semiconductor memory cell, on the other hand, written via the selection transistor AT associated with the write bit lines BL _W and the write word line WL _W, the read word line WL _R and the reading read via a respective selection transistor AT associated further bit line BL _R and another two.

  In order to manufacture such T1, T2, T3 semiconductor memory cells, for example, so-called embedded DRAM semiconductor memory cells are used.

  FIG. 4 shows a schematic cross-sectional view of a one-transistor semiconductor memory cell having a deep trench capacitor. According to FIG. 4, a deep trench for manufacturing a deep trench capacitor DTC is provided in the semiconductor substrate 10. The capacitor dielectric (CD) is formed on the trench surface and on the conductive filler layer.

  The conductive filler layer is formed as a capacitor counter electrode CE1 on the surface of the capacitor dielectric. The conductive filler layer forms a deep trench capacitor DTC together with the semiconductor substrate 10 as another capacitor electrode. A field effect transistor having a source region S and a drain region D for defining a channel in the semiconductor substrate 10 is conventionally used as the selection transistor AT.

  A gate dielectric 60 is formed on the surface of the channel, and a control electrode so-called gate G that substantially forms the word line WL is formed on the gate dielectric 60. The source region S is connected to, for example, the bit line BL in the metallization layer, for example, via the source contact portion KS or a corresponding contact. Similarly, the drain region D is connected to the deep trench capacitor DTC, that is, the capacitor counter electrode CE1 through, for example, the first metallization layer M1, the drain contact portion KD, and the capacitor contact portion KC.

  A semiconductor circuit for defining the active area AA, particularly for insulating a switching element (for example, the selection transistor AT), further includes a so-called trench isolation portion STI, and the trench isolation portion STI has, for example, an insulating lining. A layer 20 and an insulating filler layer 30 are provided.

  By using the deep trench capacitor DTC, a semiconductor memory cell that requires a very small space can be manufactured, for example, as a DRAM semiconductor memory cell. However, the manufacturing process for the deep trench capacitor DTC is particularly costly. Is extremely high.

  Therefore, in the past, the current 1T, 2T, and 3T semiconductor memory cells are actually manufactured by so-called MOS / MIM capacitors (MOS / MIMcaps), which are more cost effective for manufacturing.

  FIG. 5 shows a schematic cross-sectional view of a one-transistor semiconductor memory cell having such a MOS capacitor MOSC. The same members as the members shown in FIG. 1 or the members corresponding to the members shown in FIG. 1 are given the same member numbers below, and repeated explanations of the members are omitted.

  Accordingly, in FIG. 5, the storage capacitor is manufactured by the MOS capacitor MOSC. The semiconductor substrate 10 or the doping region formed in the semiconductor substrate 10 is used as the capacitor electrode CE2. On the surface of the capacitor electrode CE2, a capacitor dielectric CD is formed together with the capacitor counter electrode CE1. The capacitor counter electrode CE1 is formed, for example, as a polycrystalline semiconductor layer on the capacitor dielectric CD.

  Further, the capacitor counter electrode CE1 is electrically connected to the drain region D of the selection transistor AT via the capacitor contact portion KC, the drain contact portion KD, and preferably the first metallization layer M1.

  This can substantially reduce the cost, but the area required for such semiconductor memory cells has increased significantly. This is because the MOS or MIM capacitor MOSC is basically formed on the surface of the semiconductor substrate 10, and therefore the capacitance of the MOS or MIM capacitor MOSC is directly proportional to the area occupation on the available component surface. It is.

  SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor memory cell and a method for manufacturing the same that can reduce the manufacturing cost while improving the degree of integration.

  According to the invention, the object is achieved by the features of the semiconductor memory cell of claim 1 of the present application and by the features of the manufacturing method of claim 10 of the present application.

  The object is achieved in particular by using a contact hole capacitor as a storage capacitor in at least one contact hole for the source region or drain region of the select transistor. Since the capacitor is formed in the contact hole required in any case for the selection transistor, the degree of integration of the semiconductor memory cell can be substantially improved. In addition, since the sub-process of the manufacturing method for forming the required contact hole can be used at the same time for forming the contact hole capacitor, the manufacturing cost can be further reduced.

  Preferably, at least one contact hole for the contact hole capacitor is formed in an interlayer insulator formed on the semiconductor substrate, and at least a part of the source region or the drain region corresponding to the contact hole is formed. Expose.

  The counter electrode of the capacitor is formed on the surface of the contact hole, and the counter electrode does not reach the surface of the interlayer insulator, but is a lower zone in the counter electrode that is below the surface And electrically connected to the source region or the drain region.

  The capacitor insulator reaches the surface of the interlayer insulator and is formed on the counter electrode of the capacitor to form an upper region of the contact hole. Finally, a conductive filler layer for forming the capacitor electrode inside the contact hole is formed on the surface of the capacitor insulator.

  Therefore, the contact hole capacitor has a minimum space requirement, has a sufficient charging capacity, and can be manufactured by a slight modification to the conventional manufacturing method.

  Preferably, the at least one contact hole may have a columnar shape, an elliptical columnar shape, a prismatic shape, or a shape by any mask shape that can be used in a standard manufacturing method.

  In order to connect the contact hole capacitor, a capacitor connection line may be further formed on the interlayer insulator. Since such a capacitor connection line is disposed in the plane of the conventional metal layer, the electric resistance value of the capacitor connection line can be maintained at a minimum value.

  The capacitor connection line may include at least one auxiliary connection line. At least one auxiliary connection line is formed so as to be basically orthogonal to the capacitor connection line on the interlayer insulator. As described above, each capacitance can be finely adjusted to an arbitrary value for the entire contact hole capacitor.

  In particular, a plurality of contact hole capacitors may be formed for each source region or drain region of the select transistor. At least one auxiliary connection line portion may be provided for connecting the plurality of contact hole capacitors parallel to each other together. Such a capacitor may be changed or adjusted to a desired capacitance value by using, for example, a conventionally known laser beam.

  For the capacitor insulator, silicon oxide, silicon nitride and / or a so-called high-k material having a high relative dielectric constant is preferably used. As a result of its use, the desired capacity can be further increased.

  In the above manufacturing method, the selection transistor including the gate insulator and the control electrode is formed first together with the source region and the drain region. An interlayer insulator is disposed on the selection transistor. Subsequently, contact holes for at least partially exposing the source region and the drain region are formed in the interlayer insulator. Thereafter, a lining layer is formed in at least one contact hole as a counter electrode of the capacitor. However, the lining layer is formed so as not to reach the surface of the interlayer insulator.

  Next, a further insulating layer is formed as a capacitor insulator on the counter electrode of the capacitor until it reaches the surface of the interlayer insulator. Thereafter, a conductive filler layer is formed on the further insulating layer as a capacitor electrode inside the at least one contact hole for the contact hole capacitor. Subsequently, in order to connect the capacitor electrode, a capacitor connection line is formed on the interlayer insulator and the filler layer.

  Since each process for forming a conventional contact hole in the above manufacturing method can be shared with each process for forming a contact hole capacitor in the manufacturing method of the present invention, the manufacturing cost of the manufacturing method of the present invention is reduced. Extremely reduced.

  In particular, a method for forming a conductive lining layer provided by a conventional manufacturing method in both a contact hole for a contact hole capacitor and a contact hole for a remaining source region or drain region, By using simultaneously, it is possible to use each manufacturing method step or each layer manufacturing method used in the conventional contact hole manufacturing method to form the capacitor counter electrode of the contact hole capacitor of the present invention. This is an advantage.

  In addition, the auxiliary connection line portion corresponding to the capacitor connection line can be formed simultaneously with the conductive filler layer for forming the capacitor electrode. As a result, the manufacturing cost of the contact hole capacitor can be further reduced.

  Further advantageous configurations and processes of the invention are indicated in the further dependent claims.

  Hereinafter, the present invention will be described in more detail with reference to the drawings.

  1-3 are schematic equivalent circuit diagrams of prior art 1T, 2T, 3T semiconductor memory cells. FIG. 4 is a schematic cross-sectional view of a 1T semiconductor memory cell having a prior art deep trench capacitor. FIG. 5 is a schematic cross-sectional view of a 1T semiconductor memory cell having a prior art MOS capacitor.

  6A to 6C are schematic cross-sectional views showing main method steps in manufacturing the 1T semiconductor memory cell of the present invention according to the first embodiment. 7A to 7C are schematic cross-sectional views showing main method steps in manufacturing the 1T semiconductor memory cell according to the second embodiment of the present invention.

  FIG. 8 is a schematic cross-sectional view of the 1T semiconductor memory cell of the present invention according to the third embodiment. FIG. 9 is a schematic plan view of the 1T semiconductor memory cell of the present invention of FIG. FIG. 10 is a schematic plan view of the 1T semiconductor memory cell of the present invention in each of the fourth to sixth embodiments. FIG. 11 is a diagram schematically illustrating the overall capacitance as a function of the capacitor dielectric and a plurality of contact hole capacitors connected in parallel.

  6A to 6C show a schematic cross section showing the main method steps in the fabrication of a 1T semiconductor memory cell according to the first embodiment of the present invention. In the following, the members having the same reference numerals as those in FIGS. 1 to 5 are the same or corresponding members, and the repeated description thereof is omitted.

  According to FIG. 6A, first, the semiconductor substrate 1 is prepared. As the semiconductor substrate 1, it is preferable to use a Si semiconductor substrate. In such a preparation process, although not shown, in particular, a trench isolation part STI for defining the active area AA may be formed in the semiconductor substrate 1 and / or corresponding to the trench isolation part STI. Trench doping may be performed at the position to be.

  Subsequently, a selection transistor AT for selecting a semiconductor memory cell is formed on the semiconductor substrate 1. For example, the gate insulating layer 2 is formed on the entire surface of the semiconductor substrate 1, and the control electrode layer 3 is formed on the entire surface of the gate insulating layer 2. Next, a so-called gate stack including the gate insulating layer 2 and the control electrode layer 3 is patterned by, for example, a lithography method.

  Finally, the source region S and the drain region D are formed in the semiconductor substrate 1 on both sides of the gate stack in a self-aligned manner (self-alignment), for example, by an ion implantation method. In order to increase the conductivity, the control electrode layer 3 or the patterned control electrode G may be optionally salicided. A highly conductive metal semiconductor composite is formed using the deposited metal layer. For this reason, the control electrode layer 3 is preferably made of a polycrystalline semiconductor material, particularly polysilicon.

  Subsequently, a so-called layered interlayer dielectric (interlayer insulator) is formed on the surface of the semiconductor substrate 1 or the gate stacks 2 and G. For forming the interlayer dielectric, it is preferable to apply BPSG (boron / phosphorus silicate glass) to the entire surface. This BPSG layer has a predetermined standard thickness in each of the conventional methods, and the thickness of this layer already partly determines the capacitance of a contact hole capacitor to be formed in the future.

  According to FIG. 6B, contact holes are formed in the interlayer dielectric 4 for the source region S and the drain region D. The contact hole exposes the source region S and the drain region D at least partially, and forms an opening at the exposed location of the semiconductor substrate 1. In the following, regarding the contact hole, in the present embodiment, for example, one contact hole for the contact hole capacitor KK formed on the drain region D is distinguished from the other contact hole formed on the other source region S. To do. Naturally, a contact hole capacitor may be formed in the contact hole for the source region S. Ordinary contact holes may be formed in the area of the drain region D.

  Each of these contact holes is preferably formed simultaneously using a conventional standard process, in particular an anisotropic etching method, and preferably a so-called RIE method (reactive ion etching method). Thus, each contact hole for the contact hole capacitor and the remaining source region S is formed in particular at the same time, but in principle these depressions or dents are, for example, consecutive in different steps of the method It is also possible to form each of them.

  FIG. 9 is a plan view schematically illustrating such a 1T semiconductor memory cell. About the member of the same member number as FIGS. 1-6, the member which is the same or it corresponds is shown, and description of those repetition was omitted below.

  According to FIG. 9, each contact hole of different size is preferably formed in the interlayer dielectric 4 for the contact hole capacitor KK and the remaining source region S. Thereby, in particular, the capacitance of the contact hole capacitor can be increased, and the contact resistances of the source region S and the drain region D can be made substantially the same. Furthermore, in this case, in order to form the desired contact hole capacitor KK, the filling of the contact hole with the capacitor counter electrode CE1, the capacitor dielectric CD and the capacitor electrode CE2 is particularly greatly simplified.

  Returning to FIG. 6B again, subsequently, at least on the surface of the contact hole for the contact hole capacitor KK or the drain region D (that is, on the surface of the interlayer dielectric 4 on the drain region D and on the exposed surface of the semiconductor substrate 1). In addition, a conductive lining layer 5 is formed as a capacitor counter electrode CE1. In this case, for insulation reasons, it is necessary that the lining layer 5 does not extend (not reach) to the horizontal surface of the interlayer dielectric 4 in the upper zone of the contact hole.

  The lining layer 5 is preferably formed simultaneously on the surface of the remaining contact hole for the source region S or on the exposed surface of the semiconductor substrate 1 of the remaining contact hole for the source region S. This is because such a lining layer is conventionally provided in a manufacturing method for making contact vias or contact elements as a reference. Thereby, a layer corresponding to the lining layer 5 is formed on the entire surface of the wafer surface, and the above layer from the horizontal surface of the interlayer dielectric 4 is formed in order to form a desired space in the upper zone of the contact hole. Preferably, the lining layer 5 is formed by performing anisotropic etch-back on.

  For example, a TiN layer having a thickness of about 10 nm is deposited uniformly, that is, with a constant layer thickness, and etched back by the RIE etching method. As a result, the etchback occurs in the upper zone of the contact hole.

  In the manufacturing method described above, the lining layer 5 may be isotropically etched in the lower or bottom zone of the contact hole. Even if the semiconductor substrate 1 or the source region S and the drain region D are exposed, this is true. Not a disadvantage. Subsequently, a capacitor counter electrode CE1 for a contact hole capacitor is formed by the conductive lining layer 5. On the other hand, the lining layer 5 is basically formed in the remaining contact hole for the source region S in order to improve the deposition process and improve the conductivity.

  Subsequently, according to FIG. 6B, the contact holes for the remaining source region S are masked (covered) or filled with a first mask layer or a first mask MX1 (not essential), and a further dielectric layer 7 is Preferably it is deposited over the entire surface. The further dielectric layer 7 is, for example, an oxide and / or nitride layer which has a thickness of 3 to 15 nm and is preferably a so-called high-k dielectric with a high dielectric constant.

  6C, subsequently, for example, planarization to the surface of the interlayer dielectric 4 is performed, and the first mask MX1 is removed or peeled off from the remaining contact holes for the source region S. Since the capacitor dielectric CD reaches the horizontal surface of the interlayer dielectric 4, the lining layer 5, that is, the capacitor counter electrode CE1, is reliably insulated in the upper zone of the contact hole. Thus, the capacitor dielectric CD is obtained in the area of the contact hole for the contact hole capacitor or drain region D.

  According to FIG. 6C, a conductive filler layer 8 may subsequently be deposited on the surface of the interlayer dielectric 4 and in the contact holes. In that case, the contact hole is completely filled. As the filler layer 8, it is preferable to deposit a tungsten layer conventionally used in the contact hole manufacturing method on the entire surface.

  Subsequently, the conductive filler layer 8 is patterned by photolithography. As a result, the bit line BL connected to the source region S and the capacitor electrode CE2 inside the contact hole having the capacitor connection line Vss corresponding to the bit line BL can be formed in one manufacturing process.

  However, instead of patterning, it is possible in principle to further planarize until the surface of the interlayer dielectric 4 is reached. The bit line BL and the capacitor connection line for connecting the capacitor electrode CE are formed in a subsequent metallization process by a conventional method.

  FIG. 7A to FIG. 7C show further schematic cross-sectional views for explaining main processes in the method of manufacturing the one-transistor semiconductor memory cell according to the second embodiment of the present invention. The members having the same member numbers as those in FIGS. 1 to 6 indicate the same or corresponding members, and the repetitive description is omitted below. FIG. 7A shows a cross-sectional view after the preparation step according to FIG. 6A, for example as an alternative to the first embodiment.

  In the second embodiment, as in the first embodiment, the contact hole and the lining layer 5 are first formed. Subsequently, a contact hole for a future contact hole capacitor is covered or filled with a first mask MX10 (not essential). Subsequently, the contact holes for the source region S are filled with the conductive second filler layer 6 (for example, tungsten), thereby completing the contact element for the source region S. For example, a second filler layer may also be deposited over the entire surface and subsequently planarized.

  After the planarization, a part of the first mask MX10 remaining in the contact hole for the contact hole capacitor is also removed or removed, and a second mask layer MX20 is formed on the surface of the interlayer dielectric 4. As a result, only the contact hole zone for the contact hole capacitor or drain region D remains exposed. Subsequently, similarly, a dielectric layer 7 that finally becomes the capacitor dielectric CD and a conductive first filler layer 8 (for example, W) are deposited on the entire surface. A cross-sectional view of such is shown in FIG. 7B.

  In the step and the intermediate shown in FIG. 7C, similarly, planarization to the surface of the interlayer dielectric 4 may be arbitrarily performed. Subsequently, the bit line BL and the capacitor connection line Vss are respectively formed on the surfaces of the conductive first filler layer 8, that is, the capacitor electrode, and the conductive second filler layer 6.

  However, in order to manufacture the capacitor electrode CE2 in the contact hole for the contact hole capacitor, the capacitor connection line Vss is preferably formed integrally with the conductive first filler layer 8. The bit line BL is formed in a subsequent method step. The bit line BL may further be formed simultaneously with the capacitor connection line Vss and the capacitor electrode CE2 or a filler layer for the contact hole. In this case, a recess for the bit line BL is formed, for example, in the second mask layer MX20. It is also necessary to form them at the corresponding positions as in the damascene method.

  FIG. 8 is a schematic cross-sectional view for explaining a one-transistor semiconductor memory cell according to a third embodiment of the present invention. The members having the same member numbers as those in FIG. 1 to FIG. 7 indicate the same members or members corresponding thereto, and the repetitive description thereof will be omitted below.

  According to FIG. 8, the interlayer dielectric 4 may further have a continuous multilayer structure, and a multilayer structure having a continuous SiN layer 4A and a BPSG layer 4B is particularly used. In this case, the SiN layer 4A is used as a passivation layer and directly (contacts) on the surface of the semiconductor substrate 1 and the surface of the patterned gate stack composed of the gate insulating layer 2 and the control electrode G. E) is provided. The materials known from conventional contact manufacturing methods are also used for the lining layer 5 or the capacitor counter electrode CE1. A TiN layer with a thickness of about 10 nm is particularly used.

  For the capacitor dielectric CD newly introduced in the manufacturing process of the invention or for the further dielectric layer 7, it is possible to use silicon oxide, silicon nitride or so-called high-k dielectrics with a high dielectric constant. preferable. Moreover, the thickness of this dielectric layer 7 is 3 nm-15 nm, As a result, a capacity | capacitance can be adjusted with the said thickness.

  It is preferable to use a tungsten plug, which is known in the conventional contact method and can optimally fill a very deep contact hole, in each contact hole as the filler layers 6 and 8. When the filler layers 6 and 8 are not integrally formed, it is preferable that the bit line BL and the capacitor connection line Vss are patterned in the first metallization layer and formed by the Al layers. Furthermore, similarly, a Cu layer or other highly conductive metal layer can also be formed in the first metallization layer or a higher metallization layer, for example by a damascene method.

  FIG. 9 shows a schematic plan view of a 1T semiconductor memory cell according to each of the first to third embodiments. About the member of the same member number as FIG. 1 thru | or FIG. 8, the same member or a member equivalent to it is shown, The repeated description regarding it is abbreviate | omitted below.

  According to FIG. 9, the contact hole has an oval shape in its plan view (cross section along the surface direction of the semiconductor substrate 1). However, these contact holes are not limited to elliptical shapes, and may be circular, rectangular, or other shapes as well. In particular, in the present embodiment, the shape of the contact hole is assumed to be a square or a trapezoid.

  FIG. 10 is a schematic plan view for explaining one-transistor semiconductor memory cells according to the fourth to sixth embodiments of the present invention. The members having the same member numbers as those in FIGS. 1 to 9 indicate the same member or a member corresponding thereto, and repeated description thereof will be omitted below.

  According to FIG. 10, in particular, the contact hole for freely selecting and adjusting the capacitor capacitance may be greatly enlarged. The drain region D in the semiconductor substrate 1 is a region in which the doped drain region D is greatly enlarged by the auxiliary drain region HD. The auxiliary drain region HD is arranged such that its longitudinal direction is orthogonal to the longitudinal direction of the word line WL, for example. Similarly, an auxiliary connection line portion HVss may be formed on the interlayer dielectric 4. The auxiliary connection line portion HVss can sufficiently contact the filler layer 8 in the contact hole. As the electrode zone is enlarged, the capacitance of the capacitor increases. With such a configuration and method, for example, the refresh cycle can be substantially extended.

  FIG. 10 further shows a one-transistor semiconductor memory cell having two or three contact hole capacitors KK1, KK2, and KK3. The contact hole capacitors KK1, KK2, and KK3 are also disposed on the enlarged auxiliary drain region HD, and are also connected in parallel to the auxiliary connection line portion HVss on the interlayer dielectric 4. Yes.

  Each of the three contact hole capacitors KK1 to KK3 has its auxiliary contact line portion HVss formed so as to be substantially orthogonal to the capacitor connection line Vss or orthogonal to the word line WL and the bit line BL. Each capacity | capacitance may mutually be connected in parallel. As a result, the overall capacitance for the corresponding one-transistor semiconductor memory cell is increased corresponding to each contact hole capacitor KK1-KK3.

  In a modular semiconductor memory cell in which contact hole capacitors can be connected in a modular manner so as to have a predetermined capacitance value, the capacitance value is further corrected sequentially by, for example, laser trimming, which has been conventionally known. Has the advantage of being able to For this purpose, it is only necessary to remove unnecessary contact hole capacitors by separation or disconnection via the auxiliary connection line portion.

  On the other hand, in principle, the respective contact hole capacitors formed in different capacitance values or different shapes may be interconnected by the above-described method. As a result, modular capacity values can be finely adapted to each circuit requirement.

  FIG. 11 shows the dependency between the total capacitance value of the contact hole capacitor functioning as the capacitor dielectric used and the number of sub-capacitors connected in parallel as shown in FIG. A schematic graph is shown.

  Thus, very high capacitance values are obtained even for enlarged contact hole capacitors having a nitride layer of about 5 nm thickness as the capacitor dielectric. Furthermore, the predicted dependence of the overall capacitance value on the number of capacitors connected in parallel with each other could be confirmed.

  The present invention has been described above with reference to a one-transistor semiconductor memory cell formed on a silicon semiconductor substrate. However, the present invention is not limited to the above description, and covers the two-transistor and three-transistor semiconductor memory cells shown in FIGS. 2 and 3 and alternative semiconductor materials. Further, the contact hole capacitor may be formed in the contact hole for the source region S. The contact holes are basically elliptical, but alternative contact hole shapes may be used as well. Instead of the materials specifically used for contact hole capacitors, alternative materials that allow a sufficiently high capacitor capacity can also be used.

1 is a schematic equivalent circuit diagram of a prior art 1T semiconductor memory cell. FIG. FIG. 2 is a schematic equivalent circuit diagram of a prior art 2T semiconductor memory cell. FIG. 2 is a schematic equivalent circuit diagram of a prior art 3T semiconductor memory cell. 1 is a schematic cross-sectional view of a 1T semiconductor memory cell having a prior art deep trench capacitor. FIG. 1 is a schematic cross-sectional view of a 1T semiconductor memory cell having a prior art MOS capacitor. FIG. FIG. 3 is a schematic cross-sectional view showing one main step in the method for manufacturing a 1T semiconductor memory cell according to the first embodiment of the present invention. FIG. 6 is a schematic cross-sectional view showing another main process in the method of manufacturing the 1T semiconductor memory cell according to the first embodiment of the present invention. 12 is a schematic cross-sectional view showing still another main step in the method of manufacturing the 1T semiconductor memory cell according to the first embodiment of the present invention. FIG. It is the schematic sectional drawing which shows the 1 main process in the manufacturing method of 1T semiconductor memory cell based on 2nd Embodiment of this invention. It is the schematic sectional drawing which shows the other main processes in the manufacturing method of 1T semiconductor memory cell based on 2nd Embodiment of this invention. It is the schematic sectional drawing which shows the main further another process in the manufacturing method of 1T semiconductor memory cell based on 2nd Embodiment of this invention. FIG. 6 is a schematic cross-sectional view of a 1T semiconductor memory cell according to a third embodiment of the present invention. FIG. 9 is a schematic plan view of each 1T semiconductor memory cell shown in FIG. 8 of the present invention. FIG. 7 is a schematic plan view of each 1T semiconductor memory cell according to each of the fourth to sixth embodiments of the present invention. 6 is a graph schematically showing a relationship between an overall capacitance as a function of a used capacitor dielectric and a plurality of contact hole capacitors connected in parallel to each other.

Claims (2)

In a method of manufacturing a semiconductor memory cell having a contact hole capacitor (KK) and at least one selection transistor (AT) connected to the contact hole capacitor (KK),
a) preparing a semiconductor substrate (1);
b) A gate comprising a source region (S) and a drain region (D) for defining a channel in the semiconductor substrate, a gate insulator (2) and a control electrode (G) formed on the surface of the channel. Forming the selection transistor (AT) including a stack;
c) forming an interlayer insulator (4) on the surface of the semiconductor substrate (1) and on the surface of the gate stack (2, G);
d) Source or drain region and contact hole in the interlayer insulator (4) for at least partially exposing the source region (S) and drain region (D) of the select transistor (AT). Forming a contact hole for the capacitor;
e) formed on the surface of the semiconductor substrate (1) and on the surface of the at least one contact hole for the contact hole capacitor (KK) and up to the surface of the interlayer insulator (4) Forming the lining layer (5) formed so as not to reach the capacitor counter electrode (CE1);
f) extending over the surface of the interlayer insulator (4) and forming a further insulator layer (7) as a capacitor insulator on the surface of the capacitor counter electrode (CE1);
g) Inside the at least one contact hole for the contact hole capacitor (KK), a conductive filler layer (8) is formed on the surface of the capacitor insulator (CD) as a capacitor electrode (CE2). And forming as a process,
h) forming a capacitor connection line (Vss) for connecting the capacitor electrode (CE2) on the surface of the interlayer insulator (4) and on the surface of the filler layer (8); Including
In the step f), the contact holes for the source and drain regions are filled with a first mask (MX1),
The further insulator layer (7) is deposited over the entire surface and subsequently planarized until it reaches the surface of the interlayer insulator (4);
A method of manufacturing a semiconductor memory cell, wherein the first mask (MX1) is removed from the contact hole for each of the source and drain regions. In a method of manufacturing a semiconductor memory cell having a contact hole capacitor (KK) and at least one selection transistor (AT) connected to the contact hole capacitor (KK),
a) preparing a semiconductor substrate (1);
b) A gate comprising a source region (S) and a drain region (D) for defining a channel in the semiconductor substrate, a gate insulator (2) and a control electrode (G) formed on the surface of the channel. Forming the selection transistor (AT) including a stack;
c) forming an interlayer insulator (4) on the surface of the semiconductor substrate (1) and on the surface of the gate stack (2, G);
d) Source or drain region and contact hole in the interlayer insulator (4) for at least partially exposing the source region (S) and drain region (D) of the select transistor (AT). Forming a contact hole for the capacitor;
e) formed on the surface of the semiconductor substrate (1) and on the surface of the at least one contact hole for the contact hole capacitor (KK) and up to the surface of the interlayer insulator (4) Forming the lining layer (5) formed so as not to reach the capacitor counter electrode (CE1);
f) extending over the surface of the interlayer insulator (4) and forming a further insulator layer (7) as a capacitor insulator on the surface of the capacitor counter electrode (CE1);
g) Inside the at least one contact hole for the contact hole capacitor (KK), a conductive filler layer (8) is formed on the surface of the capacitor insulator (CD) as a capacitor electrode (CE2). And forming as a process,
h) forming a capacitor connection line (Vss) for connecting the capacitor electrode (CE2) on the surface of the interlayer insulator (4) and on the surface of the filler layer (8); Including
In the step f), at least one contact hole for the contact hole capacitor (KK) is filled with a first mask (MX10),
Filling the contact holes for the source or drain regions with a conductive second filler layer (6);
Removing the first mask (MX10);
Forming a second mask (MX20) exposing only the at least one contact hole for the contact hole capacitor (KK);
A method of manufacturing a semiconductor memory cell, characterized in that the further insulator layer (7) is deposited over the entire surface.

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