CN108389837B

CN108389837B - Transistor structure, memory structure and preparation method thereof

Info

Publication number: CN108389837B
Application number: CN201810433131.7A
Authority: CN
Inventors: 请求不公布姓名
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2018-05-08
Filing date: 2018-05-08
Publication date: 2023-06-30
Anticipated expiration: 2038-05-08
Also published as: CN108389837A

Abstract

The invention provides a transistor structure, a memory structure and a preparation method thereof, comprising the following steps: 1) Providing a semiconductor substrate, and forming a groove structure in the semiconductor substrate; 2) Forming a first gate oxide layer on the bottom and the side wall of the groove structure by adopting an atomic layer deposition process; 3) Forming a second gate oxide layer on the surface of the first gate oxide layer by using an in-situ water vapor generation process; 4) Forming a conductive layer on the bottom and partial side wall of the gate oxide layer; 5) Forming a hole filling insulating layer in the groove structure, wherein the groove structure is filled with the hole filling insulating layer; 6) And forming a source region and a drain region in the semiconductor substrate at two sides of the groove structure respectively. According to the transistor structure, the gate oxide layer is arranged to be of the structure that the thickness of the gate oxide layer at the bottom of the groove structure is smaller than that of the gate oxide layer at the side wall of the groove structure, so that the gate induced drain leakage current can be remarkably reduced, and the overall performance of a device is further improved.

Description

Transistor structure, memory structure and preparation method thereof

Technical Field

The invention belongs to the technical field of integrated circuit manufacturing, and particularly relates to a transistor structure, a memory structure and a preparation method thereof.

Background

Dynamic random access memory (Dynamic Random Access Memory, abbreviated as DRAM) is a semiconductor memory device commonly used in computers and is composed of a number of repeated memory cells. Each memory cell is mainly composed of a transistor and a capacitor controlled by the transistor, and the memory cells are arranged in an array form, and each memory cell is electrically connected with each other through a word line and a bit line. With the increasing development of light, thin, short and small electronic products, the design of the dram device is also required to meet the requirements of high integration and high density and the trend of miniaturization, so as to increase the integration of the dram to speed up the operation speed of the device, and meet the requirements of consumers for miniaturized electronic devices.

However, the conventional dynamic random access memory has the problem of large gate-induced drain leakage (GIDL) due to the same thickness of each part of the gate oxide layer, and the problem of deterioration of the basic characteristics-refresh characteristics and retention time of the dynamic random access memory due to the large gate-induced drain leakage.

Disclosure of Invention

In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a transistor structure, a memory structure and a method for manufacturing the same, which are used for solving the problems of poor basic characteristics-refresh characteristics, degradation of retention time and the like of the dynamic random access memory caused by the existence of a large gate-induced drain leakage current in the dynamic random access memory in the prior art.

To achieve the above and other related objects, the present invention provides a method for manufacturing a transistor structure, the transistor structure comprising the steps of:

1) Providing a semiconductor substrate, and forming a groove structure in the semiconductor substrate;

2) Forming a first gate oxide layer on the bottom and the side wall of the groove structure by adopting an atomic layer deposition process, wherein the first gate oxide layer at the bottom of the groove structure and the first gate oxide layer at the side wall of the groove structure have the same thickness;

3) Forming a second gate oxide layer on the surface of the first gate oxide layer by adopting an in-situ water vapor generation process, wherein the thickness of the second gate oxide layer positioned at the bottom of the groove structure is smaller than that of the second gate oxide layer positioned on the side wall of the groove structure; the first gate oxide layer and the second gate oxide layer form a gate oxide layer with a double-layer structure together;

4) Forming a conductive layer on the bottom and partial side wall of the gate oxide layer, wherein the top end of the conductive layer is lower than the upper surface of the semiconductor substrate;

5) Forming a hole filling insulating layer in the groove structure, wherein the groove structure is filled with the hole filling insulating layer; the method comprises the steps of,

6) And forming a source region and a drain region in the semiconductor substrate at two sides of the groove structure respectively.

As a preferred embodiment of the present invention, the thickness of the first gate oxide layer formed in the step 2) is between 40 angstroms and 50 angstroms; the thickness of the second gate oxide layer formed in the step 3) and located on the side wall of the groove structure is 80-100 angstroms; the thickness of the second gate oxide layer formed at the bottom of the trench structure in the step 3) is between 0.01 and 20 angstroms.

As a preferable scheme of the invention, the thickness of the gate oxide layer formed at the bottom of the trench structure after the step 3) is between 50 and 60 angstroms.

The present invention also provides a transistor structure comprising: a semiconductor substrate having a trench structure within the semiconductor substrate; the first gate oxide layer is positioned at the bottom and the side wall of the groove structure, and the first gate oxide layer positioned at the bottom of the groove structure and the first gate oxide layer positioned at the side wall of the groove structure have the same thickness; the second gate oxide layer is positioned on the surface of the first gate oxide layer, and the thickness of the second gate oxide layer positioned at the bottom of the groove structure is smaller than that of the second gate oxide layer positioned on the side wall of the groove structure; the first gate oxide layer and the second gate oxide layer form a gate oxide layer with a double-layer structure together; the conducting layer is positioned at the bottom and the partial side wall of the gate oxide layer, wherein the top end of the conducting layer is lower than the upper surface of the semiconductor substrate; the hole filling insulating layer is filled in the groove structure and fills the groove structure; the semiconductor substrate is further provided with an active region and a drain region, the active region is located in the semiconductor substrate at one side of the groove structure, and the drain region is located in the semiconductor substrate at the other side of the groove structure.

As a preferred aspect of the present invention, the thickness of the second gate oxide layer at the bottom of the trench structure is also smaller than the thickness of the first gate oxide layer at the bottom of the trench structure.

As a preferable scheme of the invention, the thickness of the first gate oxide layer is between 40 and 50 angstroms, the thickness of the second gate oxide layer positioned on the side wall of the groove structure is between 80 and 100 angstroms, and the thickness of the second gate oxide layer positioned at the bottom of the groove structure is between 0.01 and 20 angstroms.

As a preferable scheme of the invention, the thickness of the gate oxide layer at the bottom of the groove structure is 50-60 angstroms.

The invention also provides a preparation method of the transistor structure, which comprises the following steps:

providing a semiconductor substrate, and forming a groove structure in the semiconductor substrate; forming a gate oxide layer on the bottom and the side wall of the groove structure by adopting an in-situ water vapor generation process; forming a conductive layer on the bottom and partial side wall of the gate oxide layer, wherein the top end of the conductive layer is lower than the upper surface of the semiconductor substrate; forming a hole filling insulating layer in the groove structure, wherein the groove structure is filled with the hole filling insulating layer; forming a source region and a drain region in the semiconductor substrate at two sides of the groove structure respectively; wherein, the liquid crystal display device comprises a liquid crystal display device,

The thickness of the gate oxide layer at the bottom of the trench structure is smaller than that of the gate oxide layer at the side wall of the trench structure.

The present invention also provides a transistor structure comprising:

a semiconductor substrate having a trench structure within the semiconductor substrate;

the gate oxide layer is positioned at the bottom and the side wall of the groove structure, and the thickness of the gate oxide layer positioned at the bottom of the groove structure is smaller than that of the gate oxide layer positioned at the side wall of the groove structure;

the conducting layer is positioned at the bottom and the partial side wall of the gate oxide layer, wherein the top end of the conducting layer is lower than the upper surface of the semiconductor substrate; the method comprises the steps of,

the hole filling insulating layer is filled in the groove structure and fills the groove structure;

the semiconductor substrate is further provided with an active region and a drain region, the active region is located in the semiconductor substrate at one side of the groove structure, and the drain region is located in the semiconductor substrate at the other side of the groove structure.

The invention also provides a preparation method of the memory structure, which comprises the following steps:

1) Providing a semiconductor substrate, and forming a plurality of groove structures in the semiconductor substrate; a plurality of active areas are formed in the semiconductor substrate, and at least two groove structures penetrate through the active areas;

2) Forming a gate oxide layer at the bottom and the side wall of the groove structure, wherein the thickness of the gate oxide layer at the bottom of the groove structure is smaller than that of the gate oxide layer at the side wall of the groove structure;

3) Forming a conductive layer on the bottom and partial side wall of the gate oxide layer, wherein the top end of the conductive layer is lower than the upper surface of the semiconductor substrate; the conductive layer forms a buried gate word line, and the extending direction of the buried gate word line and the extending direction of the active region intersect at a first angle smaller than 90 degrees;

4) Forming a hole filling insulating layer in the groove structure, wherein the groove structure is filled with the hole filling insulating layer;

5) Forming a source region and a drain region in the active region of the semiconductor substrate at two sides of the groove structure respectively, wherein the drain region is positioned at the middle part of the active region between the groove structures, and the source region is positioned at the side part of the active region outside the groove structure;

6) Forming a plurality of bit lines which are arranged in parallel at intervals in the semiconductor substrate, wherein the extending direction of the bit lines is intersected with the extending direction of the active region at a second angle smaller than 90 degrees, and is intersected with the extending direction of the embedded grid word lines at a third angle smaller than or equal to 90 degrees, and the third angle is larger than the first angle and also larger than the second angle; the bit line is connected with the drain region of the transistor structure; the method comprises the steps of,

7) A plurality of capacitor structures are formed on the semiconductor substrate, the capacitor structures being connected to the source regions of the transistor structures.

In a preferred embodiment of the present invention, in step 2), forming a gate oxide layer on the bottom and the sidewall of the trench structure includes the following steps:

2-1) forming a first gate oxide layer on the bottom and the side wall of the groove structure by adopting an atomic layer deposition process, wherein the first gate oxide layer at the bottom of the groove structure and the first gate oxide layer at the side wall of the groove structure have the same thickness; the method comprises the steps of,

2-2) forming a second gate oxide layer on the surface of the first gate oxide layer by adopting an in-situ water vapor generation process, wherein the thickness of the second gate oxide layer positioned at the bottom of the groove structure is smaller than that of the second gate oxide layer positioned on the side wall of the groove structure.

As a preferable mode of the present invention, the thickness of the first gate oxide layer formed in step 2-1) is between 40 angstroms and 50 angstroms; the thickness of the second gate oxide layer formed in the step 2-2) and located on the side wall of the groove structure is 80-100 angstroms; the thickness of the second gate oxide layer formed in the step 2-2) and located at the bottom of the trench structure is between 0.01 and 20 angstroms.

As a preferred embodiment of the present invention, the steps between the step 5) and the step 6) further include the following steps: forming a bit line contact structure in the drain region of the transistor structure, wherein the bit line contact structure is contacted with the drain region of the transistor structure; the bit line formed in step 6) is connected to the drain region of the transistor structure via the bit line contact structure.

As a preferred embodiment of the present invention, the steps between the step 6) and the step 7) further include the following steps: forming a storage node contact structure in a source region of the transistor structure, wherein the storage node contact structure is contacted with the source region of the transistor structure; the capacitor structure formed in step 7) is connected to the source region of the transistor structure via the storage node contact structure.

In a preferred embodiment of the present invention, the thickness of the gate oxide layer formed in step 2) and located at the bottom of the trench structure is between 50 a and 60 a.

The present invention also provides a memory structure comprising:

the semiconductor substrate is provided with a plurality of groove structures positioned in the semiconductor substrate, a plurality of active areas are formed in the substrate, and at least two groove structures penetrate through each active area;

the conducting layer is positioned at the bottom and the partial side wall of the gate oxide layer, wherein the top end of the conducting layer is lower than the upper surface of the semiconductor substrate; the conductive layer forms a buried gate word line, and the extending direction of the buried gate word line and the extending direction of the active region intersect at a first angle smaller than 90 degrees; the method comprises the steps of,

the hole filling insulating layer is filled in the groove structure and fills the groove structure; the semiconductor substrate is further provided with an active region and a drain region, the active region is positioned in the semiconductor substrate at one side of the groove structure, and the drain region is positioned in the semiconductor substrate at the other side of the groove structure;

The extension direction of the bit lines and the extension direction of the active region intersect at a second angle smaller than 90 degrees, the extension direction of the bit lines and the extension direction of the embedded grid word lines intersect at a third angle smaller than or equal to 90 degrees, and the third angle is larger than the first angle and also larger than the second angle; the bit line is connected with the drain region of the transistor structure; the method comprises the steps of,

and the capacitor structures are connected with the source regions of the transistor structures.

As a preferred embodiment of the present invention, the gate oxide layer includes:

the first gate oxide layer is positioned at the bottom and the side wall of the groove structure, and the first gate oxide layer positioned at the bottom of the groove structure and the first gate oxide layer positioned at the side wall of the groove structure have the same thickness; the method comprises the steps of,

the second gate oxide layer is positioned on the surface of the first gate oxide layer, and the thickness of the second gate oxide layer positioned at the bottom of the groove structure is smaller than that of the second gate oxide layer positioned on the side wall of the groove structure.

As a preferred aspect of the present invention, the memory structure further includes a bit line contact structure that is located between the bit line and the drain region of the transistor structure and connects the bit line and the drain region of the transistor structure.

As a preferred aspect of the present invention, the memory structure further comprises a storage node contact structure located between and connecting the capacitor structure and the source region of the transistor structure.

As described above, the transistor structure, the memory structure and the manufacturing method thereof of the present invention have the following beneficial effects:

according to the transistor structure, the gate oxide layer is arranged to be of the structure that the thickness of the gate oxide layer at the bottom of the groove structure is smaller than that of the gate oxide layer at the side wall of the groove structure, so that the gate induced drain leakage current can be remarkably reduced, and the overall performance of a device is further improved.

Drawings

Fig. 1 is a flowchart of a method for manufacturing a transistor structure according to a first embodiment of the present invention.

Fig. 2 to 7 are schematic cross-sectional views of a transistor structure according to a first embodiment of the present invention; fig. 7 is a schematic cross-sectional view of a transistor structure according to a second embodiment of the present invention.

Fig. 8 is a schematic cross-sectional view of a transistor structure according to a third embodiment of the present invention after forming a gate oxide layer;

fig. 9 is a schematic cross-sectional structure of a transistor structure obtained by the method for manufacturing a transistor structure according to the third embodiment of the present invention, wherein fig. 9 is a schematic cross-sectional structure of a transistor structure according to the fourth embodiment of the present invention.

Fig. 10 is a flowchart of a method for manufacturing a memory structure according to a fifth embodiment of the present invention.

Fig. 11 to 20 are schematic structural diagrams of a method for manufacturing a memory structure according to a fifth embodiment of the present invention at each step; fig. 19 is a schematic top view of the structure obtained in step 6), fig. 18 is a schematic cross-sectional structure along AA direction of fig. 19, and fig. 20 is a schematic cross-sectional structure of the memory structure in the sixth embodiment of the present invention.

Description of element reference numerals

10. Semiconductor substrate

101. Shallow trench isolation structure

102. Active region

11. Groove structure

12. Gate oxide layer

121. First gate oxide layer

122. Second gate oxide layer

13. Conductive layer

131. Buried gate word line

14. Filling an insulating layer

15. Source region

16. Drain region

17. Bit line

18. Capacitor structure

19. Bit line contact structure

20. Storage node contact structure

d1 Thickness of gate oxide layer at bottom of trench structure

d2 Thickness of gate oxide layer on sidewall of trench structure

Alpha first angle

Beta second angle

Gamma third angle

Detailed Description

Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.

Please refer to fig. 1 to 20. It should be noted that, the illustrations provided in the present embodiment are merely schematic illustrations of the basic concepts of the present invention, and only the components related to the present invention are shown in the illustrations, rather than being drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.

Example 1

As shown in fig. 1, the present invention provides a method for preparing a transistor structure, where the transistor structure includes the following steps:

1) Providing a semiconductor substrate 10 and forming a trench structure 11 in the semiconductor substrate;

2) Forming a first gate oxide layer 121 on the bottom and the side wall of the trench structure 11 by adopting an Atomic Layer Deposition (ALD) process, wherein the first gate oxide layer 121 at the bottom of the trench structure 11 and the first gate oxide layer 121 at the side wall of the trench structure 11 have approximately the same thickness;

3) Forming a second gate oxide layer 122 on the surface of the first gate oxide layer 121 by adopting an in-situ steam generation (ISSG) process, wherein the thickness of the second gate oxide layer 122 at the bottom of the trench structure 11 is smaller than that of the second gate oxide layer 122 at the side wall of the trench structure 11; the first gate oxide layer 121 and the second gate oxide layer 122 together form a gate oxide layer 12 with a double-layer structure;

4) Forming a conductive layer 13 on the bottom and partial side walls of the gate oxide layer 12, wherein the top end of the conductive layer 13 is lower than the upper surface of the semiconductor substrate 10;

5) Forming a hole filling insulating layer 14 in the groove structure 11, wherein the groove structure 11 is filled with the hole filling insulating layer 14; the method comprises the steps of,

6) Source region 15 and drain region 16 are formed in semiconductor substrate 10 on both sides of trench structure 11, respectively.

In step 1), referring to step S1 of fig. 1 and fig. 2, a semiconductor substrate 10 is provided, and a trench structure 11 is formed in the semiconductor substrate 10.

The material of the semiconductor substrate 10 includes, but is not limited to, a monocrystalline or polycrystalline semiconductor material, and may be an intrinsic monocrystalline silicon substrate or a lightly doped silicon substrate, and further may be an N-type polycrystalline silicon substrate or a P-type polycrystalline silicon substrate, and in this embodiment, the semiconductor substrate 10 is a p+ type polycrystalline silicon substrate.

As an example, a plurality of shallow trench isolation structures (not shown) may be formed in the semiconductor substrate 10, and the shallow trench isolation structures isolate a plurality of active regions (not shown) in the semiconductor substrate 10. The trench structure 11 may be located within the active region, within the shallow trench isolation structure, or within both the active region and the shallow trench isolation structure.

As an example, the shape and number of the groove structures 11 may be set according to actual needs, and in fig. 2, the groove structures 11 are U-shaped grooves, and the number of the groove structures 11 is one as an example, but in an actual example, the invention is not limited thereto.

As an example, forming the trench structure 11 in the semiconductor substrate 10 includes the following steps:

1-1) forming a mask layer (not shown) with a window (not shown) on the surface of the semiconductor substrate 10, wherein the window corresponds to the trench structure vertically; a kind of electronic device with high-pressure air-conditioning system

1-2) etching the semiconductor substrate 10 based on the window to form the trench structure 11.

In step 2), referring to step S2 in fig. 1 and fig. 3, a first gate oxide layer 121 is formed on the bottom and the sidewall of the trench structure 11 by an atomic layer deposition process, and the first gate oxide layer 121 at the bottom of the trench structure 11 and the first gate oxide layer 121 at the sidewall of the trench structure 11 have approximately the same thickness.

It should be noted that, in the Step 2), the process of forming the first gate oxide layer 121 by using an atomic layer deposition process, which has a relatively good Step coverage, and can form the first gate oxide layer 121 with approximately the same thickness at the bottom and the sidewall of the trench structure 11, may be used to implement the Step 2).

As an example, the thickness of the first gate oxide layer 121 formed in step 2) may be set according to actual needs, and preferably, in this embodiment, the thickness of the first gate oxide layer 121 is between 40 angstroms and 50 angstroms.

In step 3), referring to step S3 in fig. 1 and fig. 4, an in-situ steam generation (ISSG) process is adopted to form a second gate oxide layer 122 on the surface of the first gate oxide layer 121, wherein the thickness of the second gate oxide layer 122 at the bottom of the trench structure 11 is smaller than the thickness of the second gate oxide layer 122 at the sidewall of the trench structure 11; the first gate oxide layer 121 and the second gate oxide layer 122 together form a gate oxide layer 12 with a double-layer structure.

By way of example, the so-called in-situ vapor generation process is to use oxygen doped with a small amount of hydrogen as a reaction gas, and generate a chemical reaction similar to combustion by the hydrogen and the oxygen at a high temperature to generate a large amount of gas-phase active free radicals, wherein the gas-phase active free radicals are mainly atomic oxygen, and an oxide layer with few internal defects and relatively small interface state density can be obtained by using the in-situ vapor generation process due to the strong oxidation of the atomic oxygen. However, the step coverage of the in-situ vapor generation process is poor, and because the trench structure 11 has a certain depth, when the second gate oxide layer 12 is formed in the trench structure 11 by using the in-situ vapor generation process, the thickness of the second gate oxide layer 122 at the bottom of the trench structure 11 is smaller than the thickness of the second gate oxide layer 122 at the sidewall of the trench structure 11.

As an example, the thickness of the second gate oxide layer 122 formed in step 3) may be set according to actual needs, and preferably, in this embodiment, the thickness of the second gate oxide layer 122 formed in step 3) and located on the sidewall of the trench structure 11 is between 80 angstroms and 100 angstroms, and the thickness of the second gate oxide layer 122 formed in step 3) and located on the bottom of the trench structure 11 is between 0.01 angstroms and 20 angstroms.

It should be noted that, in addition to the in-situ water vapor generation process, any other process that has a relatively poor Step coverage (Step coverage) and the thickness of the second gate oxide layer 122 that can be located at the bottom of the trench structure 11 is smaller than the thickness of the second gate oxide layer 122 that can be located at the sidewall of the trench structure 11 may be used to implement Step 3).

As an example, the thickness d1 of the gate oxide layer 12 formed at the bottom of the trench structure 11 after the step 3) may be set according to actual needs, and preferably, in this embodiment, the thickness d1 of the gate oxide layer 12 at the bottom of the trench structure 11 is between 50 angstroms and 60 angstroms. Of course, in other examples, the thickness d1 of the gate oxide layer 12 at the bottom of the trench structure 11 may be adjusted according to the actual requirement according to the thickness d2 of the gate oxide layer 12 at the sidewall of the trench structure 11, and the difference between the thickness d1 of the gate oxide layer 12 at the bottom of the trench structure 11 and the thickness d2 of the gate oxide layer 12 at the sidewall of the trench structure 11 is not limited herein.

The thickness d1 of the gate oxide layer 12 at the bottom of the trench structure 11 is smaller than the thickness d2 of the gate oxide layer 12 at the sidewall of the trench structure 11, so that the gate-induced drain leakage current of the obtained transistor structure can be significantly reduced, and the overall performance of the device is further improved.

In step 4), referring to step S4 in fig. 1 and fig. 5, a conductive layer 13 is formed on the bottom and partial sidewall of the gate oxide layer 12, wherein the top of the conductive layer 13 is lower than the upper surface of the semiconductor substrate 10.

As an example, forming the conductive layer 13 on the bottom and the partial sidewall of the gate oxide layer 12 may include the following steps:

4-1) forming a conductive material layer (not shown) on the surface of the structure obtained in the step 3) and in the trench structure 11, wherein the conductive material layer fills the trench structure 11 and covers the surface of the semiconductor substrate 10;

4-2) removing the conductive material layer located on the surface of the semiconductor substrate 10 and a part of the conductive material layer located in the trench structure 11 by using a back etching process, so that the top of the conductive material layer remaining in the trench structure 11 is lower than the upper surface of the semiconductor substrate 10, and the conductive material layer remaining in the trench structure 11 is the conductive layer 13. Of course, in other examples, an etching process or a polishing process may be used to remove the conductive material layer located on the surface of the semiconductor substrate 10, and then an etching back process may be used to remove a portion of the conductive material layer located in the trench structure 11 to obtain the conductive layer 13.

Of course, in other examples, it is also possible to deposit a conductive material layer of a certain thickness only within the trench structure 11 as the conductive layer 13.

As an example, the distance between the top of the conductive layer 13 and the upper surface of the semiconductor substrate 10 may be set according to actual needs, which is not limited herein.

As an example, the material of the conductive layer 13 may be, but is not limited to, tungsten (W).

In step 5), referring to step S5 in fig. 1 and fig. 6, a hole-filling insulating layer 14 is formed in the trench structure 11, and the hole-filling insulating layer 14 fills the trench structure 11.

As an example, forming the hole filling insulating layer 14 in the trench structure 11 includes the following steps:

5-1) forming a layer of insulating material (not shown) on the surface of the conductive layer 13 and the surface of the semiconductor substrate 10 within the trench structure 11;

5-2) removing the insulating material layer on the surface of the semiconductor substrate 10 by using a grinding process, wherein the insulating material layer remained in the trench structure 11 is the hole-filling insulating layer 14.

Of course, in other examples, an insulating material layer may be directly deposited on the surface of the conductive layer 13 in the trench structure 11, where the insulating material layer fills the trench structure 11, and the insulating material layer that fills the trench structure 11 is the hole-filling insulating layer 14.

As an example, the material of the hole-filling insulating layer 14 may be, but is not limited to, silicon nitride (SiN).

In step 6), referring to step S6 in fig. 1 and fig. 7, a source region 15 and a drain region 16 are respectively formed in the semiconductor substrate 10 at two sides of the trench structure 11.

As an example, the source region 15 and the drain region 16 are formed on the semiconductor substrate 10 at both sides of the trench structure 11 by using an ion implantation process, and a method for forming the source region 15 and the drain region 16 is known to those skilled in the art and will not be described here.

Example two

With continued reference to fig. 7 in conjunction with fig. 2 to 6, the present invention further provides a transistor structure, which may be manufactured by, but not limited to, the manufacturing method described in the first embodiment, the transistor structure comprising: a semiconductor substrate 10; a trench structure 11, said trench structure 11 being located within said semiconductor substrate 10; a first gate oxide layer 121, where the first gate oxide layer 121 is located at the bottom and the side wall of the trench structure 11, and the first gate oxide layer 121 located at the bottom of the trench structure 11 and the first gate oxide layer 121 located at the side wall of the trench structure 11 have approximately the same thickness; the second gate oxide layer 122 is located on the surface of the first gate oxide layer 121, and the thickness of the second gate oxide layer 122 located at the bottom of the trench structure 11 is smaller than the thickness of the second gate oxide layer 122 located at the side wall of the trench structure 11; the first gate oxide layer 121 and the second gate oxide layer 122 together form a gate oxide layer 12 with a double-layer structure; a conductive layer 13, wherein the conductive layer 13 is located at the bottom and partial side wall of the gate oxide layer 12, and the top end of the conductive layer 13 is lower than the upper surface of the semiconductor substrate 10; and a hole filling insulating layer 14, wherein the hole filling insulating layer 14 is filled in the groove structure 11 and fills the groove structure 11; the semiconductor substrate 10 further forms an active region 15 and a drain region 16, the source region 15 is located in the semiconductor substrate 10 at one side of the trench structure 11, and the drain region 16 is located in the semiconductor substrate 10 at the other side of the trench structure 11.

As an example, the first gate oxide layer 121 is an oxide layer formed by a process with good step coverage, and preferably, in this embodiment, the first gate oxide layer 121 is an oxide layer formed by an atomic layer deposition process; the second gate oxide layer 122 is an oxide layer formed by a process with poor step coverage, and preferably, in this embodiment, the second gate oxide layer 122 is an oxide layer formed by an in-situ vapor generation process.

As an example, the thickness of the first gate oxide layer 121 and the thickness of the second gate oxide layer 122 may be set according to actual needs, preferably, the thickness of the second gate oxide layer 122 at the bottom of the trench structure 11 is smaller than the thickness of the first gate oxide layer 121 at the bottom of the trench structure 11, more preferably, the thickness of the first gate oxide layer 121 is between 40 angstroms and 50 angstroms, and the thickness of the second gate oxide layer 122 at the sidewall of the trench structure 11 is between 80 angstroms and 100 angstroms, and the thickness of the second gate oxide layer 122 at the bottom of the trench structure 11 is between 0.01 angstroms and 20 angstroms.

The thickness d1 of the gate oxide layer 12 at the bottom of the trench structure 11 may be set according to practical needs, and preferably, in this embodiment, the thickness d1 of the gate oxide layer 12 at the bottom of the trench structure 11 is between 50 angstroms and 60 angstroms. Of course, in other examples, the thickness d1 of the gate oxide layer 12 at the bottom of the trench structure 11 may be adjusted according to the actual requirement according to the thickness d2 of the gate oxide layer 12 at the sidewall of the trench structure 11, and the difference between the thickness d1 of the gate oxide layer 12 at the bottom of the trench structure 11 and the thickness d2 of the gate oxide layer 12 at the sidewall of the trench structure 11 is not limited herein.

The thickness d1 of the gate oxide layer 12 at the bottom of the trench structure 11 is smaller than the thickness d2 of the gate oxide layer 12 at the sidewall of the trench structure 11, so that the gate-induced drain leakage current of the transistor structure can be significantly reduced, and the overall performance of the device is further improved.

Example III

The present invention also provides a method for manufacturing a transistor structure, which is substantially the same as the method for manufacturing a transistor structure described in the first embodiment, and is different from the specific structure and the forming method of the gate oxide layer 12, specifically: in the first embodiment, an atomic layer deposition process is first adopted to form the first gate oxide layer 121 on the bottom and the side wall of the trench structure 11, then an in-situ water vapor generation process is adopted to form the second gate oxide layer 122 on the surface of the first gate oxide layer 121, and the first gate oxide layer 121 and the second gate oxide layer 122 together form the gate oxide layer 12; in this embodiment, an in-situ vapor generation process may be used to form an oxide layer on the bottom and the sidewall of the trench structure 11 as the gate oxide layer 12, as shown in fig. 8. Of course, in other examples, any other process that has a relatively poor Step coverage (Step coverage) and is capable of forming the gate oxide layer 12 at the bottom of the trench structure 11 with a thickness smaller than that of the gate oxide layer 12 at the sidewall of the trench structure 11 may be used to form the gate oxide layer 12, in addition to the in-situ water vapor generation process. A cross-sectional view of the transistor structure obtained in this embodiment is shown in fig. 9.

Example IV

With continued reference to fig. 9, the present invention further provides a transistor structure, which is substantially the same as that of the second embodiment, and differs from the first embodiment only in that the gate oxide layer 12 has a different structure, specifically: the gate oxide layer 12 in the second embodiment includes the first gate oxide layer 121 located at the bottom and the sidewall of the trench structure 11 and the second gate oxide layer 122 located on the surface of the first gate oxide layer 121; in this embodiment, the gate oxide layer 12 may be a one-layer oxide layer structure, and in this case, the gate oxide layer 12 is an oxide layer formed by a process with good step coverage, preferably, in this embodiment, the gate oxide layer 12 is an oxide layer formed by an atomic layer deposition process.

Example five

Referring to fig. 10, the present invention further provides a method for manufacturing a memory structure, where the method for manufacturing a memory structure includes the following steps:

1) Providing a semiconductor substrate 10, and forming a groove structure 11 in the semiconductor substrate 10; a plurality of active regions 102 are formed in the semiconductor substrate 10, and at least two trench structures 11 penetrate through each active region 102;

2) Forming a gate oxide layer 12 at the bottom and the side wall of the trench structure 11, wherein the thickness of the gate oxide layer 12 at the bottom of the trench structure 11 is smaller than the thickness of the gate oxide layer 12 at the side wall of the trench structure 11;

3) Forming a conductive layer 13 on the bottom and partial side walls of the gate oxide layer 12, wherein the top end of the conductive layer 13 is lower than the upper surface of the semiconductor substrate 10; the conductive layer 13 forms a buried gate word line 131, and an extending direction of the buried gate word line 131 intersects with an extending direction of the active region 102 at a first angle α smaller than 90 degrees;

5) Forming a source electrode 15 and a drain electrode 16 in the active region 102 of the semiconductor substrate 10 at two sides of the trench structure, wherein the drain region 16 is positioned at the middle part of the active region 102 between the trench structures 11, and the source region 15 is positioned at the side part of the active region outside the trench structure;

6) Forming a plurality of bit lines which are arranged in parallel at intervals in the semiconductor substrate, wherein the extending direction of the bit lines is intersected with the extending direction of the active region at a second angle beta smaller than 90 degrees, and is intersected with the extending direction of the embedded gate word line at a third angle gamma smaller than or equal to 90 degrees, and the third angle gamma is larger than the first angle alpha and larger than the second angle beta; the bit line is connected with the drain region of the transistor structure; the method comprises the steps of,

In step 1), referring to step S1 in fig. 10 and fig. 11, a semiconductor substrate 10 is provided, and a trench structure 11 is formed in the semiconductor substrate 10; a plurality of active regions 102 are formed in the semiconductor substrate 10, and at least two trench structures 11 penetrate through each active region 102.

As an example, a plurality of shallow trench isolation structures 101 may be formed in the semiconductor substrate 10, and the shallow trench isolation structures 101 isolate a plurality of active regions 102 in the semiconductor substrate 10. The trench structure 11 may be located within the active region 102, within the shallow trench isolation structure 101, or within the active region 102 and the shallow trench isolation structure 101.

As an example, the shape and number of the groove structures 11 may be set according to actual needs, and in fig. 11, the groove structures 11 are U-shaped grooves, and the number of the groove structures 11 is three as an example, but in an actual example, this is not a limitation.

1-1) forming a mask layer (not shown) with a window (not shown) on the surface of the semiconductor substrate 10, wherein the window corresponds to the trench structure 11 vertically; a kind of electronic device with high-pressure air-conditioning system

In step 2), referring to step S2 in fig. 10 and fig. 12 to 14, a gate oxide layer 12 is formed on the bottom and the sidewall of the trench structure 11, and the thickness d1 of the gate oxide layer 12 at the bottom of the trench structure 11 is smaller than the thickness d2 of the gate oxide layer 12 at the sidewall of the trench structure 11.

In one example, forming the gate oxide layer 12 on the bottom and the sidewalls of the trench structure 11 includes the following steps:

2-1) forming a first gate oxide layer 121 on the bottom and the side wall of the trench structure 11 by using an Atomic Layer Deposition (ALD) process, wherein the first gate oxide layer 121 at the bottom of the trench structure 11 and the first gate oxide layer 121 at the side wall of the trench structure 11 have approximately the same thickness, as shown in fig. 12; the method comprises the steps of,

2-2) forming a second gate oxide layer 122 on the surface of the first gate oxide layer 121 by using an In Situ Steam Generation (ISSG) process, wherein the thickness of the second gate oxide layer 122 at the bottom of the trench structure 11 is smaller than the thickness of the second gate oxide layer 122 at the sidewall of the trench structure 11, as shown in fig. 13.

It should be noted that, in Step 2-1), the process of forming the first gate oxide layer 121 by using an atomic layer deposition process, which has a relatively good Step coverage, and can form the first gate oxide layer 121 with approximately the same thickness at the bottom and the sidewall of the trench structure 11, may be used to implement Step 2-1).

As an example, the thickness of the first gate oxide layer 121 formed in step 2-1) may be set according to actual needs, and preferably, in this embodiment, the thickness of the first gate oxide layer 121 is between 40 angstroms and 50 angstroms.

As an example, the thickness of the second gate oxide layer 122 formed in step 2-2) may be set according to actual needs, and preferably, in this embodiment, the thickness of the second gate oxide layer 122 formed in step 2-2) and located on the sidewall of the trench structure 11 is between 80 angstroms and 100 angstroms, and the thickness of the second gate oxide layer 122 formed in step 2-2) and located on the bottom of the trench structure 11 is between 0.01 angstroms and 20 angstroms.

It should be noted that, in addition to the in-situ water vapor generation process, any other process that has a relatively poor Step coverage (Step coverage) and the thickness of the second gate oxide layer 122 that can be located at the bottom of the trench structure 11 is smaller than the thickness of the second gate oxide layer 122 that can be located at the sidewall of the trench structure 11 may be used to implement the Step 2-2) in the Step 2-2).

In yet another example, an oxide layer may be formed on the bottom and the sidewalls of the trench structure 11 as the gate oxide layer 12 by a one-step process, as shown in fig. 14. Specifically, in this embodiment, an in-situ water vapor generation process is directly adopted to form the gate oxide layer 12 on the sidewall and the bottom of the trench structure 11. Of course, in other examples, any other process that has a relatively poor Step coverage (Step coverage) and is capable of forming the gate oxide layer 12 at the bottom of the trench structure 11 to be smaller than the gate oxide layer 12 at the sidewall of the trench structure 11 may be used to implement Step 2, besides the in-situ water vapor generation process.

As an example, the thickness d1 of the gate oxide layer 12 formed at the bottom of the trench structure 11 in step 2) may be set according to actual needs, and preferably, in this embodiment, the thickness d1 of the gate oxide layer 12 at the bottom of the trench structure 11 is between 50 a and 60 a. Of course, in other examples, the thickness d1 of the gate oxide layer 12 at the bottom of the trench structure 11 may be adjusted according to the actual requirement according to the thickness d2 of the gate oxide layer 12 at the sidewall of the trench structure 11, and the difference between the thickness d1 of the gate oxide layer 12 at the bottom of the trench structure 11 and the thickness d2 of the gate oxide layer 12 at the sidewall of the trench structure 11 is not limited herein.

In step 3), referring to step S3 in fig. 10 and fig. 15 and 19, a conductive layer 13 is formed on the bottom and partial sidewall of the gate oxide layer 12, wherein the top of the conductive layer 13 is lower than the upper surface of the semiconductor substrate 10; the conductive layer 13 forms a buried gate word line 131, and an extending direction of the buried gate word line 131 intersects an extending direction of the active region 102 at a first angle α smaller than 90 degrees.

3-1) forming a conductive material layer (not shown) on the surface of the structure obtained in the step 2) and in the trench structure 11, wherein the conductive material layer fills the trench structure 11 and covers the surface of the semiconductor substrate 10;

3-2) removing the conductive material layer located on the surface of the semiconductor substrate 10 and a part of the conductive material layer located in the trench structure 11 by using a back etching process, so that the top of the conductive material layer remaining in the trench structure 11 is lower than the upper surface of the semiconductor substrate 10, and the conductive material layer remaining in the trench structure 11 is the conductive layer 13. Of course, in other examples, an etching process or a polishing process may be used to remove the conductive material layer located on the surface of the semiconductor substrate 10, and then an etching back process may be used to remove a portion of the conductive material layer located in the trench structure 11 to obtain the conductive layer 13.

In step 4), referring to step S4 in fig. 10 and fig. 16, a hole-filling insulating layer 14 is formed in the trench structure 11, and the hole-filling insulating layer 14 fills the trench structure 11.

4-1) forming a layer of insulating material (not shown) on the surface of the conductive layer 13 and the surface of the semiconductor substrate 10 within the trench structure 11;

4-2) removing the insulating material layer on the surface of the semiconductor substrate 10 by using a grinding process, wherein the insulating material layer remained in the trench structure 11 is the hole-filling insulating layer 14.

In step 5), referring to step S5 of fig. 10 and fig. 17, a source electrode 15 and a drain electrode 16 are respectively formed in the active region 102 of the semiconductor substrate 10 at both sides of the trench structure, the drain region 16 is located at a middle portion of the active region 102 between the trench structures 11, and the source region 15 is located at a side portion of the active region outside the trench structure.

In step 6), please refer to step S6 in fig. 10 and fig. 18 to 19, wherein fig. 19 is a top view of the structure obtained in the step, fig. 18 is a schematic view of a cross-sectional structure of fig. 19 along the AA direction, a plurality of bit lines 17 are formed in the semiconductor substrate 10 in parallel and spaced apart, and an extension direction of the bit lines 17 intersects an extension direction of the buried gate word lines 131 at a third angle γ smaller than or equal to 90 ° at a second angle β smaller than 90 ° with respect to an extension direction of the active regions 102; the third angle gamma is larger than the first angle alpha and larger than the second angle beta; the bit line 17 is connected to the drain region 16 of the transistor structure.

As an example, between step 5) and step 6) the following steps are also included: forming a bit line contact structure (BLC) 19 on the drain region 16 of the transistor structure, the bit line contact structure 19 being in contact with the drain region 16 of the transistor structure; the bit line 17 formed in step 6) is connected to the drain region 16 of the transistor structure via the bit line contact structure 19. The bit line contact structure 19 is a plug structure with an electrical connection function, and the material of the bit line contact structure 19 may be metal or doped polysilicon.

By way of example, the method of forming the bit lines 17 and the bit line contact structures 19 is known to those skilled in the art and will not be described here.

A dielectric layer (not shown) is formed between the bit line 17 and the semiconductor substrate 10 and between adjacent bit lines 17 to isolate the bit line 17 from the semiconductor substrate 10 and to isolate adjacent bit lines 17.

It should be further noted that, for ease of understanding and illustration, the bit line contact structure 19 is not illustrated in fig. 19.

In step 7), referring to step S7 in fig. 10 and fig. 20, a plurality of capacitor structures 18 are formed on the semiconductor substrate 10, and the capacitor structures 18 are connected to the source regions 15 of the transistor structures.

As an example, between step 6) and step 7) the following steps are also included: forming a storage node contact Structure (SNC) 20 in the source region 15 of the transistor structure, the storage node contact structure 20 being in contact with the source region 15 of the transistor structure; the capacitor structure 18 formed in step 7) is connected to the source region 15 of the transistor structure via the storage node contact structure 20. The storage node contact structure 20 is a plug structure with an electrical connection function, and the material of the storage node contact structure 20 may be metal or doped polysilicon.

A dielectric layer (not shown) is formed between the storage node contact structures 20 and between the capacitor structures 18 to isolate the adjacent storage node contact structures 20 from the adjacent capacitor structures 18.

By way of example, the method of forming the storage node contact structure 20 and the capacitor structure 18 is known to those skilled in the art and will not be described again here.

Example six

With continued reference to fig. 20 in conjunction with fig. 10 to 19, the present invention further provides a memory structure that can be manufactured by, but not limited to, the manufacturing method described in the fifth embodiment, the memory structure comprising: a semiconductor substrate 10, wherein a plurality of trench structures 11 positioned in the semiconductor substrate 10 are arranged in the semiconductor substrate 10, and a plurality of active areas 102 isolated by shallow trench isolation structures 101 are formed in the semiconductor substrate 10; a gate oxide layer 12, wherein the gate oxide layer 12 is located at the bottom and the side wall of the trench structure 11, and the thickness of the gate oxide layer 12 located at the bottom of the trench structure 11 is smaller than the thickness of the gate oxide layer 12 located at the side wall of the trench structure 11; a conductive layer 13, wherein the conductive layer 13 is located at the bottom and partial side wall of the gate oxide layer 12, and the top end of the conductive layer 13 is lower than the upper surface of the semiconductor substrate 10; the conductive layer 13 is used for embedding the gate word line 131, and the extending direction of the embedded gate word line 131 and the extending direction of the active region 102 intersect at a first angle alpha smaller than 90; and a hole filling insulating layer 14, wherein the hole filling insulating layer 14 is filled in the groove structure 11 and fills the groove structure 11; wherein, an active region 15 and a drain electrode 16 are also formed in the semiconductor substrate 10, the source region 15 is located in the semiconductor substrate 10 at one side of the trench structure 11, and the drain electrode 16 is located in the semiconductor substrate 10 at the other side of the trench structure 11; a plurality of bit lines 17 arranged in parallel at intervals, wherein an extending direction of the bit lines 17 intersects an extending direction of the active region 102 at a second angle β smaller than 90 degrees, and an extending direction of the bit lines 17 intersects an extending direction of the buried gate word lines 131 at a third angle γ smaller than or equal to 90 degrees; the third angle gamma is larger than the first angle alpha and larger than the second angle beta; the bit line 17 is connected with the drain region 16 of the transistor structure; and, a number of capacitor structures 18, the capacitor structures 18 being connected with the source regions 15 of the transistor structures.

As an example, the shape and number of the groove structures 11 may be set according to actual needs, and in fig. 19, the groove structures 11 are U-shaped grooves, and the number of the groove structures 11 is three as an example, but in an actual example, this is not a limitation.

In one example, the gate oxide layer 12 includes: a first gate oxide layer 121, where the first gate oxide layer 121 is located at the bottom and the side wall of the trench structure 11, and the first gate oxide layer 121 located at the bottom of the trench structure 11 and the first gate oxide layer 121 located at the side wall of the trench structure 11 have approximately the same thickness; and a second gate oxide layer 122, where the second gate oxide layer 122 is located on the surface of the first gate oxide layer 121, and the thickness of the second gate oxide layer 122 located at the bottom of the trench structure 11 is smaller than the thickness of the second gate oxide layer 122 located at the sidewall of the trench structure 11.

In another example, the gate oxide layer 12 may be an oxide layer, where the gate oxide layer 12 is an oxide layer formed by a step coverage rate better process, and in this embodiment, the gate oxide layer 12 is preferably an oxide layer formed by an atomic layer deposition process.

As an example, the memory structure further comprises a bit line contact structure 19, the bit line contact structure 19 being located between the bit line 17 and the drain region 16 of the transistor structure and connecting the bit line 17 with the drain region 16 of the transistor structure.

As an example, the memory structure further comprises a storage node contact structure 20, the storage node contact structure 20 being located between the capacitor structure 18 and the source region 15 of the transistor structure and connecting the capacitor structure 18 with the source region 15 of the transistor structure.

In summary, the present invention provides a transistor structure, a memory structure and a method for manufacturing the same, wherein the transistor structure includes the following steps: 1) Providing a semiconductor substrate, and forming a groove structure in the semiconductor substrate; 2) Forming a first gate oxide layer on the bottom and the side wall of the groove structure by adopting an atomic layer deposition process, wherein the first gate oxide layer at the bottom of the groove structure and the first gate oxide layer at the side wall of the groove structure have the same thickness; 3) Forming a second gate oxide layer on the surface of the first gate oxide layer by adopting an in-situ water vapor generation process, wherein the thickness of the second gate oxide layer positioned at the bottom of the groove structure is smaller than that of the second gate oxide layer positioned on the side wall of the groove structure; the first gate oxide layer and the second gate oxide layer form a gate oxide layer with a double-layer structure together; 4) Forming a conductive layer on the bottom and partial side wall of the gate oxide layer, wherein the top end of the conductive layer is lower than the upper surface of the semiconductor substrate; 5) Forming a hole filling insulating layer in the groove structure, wherein the groove structure is filled with the hole filling insulating layer; and 6) forming a source region and a drain region in the semiconductor substrate at two sides of the groove structure respectively. According to the transistor structure, the gate oxide layer is arranged to be of the structure that the thickness of the gate oxide layer at the bottom of the groove structure is smaller than that of the gate oxide layer at the side wall of the groove structure, so that the gate induced drain leakage current can be remarkably reduced, and the overall performance of a device is further improved.

The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims

1. A method of fabricating a transistor structure, the transistor structure comprising the steps of:

2. The method of claim 1, wherein the first gate oxide layer formed in step 2) has a thickness of between 40 angstroms and 50 angstroms; the thickness of the second gate oxide layer formed in the step 3) and located on the side wall of the groove structure is 80-100 angstroms; the thickness of the second gate oxide layer formed at the bottom of the trench structure in the step 3) is between 0.01 and 20 angstroms.

3. The method of claim 1 or 2, wherein the gate oxide layer formed at the bottom of the trench structure after step 3) has a thickness of 50 a to 60 a.

4. A transistor structure, the transistor structure comprising:

a semiconductor substrate having a trench structure within the semiconductor substrate and a material of the semiconductor substrate comprising a monocrystalline or polycrystalline semiconductor material;

A first gate oxide layer located at the bottom and side wall of the trench structure and located at the bottom of the trench structure

The first gate oxide layer and the first gate oxide layer positioned on the side wall of the groove structure have the same thickness;

the second gate oxide layer is positioned on the surface of the first gate oxide layer, and the thickness of the second gate oxide layer positioned at the bottom of the groove structure is smaller than that of the second gate oxide layer positioned on the side wall of the groove structure; the first gate oxide layer and the second gate oxide layer form a gate oxide layer with a double-layer structure together;

5. The structure of claim 4 wherein the thickness of the second gate oxide layer at the bottom of the trench structure is also less than the thickness of the first gate oxide layer at the bottom of the trench structure.

6. The structure of claim 4 wherein said first gate oxide layer has a thickness of between 40 and 50 angstroms, said second gate oxide layer on said trench structure sidewall has a thickness of between 80 and 100 angstroms, and said second gate oxide layer on said trench structure bottom has a thickness of between 0.01 and 20 angstroms.

7. The structure of any of claims 4-6 wherein the gate oxide layer at the bottom of the trench structure has a thickness of between 50 angstroms and 60 angstroms.

8. A method of fabricating a memory structure, the method comprising:

2) Forming a gate oxide layer at the bottom and the side wall of the groove structure, wherein the gate oxide layer comprises a first gate oxide layer formed at the bottom and the side wall of the groove structure by adopting an atomic layer deposition process, and the first gate oxide layer at the bottom of the groove structure and the first gate oxide layer at the side wall of the groove structure have the same thickness; forming a second gate oxide layer on the surface of the first gate oxide layer by adopting an in-situ water vapor generation process, wherein the thickness of the second gate oxide layer positioned at the bottom of the groove structure is smaller than that of the second gate oxide layer positioned on the side wall of the groove structure;

9. The method of claim 8, wherein the first gate oxide layer is formed to a thickness of between 40 angstroms and 50 angstroms; the thickness of the formed second gate oxide layer positioned on the side wall of the groove structure is 80-100 angstroms; the thickness of the second gate oxide layer formed at the bottom of the trench structure is between 0.01 and 20 angstroms.

10. The method of claim 8, further comprising the steps of, between step 5) and step 6):

forming a bit line contact structure in the drain region of the transistor structure, wherein the bit line contact structure is contacted with the drain region of the transistor structure; the bit line formed in step 6) is connected to the drain region of the transistor structure via the bit line contact structure.

11. The method of claim 8, further comprising the steps of, between step 6) and step 7):

forming a storage node contact structure in a source region of the transistor structure, wherein the storage node contact structure is contacted with the source region of the transistor structure; the capacitor structure formed in step 7) is connected to the source region of the transistor structure via the storage node contact structure.

12. The method of any one of claims 8 to 11, wherein the gate oxide layer formed in step 2) at the bottom of the trench structure has a thickness of between 50 a and 60 a.

13. A memory structure, the memory structure comprising:

the semiconductor substrate is provided with a plurality of groove structures positioned in the semiconductor substrate, a plurality of active areas are formed in the substrate, at least two groove structures penetrate through each active area, and the material of the semiconductor substrate comprises monocrystalline or polycrystalline semiconductor material;

the gate oxide layer is positioned at the bottom and the side wall of the groove structure, the thickness of the gate oxide layer positioned at the bottom of the groove structure is smaller than that of the gate oxide layer positioned at the side wall of the groove structure, the gate oxide layer comprises a first gate oxide layer, the first gate oxide layer positioned at the bottom and the side wall of the groove structure, and the first gate oxide layer positioned at the bottom of the groove structure and the first gate oxide layer positioned at the side wall of the groove structure have approximately the same thickness; the second gate oxide layer is positioned on the surface of the first gate oxide layer, and the thickness of the second gate oxide layer positioned at the bottom of the groove structure is smaller than that of the second gate oxide layer positioned on the side wall of the groove structure;

14. The structure of claim 13 wherein the thickness of the second gate oxide layer at the bottom of the trench structure is also less than the thickness of the first gate oxide layer at the bottom of the trench structure.

15. The structure of claim 13 wherein said first gate oxide layer has a thickness of between 40 and 50 angstroms, said second gate oxide layer on said trench structure sidewall has a thickness of between 80 and 100 angstroms, and said second gate oxide layer on said trench structure bottom has a thickness of between 0.01 and 20 angstroms.

16. The structure of claim 13, wherein the memory structure further comprises a bit line contact structure between and connecting the bit line and the drain region of the transistor structure.

17. The structure of claim 13, wherein the memory structure further comprises a storage node contact structure located between and connecting the capacitor structure and a source region of the transistor structure.

18. The structure of any of claims 13-17 wherein the gate oxide layer at the bottom of the trench structure has a thickness of between 50 a and 60 a.