CN112490246B

CN112490246B - Semiconductor device and method for manufacturing the same

Info

Publication number: CN112490246B
Application number: CN202011230844.7A
Authority: CN
Inventors: 薛磊; 刘威; 陈亮
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2020-11-06
Filing date: 2020-11-06
Publication date: 2024-04-05
Anticipated expiration: 2040-11-06
Also published as: CN112490246A

Abstract

The invention provides a semiconductor device and a preparation method thereof, wherein the semiconductor device comprises a semiconductor substrate, a dielectric layer, a contact element and a metal interconnection layer; the semiconductor substrate comprises a transistor and a shallow trench isolation structure; the contact element penetrates through the dielectric layer and comprises a first contact element and a second contact element which are contacted with the same shallow trench isolation structure, so that a capacitor is formed by the first contact element and the second contact element; the metal interconnection layer is positioned on the dielectric layer and is electrically connected with the contact element. The invention can increase the capacitance of the capacitor and expand the application range of the semiconductor device on the premise of not changing the size of the semiconductor device.

Description

Semiconductor device and method for manufacturing the same

Technical Field

The invention belongs to the technical field of semiconductors, and relates to a semiconductor device and a preparation method thereof.

Background

Existing Charge pumps (Charge pumps), also known as switched capacitor voltage converters, are converters that use so-called "fast" or "pumping" capacitors to store energy, mainly in applications including MOS (metal-oxide-silicon) capacitors and MOM (metal-oxide-metal) capacitors, which however generally require a large wafer area.

Taking 3D NAND as an example, 3D NAND is a technology of increasing capacity by vertically stacking memory cells to obtain higher storage density. In 3D NAND technology, the memory cell operates at a high voltage, so a capacitor is required to implement the voltage boosting. In the conventional 3D NAND architecture, the peripheral circuit (peripheral) and the stacked memory Array (Array) are usually fabricated on the same wafer, so that in such a 3D NAND architecture, the peripheral circuit may have enough space to form a capacitor with a larger plate area, so that a sufficient capacitance may be provided to meet the application requirements, and thus the technical problem of preparing a high-density, high-capacitance capacitor in the conventional 3D NAND architecture is not considered excessively. However, with the development of semiconductor technology, the preparation of integrated circuits with lower cost, faster and higher integration has become the target pursued by the existing semiconductor technology, so that the conventional large-sized 3D NAND architecture is no longer suitable for the development requirement, and similarly, the existing structure of the capacitor prepared by occupying a larger wafer area is no longer suitable for the development requirement, and how to prepare a high-density and high-capacitance capacitor in a limited space to meet the development trend of semiconductor devices has become an urgent problem to be solved.

Therefore, it is necessary to provide a novel semiconductor device and a method for manufacturing the same.

Disclosure of Invention

In view of the above-described drawbacks of the prior art, an object of the present invention is to provide a semiconductor device and a method for manufacturing the same, which solve the problem that it is difficult to form a capacitor with high capacitance over a limited wafer area in the prior art.

To achieve the above and other related objects, the present invention provides a semiconductor device comprising:

the semiconductor substrate comprises a transistor and a shallow trench isolation structure;

a dielectric layer on the semiconductor substrate, wherein the dielectric layer covers the transistor and the shallow trench isolation structure;

a contact element penetrating the dielectric layer, the contact element comprising at least one first contact element and at least one second contact element in contact with the same shallow trench isolation structure to form a capacitor through the first contact element and the second contact element;

and the metal interconnection layer is positioned on the dielectric layer and is electrically connected with the contact element.

Optionally, the aspect ratio of the contact element ranges from 200:1 to 2500:1.

Optionally, on the same shallow trench isolation structure, N capacitors are included, where N is a positive integer and N is greater than or equal to 2.

Optionally, the capacitors on the same shallow trench isolation structure are arranged in parallel along the X direction of the shallow trench isolation structure.

Optionally, the aspect ratio of the contact element ranges from 1:1 to 20:1. Optionally, on the same shallow trench isolation structure, along an X direction of the shallow trench isolation structure, X capacitors are included, along a Y direction of the shallow trench isolation structure, Y capacitors are included, and X and Y capacitors are perpendicular to each other, wherein X and Y are positive integers, and at least one of X and Y is greater than 1.

Optionally, the capacitors on the same shallow trench isolation structure are staggered.

Optionally, the capacitor comprises one or a combination of a parallel connection or a series connection.

The present invention also provides a semiconductor device including:

a first wafer, the first wafer comprising:

a metal interconnect layer on the dielectric layer, the metal interconnect layer electrically connected to the contact element;

a second wafer comprising a functional array layer and an array interconnect layer electrically connected to the functional array layer;

wherein the metal interconnect layer is electrically connected with the array interconnect layer.

Optionally, the aspect ratio of the contact element ranges from 200:1 to 2500:1 or from 1:1 to 20:1.

The invention also provides a preparation method of the semiconductor device, which comprises the following steps:

providing a semiconductor substrate, wherein the semiconductor substrate comprises a transistor and a shallow trench isolation structure;

forming a dielectric layer on the semiconductor substrate, and etching the dielectric layer to form a contact hole penetrating to the shallow trench isolation structure;

filling the contact hole to form a contact element, wherein the contact element comprises at least one first contact element and at least one second contact element which are contacted with the same shallow trench isolation structure so as to form a capacitor through the first contact element and the second contact element;

a metal interconnect layer is formed over the dielectric layer and electrically connected to the contact element.

Optionally, the contact elements are formed with an aspect ratio ranging from 200:1 to 2500:1 or from 1:1 to 20:1.

As described above, the semiconductor device and the method for manufacturing the same according to the present invention include a transistor and a shallow trench isolation structure in a semiconductor substrate, a dielectric layer is formed on the semiconductor substrate, a contact element is formed in the dielectric layer, and the contact element includes a first contact element and a second contact element that are in contact with the same shallow trench isolation structure, so as to form a capacitor through the first contact element and the second contact element, and a metal interconnection layer is formed on the dielectric layer. On the premise of not changing the size of the semiconductor device, the first contact element and the second contact element with smaller spacing are arranged on the shallow trench isolation structure, so that the spacing of the capacitor can be effectively reduced, and the capacitance can be increased; the area of the capacitor can be effectively increased by increasing the areas of the first contact element and the second contact element which are positioned on the shallow trench isolation structure, so that the capacitance is increased; by increasing the number of contact elements on the shallow trench isolation structure, the distribution density of the capacitor can be increased to increase the capacitance; the communication of the capacitor can be flexibly controlled through the metal interconnection layer, so that the application range of the semiconductor device is widened.

Drawings

Fig. 1 shows a schematic cross-sectional structure of the 3D NAND in the comparative example.

Fig. 2 is an enlarged schematic view of the area a in fig. 1.

Fig. 3 is a schematic diagram showing a cross-sectional structure of the 3D NAND in the embodiment.

Fig. 4 is an enlarged schematic view of the area a' in fig. 3.

Fig. 5a to 5c are schematic views of three different enlarged structures of the region B in fig. 4.

Fig. 6 is a schematic view showing a process flow for manufacturing a semiconductor device according to the present invention.

Description of element reference numerals

10. 10' first wafer

11. 11' metal interconnect layer

20. 20' second wafer

21. 21' array interconnect layer

22. 22' functional array layer

100. 110 semiconductor substrate

101. 111 semiconductor substrate

102. 112 transistor

1021. 1121 source electrode

1022. 1122 drain electrode

1023. 1123 gate structure

103. 113 shallow trench isolation structure

104. 114 passivation layer

200. 210 first dielectric layer

300. 310 contact element

301. 311 first contact element

302. 312 second contact element

400. 410 a second dielectric layer

500. 510 metal layer

501. 511 first metal layer

502. 512 second metal layer

600. 610 metal plug

a. Distance b

A. Regions A', B

H height

D1, D2, D3 spacing

Width of W1, W2, W3

Length of L1, L2, L3

Detailed Description

Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.

As described in detail in the embodiments of the present invention, the cross-sectional view of the device structure is not partially enlarged to a general scale for convenience of explanation, and the schematic drawings are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.

For ease of description, spatially relative terms such as "under", "below", "beneath", "above", "upper" and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Furthermore, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers or one or more intervening layers may also be present. As used herein, "between … …" is meant to include both endpoints.

In the context of this application, a structure described as a first feature being "on" a second feature may include embodiments where the first and second features are formed in direct contact, as well as embodiments where additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be changed at will, and the layout of the components may be more complex.

Comparative example

In the comparative example, a semiconductor device is exemplified by 3D NAND, as shown in fig. 1, which is a schematic structural diagram of the 3D NAND in the present comparative example, wherein the 3D NAND has a first wafer 10 and a second wafer 20, the first wafer 10 includes a metal interconnection layer 11, the second wafer 20 includes an array interconnection layer 21 and a functional array layer 22, and the 3D NAND is electrically connected to the metal interconnection layer 11 and the array interconnection layer 21 through a bonding process, thereby achieving the electrical connection of the first wafer 10 and the second wafer 20 to perform circuit control of the second wafer 20 through the first wafer 10.

It should be noted that, in fig. 1, only a part of the device structure is illustrated in the edge region of the first wafer 10 for simplicity of illustration, but it is understood that the entire first wafer 10 has the elements such as the transistor, the contact element, the metal interconnection layer, the shallow trench isolation structure, etc., and the specific elements and the distribution thereof may be selected and arranged according to the needs.

Specifically, since the conventional 3D NAND is to make the peripheral circuit (peripheral) and the stacked memory Array (Array) on the same wafer, in this comparative example, in order to reduce the device size, improve the integration level and improve the device quality, the peripheral circuit and the stacked memory Array are respectively made on different wafers, and the peripheral circuit and the stacked memory Array are electrically connected through a bonding process.

Referring to fig. 2, an enlarged schematic view of the area a of the first wafer 10 is shown, wherein the specific structure and preparation method of the second wafer 20 are described in the prior art, and the first wafer 10 may be applied to other semiconductor devices as needed, which is not limited herein.

The first wafer 10 includes a semiconductor substrate 100, a first dielectric layer 200, a contact element 300, and the metal interconnection layer 11. The semiconductor base 100 includes a semiconductor substrate 101, a transistor 102, a shallow trench isolation structure 103, and a passivation layer 104, and the transistor 102 includes a source 1021, a drain 1022, and a gate structure 1023, the transistor 102 may be a CMOS transistor, but is not limited thereto; the metal interconnection layer 11 includes the second dielectric layer 400, the metal layer 500 and the metal plug 600, but is not limited thereto, and the metal interconnection layer 11 may include other structures. The contact element 300 includes a first contact element 301 contacting the active region and a second contact element 302 contacting the gate structure 1023, so that a capacitor is formed by the first contact element 301 and the second contact element 302, and the first contact element 301 and the second contact element 302 are electrically connected to the outside, that is, the array interconnect layer 21 in the second wafer 20, through a first metal layer 501, a second metal layer 502, and a metal plug 600 located between the first metal layer 501 and the second metal layer 502 in the metal interconnect layer 11, respectively, it being understood that the first contact element 301 and the second contact element 302 form two plates of the capacitor, and that the capacitor further includes an insulating medium, that is, the first dielectric layer 200, located between the first contact element 301 and the second contact element 302.

In this case, since the contact element 300 is in contact with the active region and the gate structure 1023, it is necessary to consider the distance b between the contact element 300 and the gate structure 1023 and the overlapping distance a between the gate structure 1023 and the contact element 300 when forming the first contact element 301 and the second contact element 302, and thus it is difficult to further manufacture the capacitor having high capacitance.

In addition, as semiconductor technology advances toward higher density and higher capacity, the number of layers of the functional array layer 22 in the second wafer 20 is also increasing in the 3D NAND architecture, thereby requiring the first wafer 10 to have a denser distribution, so that the capacitors on the transistors 102 are also difficult to meet.

Furthermore, in the 3D NAND, in order to reduce the size of the 3D NAND, the first dielectric layer 200 is generally thin, so that the height of the contact element 300 is small, and thus the capacitance that the capacitor formed by the contact element 300 can provide is limited in height, thereby also limiting the feasibility of forming the capacitor with high capacitance.

Examples

To further solve the limitation of the semiconductor device in the comparative example in terms of high capacitance, the following is further improved.

Referring to fig. 3, the present embodiment provides a 3D NAND, the 3D NAND has a first wafer 10' and a second wafer 20', the first wafer 10' includes a metal interconnection layer 11', the second wafer 20' includes an array interconnection layer 21' and a functional array layer 22', and the 3D NAND is electrically connected to the metal interconnection layer 11' and the array interconnection layer 21' through a bonding process, so as to electrically connect the first wafer 10' and the second wafer 20', so as to control the circuit of the second wafer 20' through the first wafer 10 '.

It should be noted that, in fig. 3, only a part of the device structure is illustrated in the edge region of the first wafer 10 'for simplicity of illustration, but it is understood that the transistor, the contact element, the metal interconnection layer, the shallow trench isolation structure, etc. are all included in the first wafer 10', the specific distribution may be set according to needs, and the specific electrical connection manner between the contact element and the metal interconnection layer 11 'in the first wafer 10' in illustration may be selected according to needs, and only the contact element located on the same shallow trench isolation structure may be required to form a capacitor, and the specific electrical connection manner is not limited herein.

Referring to fig. 4, an enlarged schematic view of the area a 'of the first wafer 10' is shown, wherein the specific structure and preparation method of the second wafer 20 'are not described herein, and the first wafer 10' may be applied to other semiconductor devices as needed in another example, without being excessively limited thereto.

Wherein the first wafer 10' comprises:

a semiconductor substrate 110, wherein the semiconductor substrate 110 includes a transistor 112 and a shallow trench isolation structure 113;

a dielectric layer on the semiconductor substrate 110, wherein the dielectric layer covers the transistor 112 and the shallow trench isolation structure 113;

a contact element 310, the contact element 310 penetrating the dielectric layer, and the contact element 310 comprising at least one first contact element 311 and at least one second contact element 312 in contact with the same shallow trench isolation structure 113, such that a capacitor is constituted by the first contact element 311 and the second contact element 312;

a metal interconnect layer 11', the metal interconnect layer 11' being located on the dielectric layer, and the metal interconnect layer 11' being electrically connected to the contact element 310.

Specifically, the semiconductor base 110 includes a semiconductor substrate 111, a transistor 112, a shallow trench isolation structure 113, and further may further include a passivation layer 114, and the transistor 112 includes a source 1121, a drain 1122, and a gate structure 1123, and the transistor 112 may be a CMOS transistor, but is not limited thereto; the dielectric layer is a first dielectric layer 210; the metal interconnect layer 11' includes a second dielectric layer 410, a metal layer 510, and a metal plug 610. The specific structure and type of the semiconductor substrate 110 and the metal interconnection layer 11' are not excessively limited herein. The contact element 310 includes the first contact element 311 and the second contact element 312 that are in contact with the same shallow trench isolation structure 113, so that the first contact element 311 and the second contact element 312 form the capacitor, and it can be understood that the first contact element 311 and the second contact element 312 form two plates of the capacitor, and the capacitor further includes the first dielectric layer 210 that is an insulating medium between the first contact element 311 and the second contact element 312. Further, the contact element 310 further includes a contact element disposed on the transistor 112 and electrically connected to the gate structure 1123 and the active region of the transistor 112, respectively. Wherein the contact element 310 is electrically connected to the metal interconnection layer 11', so that the contact element 310 and the array interconnection layer 21' in the second wafer 20' can be connected through the metal interconnection layer 11' to perform circuit control on the second wafer 20 '.

In this embodiment, the contact element 310 is disposed on the shallow trench isolation structure 113 without considering the problem of the locations of the contact element 310 and the transistor 112, and the size of the contact element 310 is limited only by the precision of the etching process, so that the pitch of the first contact element 311 and the second contact element 312 can be effectively reduced to form the capacitor with smaller pitch to increase the capacitance.

As an example, in the capacitor, a space D1 is provided between the first contact element 311 and the second contact element 312, and the range of the space D1 is 0.1 μm to 0.15 μm.

Specifically, referring to FIG. 5a, an enlarged top view of the area B of FIG. 4 is shown. Wherein, according to the principle of the capacitor, when the distance D1 between the first contact element 311 and the second contact element 312 is smaller, the capacitance of the capacitor can be increased. Further, when the distance D1 is smaller, the number of the contact elements 310 may be increased in a limited area to increase the distribution density of the capacitor, so as to expand the application range of the semiconductor device. The range of the distance D1 may include any value ranging from 0.1 μm to 0.15 μm, such as 0.12 μm, 0.14 μm, etc., which is not limited herein.

As an example, the range of the area S between the first contact element 311 and the second contact element 312 includes 0.01 μm ² ～100μm ² 。

Specifically, according to the principle of the capacitor, as the area S facing between the first contact member 311 and the second contact member 312 is larger, the capacitance of the capacitor may be increased. To avoid increasing the size of the semiconductor device, the size of the contact element 310 is related to the size of the shallow trench isolation structure 113 and the thickness of the first dielectric layer 210, and in this embodiment, the range of the area S may include 1 μm ² 、10μm ² 、50μm ² 、100μm ² And the like, and may be specifically selected as desired.

By way of example, the contact elements 310 are formed with an aspect ratio in the range of 1:1 to 2500:1, preferably 200:1 to 2500:1 or 1:1 to 20:1.

In particular, the contact element 310 includes a square morphology with an aspect ratio of 1:1, but may also include a rectangular morphology, which may be selected as desired.

Wherein the range of the length of the first contact element 311 and the second contact element 312 is 0.05 μm to 100 μm.

Specifically, in the embodiment, referring to fig. 5a, the first contact element 311 and the second contact element 312 adopt a wall shape, wherein the range of the length L1 of the first contact element 311 and the second contact element 312 may include 0.05 μm to 100 μm. In this embodiment, since the wall morphology is adopted, it is preferable to have a larger value of the length L1, such as 10 μm, 25 μm, 50 μm, 80 μm, 100 μm, etc., within 10 μm to 100 μm in order to increase the capacitance of the capacitor, but not limited thereto. As shown in fig. 5b and 5c, the shape of the contact element 310 is rectangular, and the lengths L2 and L3 are smaller than the length L1, for example, the lengths L2 and L3 may take values within 0.05 μm, 0.1 μm, 0.2 μm, 0.5 μm, 0.8 μm, etc. from 0.05 μm to 1.0 μm, so as to increase the distribution density of the capacitor and increase the capacitance by providing the contact element 310 with a smaller size,

the range of the widths of the first contact element 311 and the second contact element 312 is 40nm to 50nm.

Specifically, when the width of the contact element 310 is smaller, the number of the contact elements 310 may be increased in a limited area to increase the distribution density of the capacitor, but the width of the contact element 310 is also affected by the etching process, so that in this embodiment, the value of the width of the contact element 310 may be a point value in any range of 45nm, 48nm, 50nm, etc., which is not limited excessively.

As in fig. 5a, since the contact element 310 adopts the length L1 having a larger value to increase the capacitance by increasing the area S of the capacitor, the aspect ratio of the contact element 310 is preferably in any value in the range of 200:1 to 2500:1. In order to increase the capacitance, as shown in fig. 5b and 5c, a plurality of capacitors having small dimensions may be provided, for example, the length ratio of the contact element 310 may be any value in the range of 1:1 to 20:1, so as to increase the number of capacitors.

As an example, the same shallow trench isolation structure 113 includes N first contact elements 311 and second contact elements 312 correspondingly disposed thereon to form N capacitors, where N is a positive integer and N is greater than or equal to 2.

Specifically, referring to fig. 5a, in this embodiment, 2 first contact elements 311 and second contact elements 312 are respectively included and alternately arranged, so that 2 capacitors with a parallel arrangement may be formed, but the number of the first contact elements 311 and the second contact elements 312 is not limited thereto, in another embodiment, only 1 first contact element 311 and second contact element 312, or a plurality of first contact elements 311 and second contact elements 312, such as 3, 4, 5, etc. are correspondingly arranged, and the arrangement of the capacitors in this embodiment is preferably suitable for the contact elements 310 with a larger aspect ratio, but it is understood that the arrangement of the capacitors with a larger aspect ratio in the range of 200:1 to 2500:1 may be adopted according to the need, or the arrangement of the capacitors in the embodiment may be excessively limited according to the need, such as the arrangement of fig. 5b and 5c, or the other arrangement of the capacitors may be excessively limited.

As an example, on the same shallow trench isolation structure 113, along the X direction of the shallow trench isolation structure 113, X first contact elements 311 and second contact elements 312 are correspondingly disposed, and along the Y direction of the shallow trench isolation structure 113, Y first contact elements 311 and second contact elements 312 are correspondingly disposed, wherein X and Y are both positive integers, and at least one of X and Y is greater than 1.

Specifically, referring to fig. 5b, on the same shallow trench isolation structure 113, the first contact element 311 and the second contact element 312 are correspondingly disposed along the X direction of the shallow trench isolation structure 113, and the first contact element 311 and the second contact element 312 are correspondingly disposed along the Y direction of the shallow trench isolation structure 113, wherein X and Y are perpendicular to each other, but the value of X and Y can be set as required. Wherein, the range of the width W2 can be 40 nm-50 nm, the range of the length L2 can be 0.05 μm-100 μm, preferably 0.05 μm-1.0 μm, and the range of the distance D2 can be 0.1 μm-0.15 μm. In fig. 5b, the distance D2 may be equal to D1 and the width W2 may be equal to W1, but in fig. 5b, the shape of the contact element 310 is rectangular, i.e. the length L2 is smaller than the length L1, for example, the length L2 may be equal to 0.05 μm, 0.1 μm, 0.2 μm, 0.5 μm, or 0.8 μm, so as to increase the distribution density of the capacitor by the smaller length L2, so as to expand the application range of the capacitor, but the values of D2, W2, and L2 and the values of x and y are not limited thereto. In the present embodiment, the plurality of capacitors are formed in parallel, but not limited thereto.

Further, as an example, the capacitors formed by the first contact element 311 and the second contact element 312 are staggered.

Specifically, referring to fig. 5c, the capacitors formed on the same shallow trench isolation structure 113 are arranged in a staggered manner. Wherein, the range of the width W3 can be 40 nm-50 nm, the range of the length L3 can be 0.05 μm-100 μm, preferably 0.05 μm-1.0 μm, and the range of the distance D3 can be 0.1 μm-0.15 μm. In this embodiment, the distribution density of the capacitor can be further increased compared to fig. 5b to further expand the application area of the capacitor, but the values of D3, W3, and L3 and the values in the X and Y directions are not limited thereto.

As an example, one or a combination of parallel connection or series connection is included between a plurality of the capacitors.

Specifically, according to specific needs, the capacitor on the same shallow trench isolation structure 113 may be controlled by the metal interconnection layer 11' to include one or a combination of parallel connection and serial connection, so as to further expand the application range of the semiconductor device, and the specific connection mode may be selected according to needs, so that the application principle of the capacitor is only required to be satisfied without being excessively limited.

As an example, the range of the height H of the first contact element 311 and the second contact element 312 includes 0.2 μm to 1.0 μm.

Specifically, the larger the range of the height H of the first contact element 311 and the second contact element 312, the more advantageous is to increase the effective area of the capacitor, so that the capacitance of the capacitor can be increased, but the increase of the height H will definitely increase the size of the semiconductor device, so in this embodiment, the value of the height H of the first contact element 311 and the second contact element 312 is preferably, for example, 0.4 μm, 0.5 μm, 0.6 μm, 0.8 μm, etc., so as to reduce the size of the semiconductor device, but the range of the height H is not limited thereto, and may be specifically selected according to the needs.

Referring to fig. 3 and 6, the present embodiment also provides a method for manufacturing a semiconductor device, which can be used to manufacture the semiconductor device, but the method for manufacturing the semiconductor device is not limited thereto, and the structure of the semiconductor device is not described herein. The preparation method of the semiconductor device specifically comprises the following steps:

providing a semiconductor substrate 110, wherein the semiconductor substrate 110 comprises a transistor 112 and a shallow trench isolation structure 113;

forming a dielectric layer on the semiconductor substrate 110, and etching the dielectric layer to form a contact hole (not shown) penetrating to the shallow trench isolation structure;

filling the contact hole to form a contact element 310, wherein the contact element 310 comprises a first contact element 311 and a second contact element 312 which are contacted with the same shallow trench isolation structure 113, so that a capacitor is formed by the first contact element 311 and the second contact element 312;

a metal interconnect layer 11 'is formed on the dielectric layer, and the metal interconnect layer 11' is electrically connected with the contact element 310.

Specifically, referring to fig. 3 to 5c, the surface of the transistor 112 may include a passivation layer 114, and the passivation layer 114 may be made of SiN, for example; the dielectric layer includes the first dielectric layer 210 and the second dielectric layer 410, and materials of the dielectric layer may be BCB, silicon oxide, TEOS, etc.; the materials of the first contact element 311 and the second contact element 312 may be Cu metal, W metal, etc., and the specific materials are not limited herein.

As an example, in the capacitor, the range of the distance between the first contact element 311 and the second contact element 312 is 0.1 μm to 0.15 μm, and the first contact element 311 and the second contact element 312 are formedThe range of values for the area between elements 312 includes 0.01 μm ² ～100μm ² 。

As an example, the aspect ratio of the contact element 310 is formed in a range including 200:1 to 2500:1 or 1:1 to 20:1; the length of the contact member 310 is formed to have a value ranging from 0.05 μm to 100 μm, preferably from 0.05 μm to 1.0 μm and from 10 μm to 100 μm; the width of the contact element 310 is formed to have a range of values from 40nm to 50nm.

As an example, the range of values for the height of the contact element 310 formed includes 0.2 μm to 1.0 μm.

As an example, the number of capacitors formed on the same shallow trench isolation structure 113 includes N, where N is a positive integer and N.gtoreq.2.

As an example, the capacitors on the same shallow trench isolation structure 113 are arranged in parallel along the X direction of the shallow trench isolation structure 113.

As an example, on the same shallow trench isolation structure 113, X capacitors are included along the X direction of the shallow trench isolation structure 113, Y capacitors are included along the Y direction of the shallow trench isolation structure 113, X and Y are perpendicular to each other, where X and Y are positive integers, and at least one of X and Y is greater than 1.

As an example, the capacitors on the same shallow trench isolation structure 113 are staggered.

As an example, the capacitor comprises one or a combination of a parallel connection or a series connection.

As an example, referring to fig. 3, the steps of:

providing a second wafer 20', the second wafer 20' comprising a functional array layer 22' and an array interconnect layer 21' electrically connected to the functional array layer 22 ';

the metal interconnection layer 11 'is bonded to the array interconnection layer 21' so that the array interconnection layer 21 'is electrically connected to the metal interconnection layer 11'.

Wherein the contact element 310 is electrically connected to the metal interconnection layer 11', so that the contact element 310 and the array interconnection layer 21' in the second wafer 20' can be connected through the metal interconnection layer 11' to perform circuit control on the second wafer 20 '.

In summary, the semiconductor device and the method for manufacturing the same according to the present invention include a transistor and a shallow trench isolation structure in a semiconductor substrate, a dielectric layer is formed on the semiconductor substrate, a contact element is formed in the dielectric layer, and the contact element includes a first contact element and a second contact element that are in contact with the same shallow trench isolation structure, so as to form a capacitor through the first contact element and the second contact element, and a metal interconnection layer is formed on the dielectric layer. On the premise of not changing the size of the semiconductor device, the first contact element and the second contact element with smaller spacing are arranged on the shallow trench isolation structure, so that the spacing of the capacitor can be effectively reduced, and the capacitance can be increased; the area of the capacitor can be effectively increased by increasing the areas of the first contact element and the second contact element which are positioned on the shallow trench isolation structure, so that the capacitance is increased; by increasing the number of contact elements on the shallow trench isolation structure, the distribution density of the capacitor can be increased to increase the capacitance; the communication of the capacitor can be flexibly controlled through the metal interconnection layer, so that the application range of the semiconductor device is widened.

The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, the semiconductor device comprising:

2. The semiconductor device according to claim 1, wherein: the aspect ratio of the contact element ranges from 200:1 to 2500:1.

3. The semiconductor device according to claim 2, wherein: the same shallow trench isolation structure comprises N capacitors, wherein N is a positive integer and N is more than or equal to 2.

4. The semiconductor device according to claim 2, wherein: the capacitors on the same shallow trench isolation structure are arranged in parallel along the X direction of the shallow trench isolation structure.

5. The semiconductor device according to claim 1, wherein: the aspect ratio of the contact element ranges from 1:1 to 20:1.

6. The semiconductor device according to claim 5, wherein: on the same shallow trench isolation structure, along the X direction of the shallow trench isolation structure, the capacitor comprises X capacitors, along the Y direction of the shallow trench isolation structure, the capacitor comprises Y capacitors, and the capacitors are mutually perpendicular, wherein X and Y are positive integers, and at least one of X and Y is larger than 1.

7. The semiconductor device according to claim 5, wherein: the capacitors on the same shallow trench isolation structure are staggered.

8. The semiconductor device according to claim 1, wherein: the capacitor comprises one or a combination of a parallel connection or a series connection.

9. A semiconductor device, the semiconductor device comprising:

a first wafer, the first wafer comprising:

10. The semiconductor device according to claim 9, wherein: the aspect ratio of the contact element ranges from 200:1 to 2500:1 or from 1:1 to 20:1.

11. A method of manufacturing a semiconductor device, comprising the steps of:

12. The method for manufacturing a semiconductor device according to claim 11, wherein: the contact element is formed with an aspect ratio ranging from 200:1 to 2500:1 or from 1:1 to 20:1.