KR19980029372A - Method for forming wiring layer of semiconductor device - Google Patents

Abstract

This invention is described about the wiring layer formation method of a semiconductor element.

The method may include forming a first wiring layer and a first insulating layer by sequentially depositing a conductive material and an insulating material on a semiconductor substrate; Patterning the first insulating film / first wiring layer; Depositing a silicon on glass (SOG) material on the semiconductor substrate on which the patterned first insulating film / first wiring layer is formed to form a second insulating film; Etching back the second insulating film until the first insulating film is exposed; Depositing an insulating material on the semiconductor substrate to form a third insulating film; Etching a predetermined region of the third insulating film; And depositing and patterning a conductive material on the semiconductor substrate to form a second wiring layer.

That is, a parasitic capacitance formed between the first wiring layer and the second wiring layer without generating voids between the patterned first wiring layer and the second wiring layer because no SOG material is present on the first wiring layer. Since the parastic capacitance is reduced, the RC delay due to the resistance R and the capacitance C is improved.

Description

Wiring layer formation method of a semiconductor element

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a wiring layer of a semiconductor device for preventing voids from occurring in an insulating film between wiring layers.

As semiconductor devices are highly integrated, the spacing between wiring layers is also decreasing.

In addition, an insulating film is formed between the wiring lines to achieve flatness in the multi-layer wiring structure. The insulating film is formed by chemical vapor deposition (CVD) on top and bottom of an oxide film / silicon on glass (SOG) structure, that is, a silicon on glass (SOG) material. ) Has a multilayer structure in which the oxide film is formed.

The SOG material includes a polymer such as Hydrogen Siliquioxane (HSQ), Benzocycrobutene (BCB), or fluorinated poly aryl ether, which is a low dielectric material to reduce parasitic capacitance between wiring layers.

However, the SOG material has a problem of generating voids between wiring layers.

An object of the present invention is to provide a wiring layer forming method of a semiconductor device for preventing the generation of voids in the insulating film between the wiring layers.

1A to 1F are cross-sectional views illustrating a method of forming a wiring layer of a semiconductor device according to the present invention.

In order to achieve the above object, the present invention comprises the steps of depositing a conductive material and an insulating material on a semiconductor substrate in order to form a first wiring layer and a first insulating film; Patterning the first insulating film / first wiring layer; Depositing a silicon on glass (SOG) material on the semiconductor substrate on which the patterned first insulating film / first wiring layer is formed to form a second insulating film; Etching back the second insulating film until the first insulating film is exposed; Depositing an insulating material on the semiconductor substrate to form a third insulating film; Etching a predetermined region of the third insulating film; And forming a second wiring layer by depositing and patterning a conductive material on the semiconductor substrate.

The second insulating film is preferably formed using any one of a polymer such as Hydrogen Siliquioxane (HSQ), Benzocycrobutene (BCB), Fluorinated poly aryl ether.

It is preferable to form the said 1st insulating film in 1000 micrometers or less.

Accordingly, in the method for forming a wiring layer of a semiconductor device according to the present invention, no void occurs between the first wiring layer and the second wiring layer patterned because SOG material is not present on the first wiring layer, which is a lower wiring layer, and the first wiring layer is not generated. Since the parasitic capacitance formed between the second wiring layer and the second wiring layer is reduced, the RC delay due to the resistance R and the capacitor C is improved.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1A to 1F are cross-sectional views illustrating a method of forming a wiring layer of a semiconductor device according to the present invention.

Reference numeral 1 is a semiconductor substrate, 3 is a pattern, 5 is a first insulating film, 7 · 7a is a first wiring layer, 9 · 9a is a second insulating film, 11 · 11a is a third insulating film, and 13 is 15a and 15b represent a 2nd wiring layer, respectively.

Referring to FIG. 1A, a first insulating film 5, a first wiring layer 7, and a second insulating film 9 are sequentially formed on the semiconductor substrate 1 on which the pattern 3 is formed.

The pattern 3 may be a gate, a storage electrode, a bit line, or the like.

The first wiring layer 7 is formed using a blanket metal.

The second insulating film 9 is formed of an oxide film by using a chemical vapor deposition (CVD) or a plasma vapor deposition (PVD) method, or by using SiON and SiOF, the thickness of which is 1000 Å or less.

Referring to FIG. 1B, a predetermined region of the second insulating layer 9 / first wiring layer 7 is etched using a photolithography method to form a patterned second insulating layer 9a / first wiring layer 7a. .

Referring to FIG. 1C, a low dielectric material SOG (Silicon On Glass) is deposited on the entire surface of the semiconductor substrate 1 on which the second insulating layer 9a / the first wiring layer 7a are formed to form the third insulating layer 11. do.

The third insulating layer 11 is formed by spin on coating Hydrogen Siliquioxane (HSQ), Benzocycrobutene (BCB) or Fluorinated poly aryl ether.

Referring to FIG. 1D, the third insulating layer 11 is etched back to form the third insulating layer 11a until the second insulating layer 9a is exposed.

Referring to FIG. 1E, a fourth insulating layer 13 is formed on the semiconductor substrate 1.

The fourth insulating layer 13 is formed of an oxide film using a chemical vapor deposition (CVD) or a plasma vapor deposition (PVD) method, or formed using SiON or SiOF.

Referring to FIG. 1F, a process of depositing a photoresist film (not shown) on the fourth insulating layer 13, and patterning the photoresist film by using a mask for exposing a predetermined region of the first wiring layer 7a. And etching the fourth insulating film 13 and the third insulating film 9a by using the photosensitive film as a mask to form the contact hole 14, removing the photosensitive film, and on the semiconductor substrate 1. After the deposition of the conductive material, the process of forming the second wiring layers 15a and 15b by patterning is sequentially performed.

The second wiring layer 15a is connected to the first wiring layer 7a through the contact hole 14.

The present invention is not limited to this, and it is apparent that many modifications are possible by those skilled in the art within the technical idea of the present invention.

As described above, in the method for forming a wiring layer of the semiconductor device according to the present invention, no void occurs between the patterned first wiring layer and the second wiring layer because SOG material is not present on the first wiring layer, which is a lower wiring layer. Since the parasitic capacitance formed between the first wiring layer and the second wiring layer is reduced, the RC delay due to the resistance R and the capacitor C is improved.

Claims (3)

Sequentially depositing a conductive material and an insulating material on the semiconductor substrate to form a first wiring layer and a first insulating film; Patterning the first insulating film / first wiring layer; Depositing a silicon on glass (SOG) material on the semiconductor substrate on which the patterned first insulating film / first wiring layer is formed to form a second insulating film; Etching back the second insulating film until the first insulating film is exposed; Depositing an insulating material on the semiconductor substrate to form a third insulating film; Etching a predetermined region of the third insulating film; And forming a second wiring layer by depositing and patterning a conductive material on the semiconductor substrate. The method of claim 1, wherein the second insulating layer is formed using any one of a polymer such as Hydrogen Siliquioxane (HSQ), Benzocycrobutene (BCB), and Fluorinated poly aryl ether. The method of forming a wiring layer of a semiconductor device according to claim 1, wherein the first insulating film is formed to a thickness of 1000 kPa or less.