KR20010059136A - Method for manufacturing flash memory device - Google Patents

Abstract

PURPOSE: A method for manufacturing a flash memory device is provided to prevent a gate attack by improving a topology of a floating gate due to a stepped portion of an upper portion of a field oxide layer. CONSTITUTION: An isolation layer(32) is formed on a semiconductor substrate(31). The first conductive layer is formed thereon. The first conductive layer pattern(33a,33b) is formed by etching selectively the first conductive layer. A dielectric layer and the second conductive layer are formed on the first conductive layer pattern(33a,33b). The second conductive layer is etched to reduce a stepped portion of the first conductive layer pattern(33a,33b). The first photoresist pattern is formed on the cell region. The second conductive layer and the dielectric layer are removed from the peripheral circuit region. The third conductive layer and an anti-reflection layer are formed thereon. The second photoresist pattern is formed on the anti-reflection layer. The anti-reflection layer, the third conductive layer, and the dielectric layer are removed selectively by using the second photoresist pattern as a mask.

Description

Method for manufacturing a flash memory device {METHOD FOR MANUFACTURING FLASH MEMORY DEVICE}

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a flash memory device having a floating gate of a laminated structure.

In the process of forming a floating gate in a 0.25 μm wide 8M-class flash memory under development, a gate line size of 0.25 μm or less is applied according to the integration of devices.

When using the ultra-small size and using the isolation-sealed local oxide of silicon (NS-LOCOS) process, the conductive film pattern of the gate line is formed over the field oxide film (FOX). Subsequent topologies due to the profile deteriorate, resulting in a gate line attack due to the lack of photoresist selectivity for the etching process during gate line formation.

Hereinafter, a method of manufacturing a floating gate of a flash memory device according to the related art will be described with reference to the accompanying drawings.

As shown in FIG. 1A, the gate line is formed by dividing the cell region X and the peripheral circuit region Y. In the cell region X, a floating gate corresponding to the cell is formed later, and the peripheral circuit region Y is formed. ) Is the gate line of the peripheral circuit transistor.

In the method of manufacturing a flash memory device, a device isolation film 12 is formed on a semiconductor substrate 11 subjected to a predetermined lower step by using a local oxide of silicon (LOCOS) process. Subsequently, polysilicon is deposited as a first conductive layer on the resultant, and then selectively patterned to form first conductive layers 13a and 13b in the cell region X and the peripheral circuit region Y, respectively. In this case, the first conductive film 13a formed in the cell region X is formed over the device isolation film 12.

As shown in FIG. 1B, an ONO film 14 is formed on the entire surface including the first conductive films 13a and 13b as a dielectric film, and then the ONO film in the peripheral circuit region Y is selectively removed and the resultant product is removed. Polysilicon is formed on the upper portion as the second conductive film 15. In this case, the second conductive layer 15 uses a cover polysilicon applied only to a flash memory device.

As illustrated in FIG. 1C, after the third conductive film 16, the tungsten silicide 17, and the anti-reflection film 18 are sequentially deposited on the entire surface including the second conductive film 15, the first photoresist film pattern ( Dry etching is performed using 19) to form gate lines of the cell region X and the peripheral circuit region Y.

As shown in FIG. 1D, when the gate line of the peripheral circuit region Y is formed using the first photoresist pattern 19 in the first dry etching process, the ONO film 14 is formed in the cell region X. As an etch stop layer, only the second conductive layer pattern 15a is formed.

As illustrated in FIG. 1E, dry etching is performed using the second photoresist layer pattern 20 to remove the ONO layer of the cell region X. The second photoresist layer pattern 20 is formed only on the transistors of the cell region X. Is formed. After the ONO film 14, which is an etch stop barrier, is removed to form the floating gate existing in the cell region X, the transistors of the cell region X and the peripheral circuit region Y may be formed.

As shown in FIG. 2, when the gate line is formed in the above-described process sequence, the oxynitride film, which is an antireflection film ARC of the floating gate of the cell region, is not sustained during dry etching and is attacked.

3 (a) and 3 (b) show an anti-reflection film attack caused by the first conductive film step when forming the gate pattern, and the reason for this is explained in two ways.

As shown in (a) of FIG. 3, when the first conductive films 13a and 13b are formed, the topology of the first conductive film 13a formed on the device isolation film 12 is deteriorated, and subsequent processes are performed. When coating the photoresist for forming the gate pattern, a difference in the thickness of the photoresist is caused according to the topology caused by the step A of the first conductive layer 13a.

As shown in (b) of FIG. 3, the photoresist loss is intensified due to the lack of selectivity of the photoresist during dry etching of the gate line due to the difference due to the photoresist thickness, and then, during tungsten silicide (WSix) and polysilicon etching, The antireflection film 18 formed on the stepped portion of the first conductive film 13a is etched, so that almost all of the antireflection film 18 on the first conductive film 13a step is removed during the gate etching.

Therefore, due to the process problem generated during the gate etching, the anti-reflection film attack is performed in the self-aligned etching process that removes the ONO film and the first conductive film 13a to form the floating gate of the cell region, which is a subsequent process. To generate a gate attack. This process problem is easy to improve the selectivity to the photosensitive film in the etching step by etching recipe tuning (tuning) rather than the side, but the method is difficult under the current conditions.

This reason can be seen from the step-by-step etch rate for the dry etching process. That is, it can be seen that the selectivity of the photoresist in the anti-reflection film and the gate etching step is almost 1: 1. Accordingly, if the etching target for removing the residual film from the current base is 150% to 200% over-etched, the photoresist film is lost early in the gate etching step, and the anti-reflective film at the top of the first conductive film 13a step is also lost.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide a method of manufacturing a flash memory device suitable for preventing a gate attack by improving the topology of the floating gate due to the step difference caused on the field oxide film. .

1A to 1E illustrate a method of manufacturing a flash memory device according to the prior art;

2 is a view showing a gate attack according to the prior art,

3 is a view showing an anti-reflection film attack due to the first conductive film step of the prior art,

4A-4E illustrate a method of manufacturing a flash memory device according to an embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

31 semiconductor substrate 32 device isolation film

33a, 33b: first conductive film pattern 34: ONO film

35a: second conductive film pattern 36: third conductive film

37: antireflection film 38a, 38b, 39a, 39b: photosensitive film pattern

Ⅰ: Cell area Ⅱ: Peripheral circuit area

In order to achieve the above object, the present invention provides a method of manufacturing a flash memory device, which is divided into a cell region and a peripheral circuit region, the method comprising: forming a device isolation film on a semiconductor substrate; Selectively etching to form a first conductive layer pattern over the device isolation layer, a third step of forming a dielectric layer and a second conductive layer over the first conductive layer pattern, and a first conductive layer over the device isolation layer A fourth step of etching the entire second conductive layer in order to reduce the step difference of the pattern, by forming a first photoresist layer pattern on the cell region and using the first photoresist layer pattern as a mask; In a fifth step of removing the dielectric film, a third conductive film and an antireflection film are formed on the resultant, and a second photoresist pattern is formed on the antireflection film. And a sixth step, the second photosensitive film pattern, characterized by yirueojim including a seventh step as a mask to selectively remove the anti-reflection film, a third conductive film and a dielectric film.

Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

4A to 4E are views illustrating a method of manufacturing a flash memory device according to an embodiment of the present invention.

As shown in FIG. 4A, a cell isolation layer 32 is formed on a semiconductor substrate 31 using a shallow trench isolation (STI) process to define a cell region I and a peripheral circuit region II. A predetermined lower step is performed on the semiconductor substrate 31 on which the 32 is formed. In this case, the device isolation film 32 is formed in the transistor of the cell region (I), but the device isolation film 32 is not formed in the transistor of the peripheral circuit region (II). Since the STI process is used, the conductive film for forming the floating gate is formed. The topology can be lowered during deposition.

Subsequently, a first conductive film, for example, polysilicon (polysilicon) is deposited on the semiconductor substrate 31 to a thickness of 1700 Å, and then a photoresist is applied on the first conductive film and patterned by an exposure and development process. . Subsequently, when dry etching is performed using the patterned photoresist as a mask, first conductive film patterns 33a and 33b are formed in the transistor of the cell region I and the transistor of the peripheral circuit region II. The polysilicon for the first conductive film may be deposited using argon sputtering.

Then, an ONO film (Oxide Nitride Oxide) 34 is deposited on the first conductive film patterns 33a and 33b as a dielectric film, and then polysilicon is deposited as the second conductive film 35 on the ONO film 34. It is deposited at a thickness of 4000 to 5000 mm 3.

At this time, in the prior art, the polysilicon for the second conductive film 35 is formed to be 150 to 500 Å thin, and the polysilicon for the second conductive film 35 is referred to as cover polysilicon. Here, the polysilicon for the second conductive layer 35 requires a dielectric layer to operate as a floating gate in the cell region I, and does not require a dielectric layer to operate as a transistor in the peripheral circuit region II. . Also, due to the step D of the first conductive film pattern 33a, the step E may be generated in the second conductive film 35 as in the prior art.

In addition, even when the thick second conductive layer 35 is used as an etching mask, the ONO layer 34 is not lost even though the second conductive layer 35 is removed through wet etching. Thus, the electrical characteristics of the floating gate of the cell region can be secured.

As shown in FIG. 4B, in order to improve the topology of the first conductive layer pattern 33a on the device isolation layer 32, the second conductive layer 35 is etched back to induce a step ( F) decrease. At this time, the thickness of the polysilicon remaining when the second conductive layer 35 is etched back is controlled to 500 kPa. In this case, amorphous silicon may be used as the second conductive layer 35, and after etching back the second conductive layer 35, cleaning using BOE (Buffered Oxide Etchant) and a scrubber to reduce the loss due to plasma. Carry out the process.

As shown in FIG. 4C, a photoresist film is applied on the etched back second conductive film 35a and patterned by an exposure and development process, and then the patterned photoresist film is used as a mask. 2 Dry-etch the conductive film 35 and the ONO film 34. Here, the etchant used when dry etching the second conductive layer 35 is a device using a high density plasma source (Transfer Coupled Plasma) and a Magnetic Enhanced Reactive Ion Etch (MERIE) etchant. Use The reason why the second conductive layer 35 including the ONO layer 34 is removed is to allow the peripheral circuit region II to operate as a transistor instead of a floating gate.

As shown in FIG. 4D, a third conductive layer 36 including polysilicon 700 μs and tungsten silicide layer 2000 μs is formed on the resultant, and then reflected on the third conductive layer 36. Oxynitride (1200 Å) is deposited as the barrier film 37.

Subsequently, a photoresist film is coated on the antireflection film 37 and patterned by an exposure and development process to form photoresist patterns 38a, 38b, 39a, and 39b for defining a floating gate. At this time, the photoresist pattern is formed on both the cell region (I) and the peripheral circuit region (II), and the photoresist pattern (38a, 38b) formed on the cell region is used as a floating gate pattern, and the upper portion of the peripheral circuit region (II) The photoresist patterns 39a and 39b formed in the transistors are used as transistor gate patterns.

As shown in FIG. 4E, when the floating gate etching is performed on the cell region I and the peripheral circuit region II using the photoresist patterns 38a, 38b, 39a, and 39b as a mask, the peripheral circuit region is formed. In (II), since there is no ONO film 34, the antireflection film 37 and the third conductive film 36 are dry etched, and in the cell region I, dry etching is stopped in the ONO film 34. Here, a mixed gas of Cl ₂ and O ₂ is used to improve the attack of tungsten silicide and polysilicon, which are the third conductive layer 36 material, during the floating gate etching.

Subsequently, a photoresist pattern (not shown) is formed on the transistor of the peripheral circuit region II, and then the ONO layer 34 of the etched cell region is removed using the photoresist pattern as a mask to form a floating gate. . By removing the ONO film 34 in this manner, a good etching profile G without attack of the anti-reflection film 37a and the third conductive film pattern 36a formed on the floating gate can be obtained.

As described above, in the present invention, the step difference caused by the first conductive layer pattern 33a on the device isolation layer is reduced to the etch back of the second conductive layer 35, thereby lowering the topology of the floating gate to relatively increase the photoresist selectivity. You can.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

The above-described present invention can improve the gate top notch due to the lack of photoresist selectivity by using a topology improvement through the conductive film etch back under the floating gate of the flash memory device, and can easily increase the process margin through the step difference. It can be effective.

In addition, the lack of the photoresist selectivity during gate etching can be overcome by improving the topology, thereby improving the yield of the device by eliminating process instability and securing process margins.

Claims (11)

In the flash memory device manufacturing method divided into a cell region and a peripheral circuit region, Forming a device isolation film on the semiconductor substrate; Forming a first conductive film on the resultant material and selectively etching the first conductive film to form a first conductive film pattern on the device isolation film; A third step of forming a dielectric film and a second conductive film on the first conductive film pattern; A fourth step of etching the entire surface of the second conductive layer to reduce the step difference between the first conductive layer pattern on the device isolation layer; Forming a first photoresist layer pattern on the cell region and removing the second conductive layer and the dielectric layer of the peripheral circuit region using the first photoresist layer pattern as a mask; A sixth step of forming a third conductive film and an anti-reflection film on the resultant and a second photoresist pattern on the anti-reflection film; And A seventh step of selectively removing the anti-reflection film, the third conductive film and the dielectric film using the second photoresist pattern as a mask Method of manufacturing a flash memory device, characterized in that consisting of. The method of claim 1, In the first step, The device isolation film is a method of manufacturing a flash memory device, characterized in that formed using the STI process. The method of claim 1, In the second step, The first conductive film is a method of manufacturing a flash memory device, characterized in that using polysilicon. The method of claim 1, In the third step, And the second conductive film is made of polysilicon having a thickness of 4000 to 5000 microns. The method of claim 1, The fourth step, And etching the entire surface of the second conductive layer using argon sputtering. The method of claim 1, In the fourth step, And the front etched second conductive film is formed to a thickness of 500 to 700 kHz. The method of claim 1, The seventh step, The dielectric film of the cell region is used as an etch stop layer. The method of claim 1, A method of manufacturing a flash memory device, characterized in that amorphous silicon is used as the second conductive film. The method of claim 1, The fourth step, And cleaning by using a BOE and a scrubber to reduce losses due to plasma after the second conductive layer front surface etching. The method of claim 1, In the fifth step, The second conductive film is removed using a TCP or MERIE etching device using a high density plasma source. The method of claim 1, The seventh step, Cl ₂ and O ₂ gas is used to prevent the attack of the third conductive film.