KR20040008760A - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor device Download PDFInfo
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- KR20040008760A KR20040008760A KR1020020042449A KR20020042449A KR20040008760A KR 20040008760 A KR20040008760 A KR 20040008760A KR 1020020042449 A KR1020020042449 A KR 1020020042449A KR 20020042449 A KR20020042449 A KR 20020042449A KR 20040008760 A KR20040008760 A KR 20040008760A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
- H01L21/0276—Photolithographic processes using an anti-reflective coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체소자의 제조방법에 관한 것으로, 보다 상세하게 자기정렬콘택(self aligned contact, SAC) 방법을 사용한 식각공정 시 마스크절연막의 손실을 억제하는 반도체소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device for suppressing loss of a mask insulating film during an etching process using a self aligned contact (SAC) method.
반도체소자가 고집적화 되어가면서 대부분의 콘택홀은 SAC방법을 이용하여 형성되고 있다.As semiconductor devices are becoming highly integrated, most contact holes are formed using the SAC method.
특히, 최근의 기술 동향에서 SAC방법으로 콘택홀을 형성하는 경우 식각장벽으로 사용하는 물질을 도전배선의 하드마스크로 사용하고 있으며, 이때 잔존하는 하드마스크의 두께는 SAC 페일(fail) 발생에 큰 변수로 작용한다.In particular, in the recent technology trend, when the contact hole is formed by the SAC method, a material used as an etch barrier is used as a hard mask for the conductive wiring, and the thickness of the remaining hard mask is a large variable in the generation of SAC fail. Acts as.
이때, 식각장벽으로 사용되는 하드마스크의 두께는 소자의 고집적화로 인하여 어느 수준 이상은 사용할 수 없다.In this case, the thickness of the hard mask used as an etch barrier cannot be used above a certain level due to the high integration of the device.
상기 SAC 페일의 개선을 위하여 도전배선 형성 시 도전배선의 상부에 존재하는 하드마스크의 두께를 계속 증가시키고 있다.In order to improve the SAC fail, the thickness of the hard mask existing on the upper portion of the conductive line is continuously increased when the conductive line is formed.
그러나 상기 하드마스크의 두께를 증가시키는 경우 도전배선의 형성 과정 자체가 어려워진다는 문제점이 있다.However, when increasing the thickness of the hard mask, there is a problem that the formation process of the conductive wiring itself becomes difficult.
반도체소자의 고집적화로 도전배선의 선폭이 감소하는 시점에서 감광막의 두께는 감소하는데 피식각층이 도전배선의 두께가 증가하기 때문이다.When the line width of the conductive wiring decreases due to the high integration of the semiconductor device, the thickness of the photosensitive film decreases because the thickness of the conductive wiring increases in the etching target layer.
그러므로 잔존하는 하드마스크의 절대량을 증가시키기 위하여 많은 연구가 행해지고 있으며, 이러한 연구는 식각선택비 향상을 꾀하는 것으로 진행이 되고 있다.Therefore, many studies have been conducted to increase the absolute amount of the remaining hard mask, and these studies are proceeding to improve the etching selectivity.
이하, 첨부된 도면을 참고로 하여 종래기술에 대하여 설명한다.Hereinafter, with reference to the accompanying drawings will be described in the prior art.
도 1a 내지 도 1c 는 종래기술에 따른 반도체소자의 제조방법에 의한 공정 단면도로서, 비트라인 형성방법을 도시한다.1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the related art, and illustrate a method of forming a bit line.
먼저, 소정의 하부구조물이 구비되는 반도체기판(11) 상부에 비트라인 콘택플러그(13)가 구비되는 층간절연막(12)을 형성한다.First, an interlayer insulating layer 12 having a bit line contact plug 13 is formed on a semiconductor substrate 11 having a predetermined lower structure.
다음, 전체표면 상부에 비트라인용 제1도전층(14)을 형성한다. 이때, 상기 제1도전층(14)은 다결정실리콘층 또는 확산방지막으로 사용되는 Ti/TiN막으로 형성된 것이다.Next, a first conductive layer 14 for bit lines is formed on the entire surface. In this case, the first conductive layer 14 is formed of a polysilicon layer or a Ti / TiN film used as a diffusion barrier.
그 다음, 상기 제1도전층(14) 상부에 제2도전층(16)을 형성한다. 이때, 상기 제2도전층(16)은 W막 또는 WSix막으로 형성된 것이다.Next, a second conductive layer 16 is formed on the first conductive layer 14. In this case, the second conductive layer 16 is formed of a W film or a WSi x film.
다음, 상기 제2도전층(16) 상부에 마스크절연막(18)을 형성한다. 이때, 상기 마스크절연막(18)은 질화막 또는 산화막으로 형성된 것이다.Next, a mask insulating layer 18 is formed on the second conductive layer 16. In this case, the mask insulating film 18 is formed of a nitride film or an oxide film.
그 다음, 상기 마스크절연막(18) 상부에 반사방지막(도시안됨)을 형성한 후, 상기 반사방지막 상부에 비트라인으로 예정되는 부분을 보호하는 감광막패턴(20)을형성한다. 이때, 상기 반사방지막은 SiON막으로 형성된다. (도 1a 참조)Next, an antireflection film (not shown) is formed on the mask insulating film 18, and then a photoresist pattern 20 is formed on the antireflection film to protect a portion intended as a bit line. At this time, the anti-reflection film is formed of a SiON film. (See Figure 1A)
다음, 상기 감광막패턴(20)을 식각마스크로 상기 반사방지막 및 마스크절연막(18)을 식각하여 마스절연막패턴(19) 및 반사방지막패턴(도시안됨)을 형성한다.Next, the anti-reflection film and the mask insulating film 18 are etched using the photoresist pattern 20 as an etch mask to form a mask insulating film pattern 19 and an anti-reflection film pattern (not shown).
그 다음, 상기 감광막패턴(20)을 제거한다. (도 1b 참조)Next, the photoresist pattern 20 is removed. (See FIG. 1B)
다음, 상기 마스크절연막패턴(19)을 식각마스크로 상기 제2도전층(16)과 제1도전층(14)을 식각하여 제2도전층패턴(17)과 제1도전층패턴(15) 적층구조의 비트라인을 형성한다. (도 1c 참조)Next, the second conductive layer 16 and the first conductive layer 14 are etched using the mask insulating layer pattern 19 as an etch mask to stack the second conductive layer pattern 17 and the first conductive layer pattern 15. Form the bit line of the structure. (See Figure 1C)
상기한 바와 같이 종래기술에 따른 반도체소자의 제조방법은, 마스크절연막을 식각마스크로 이용하여 식각공정을 진행하는 경우 상기 반사방지막 및 마스크절연막이 손실되어 후속 자기정렬콘택 식각에 대한 공정 마진이 부족하여 소자 간에 절연 특성이 저하되는 문제점이 있다.As described above, in the method of manufacturing a semiconductor device according to the related art, when an etching process is performed using a mask insulating film as an etch mask, the anti-reflection film and the mask insulating film are lost, and thus a process margin for subsequent self-aligned contact etching is insufficient. There is a problem that the insulation properties between the devices is degraded.
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 소자분리절연막 또는 도전배선을 형성하는 경우 소자분리마스크로 사용되는 질화막 상부 또는 도전배선 상부에 형성되는 마스크절연막 상에 다결정실리콘 또는 도전배선과 같은 종류의 물질로 캐핑막을 형성한 후 사진식각공정을 실시함으로써 캐핑막의 증착 두께를 감소시킬 수 있고, 식각공정 시 상기 마스크절연막의 손실을 방지하여 후속 공정으로 형성되는 소자와의 절연 특성을 향상시켜 소자의 수율 및 신뢰성을 향상시키는 반도체소자의 제조방법을 제공하는데 그 목적이 있다.In order to solve the above-mentioned problems of the prior art, when forming a device isolation insulating film or a conductive wiring, a polysilicon or a conductive wiring such as a polysilicon or a conductive wiring is formed on a nitride insulating film formed on an upper surface of a nitride film or an upper conductive wiring. After the capping film is formed of a kind of material, the deposition thickness of the capping film may be reduced by performing a photolithography process, and the insulating layer is improved by improving the insulating property with the device formed in a subsequent process by preventing the loss of the mask insulating film during the etching process. It is an object of the present invention to provide a method for manufacturing a semiconductor device that improves the yield and reliability.
도 1a 내지 도 1c 는 종래기술에 따른 반도체소자의 제조방법에 의한 공정 단면도.1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.
도 2a 내지 도 2d 는 본 발명의 제1실시예에 따른 반도체소자의 제조방법에 의한 공정 단면도.2A through 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention.
도 3a 내지 도 3e 는 본 발명의 제2실시예에 따른 반도체소자의 제조방법에 의한 공정 단면도.3A to 3E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.
도 4a 내지 도 4c 는 본 발명의 제3실시예에 따른 반도체소자의 제조방법에 의한 공정 단면도.4A to 4C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a third embodiment of the present invention.
< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>
11, 21, 31, 51 : 반도체기판 12, 52 : 층간절연막11, 21, 31, 51: semiconductor substrate 12, 52: interlayer insulating film
13, 53 : 비트라인 콘택플러그 14, 33, 54 : 제1도전층13, 53: bit line contact plug 14, 33, 54: first conductive layer
15, 34, 55 : 제1도전층패턴 16, 35, 56 : 제2도전층15, 34, 55: first conductive layer pattern 16, 35, 56: second conductive layer
17, 36, 57 : 제2도전층패턴 18, 37, 58 : 마스크절연막17, 36, 57: second conductive layer pattern 18, 37, 58: mask insulating film
19, 38, 59 : 마스크절연막패턴 20, 29, 43, 62 : 감광막패턴19, 38, 59: mask insulating film pattern 20, 29, 43, 62: photoresist film pattern
22 : 패드산화막 23 : 패드산화막패턴22: pad oxide film 23: pad oxide film pattern
24 : 질화막 25 : 질화막패턴24: nitride film 25: nitride film pattern
26, 40, 60 : 캐핑막 27, 40 : 캐핑막패턴26, 40, 60: capping film 27, 40: capping film pattern
28, 41 : 유기반사방지막 30 : 트렌치28, 41: organic antireflection film 30: trench
32 : 게이트절연막32: gate insulating film
이상의 목적을 달성하기 위한 본 발명에 따른 반도체소자의 제조방법은,Method for manufacturing a semiconductor device according to the present invention for achieving the above object,
반도체기판 상부에 패드산화막, 질화막, 캐핑막 및 유기반사방지막을 형성하는 공정과,Forming a pad oxide film, a nitride film, a capping film, and an organic antireflection film on the semiconductor substrate;
상기 유기반사방지막 상부에 소자분리영역으로 예정되는 부분을 노출시키는 감광막패턴을 형성하는 공정과,Forming a photoresist pattern on the organic anti-reflective coating to expose a portion intended to be an isolation region;
상기 감광막패턴을 식각마스크로 상기 유기반사방지막, 캐핑막, 질화막 및 패드산화막을 식각하여 유기반사방지막패턴, 캐핑막패턴, 질화막패턴 및 패드산화막패턴을 형성하는 공정과,Etching the organic antireflection film, capping film, nitride film, and pad oxide film using the photoresist pattern as an etch mask to form an organic antireflection film pattern, a capping film pattern, a nitride film pattern, and a pad oxide film pattern;
상기 감광막패턴과 유기반사방지막패턴을 제거하는 공정과,Removing the photoresist pattern and the organic antireflection coating pattern;
상기 캐핑막패턴을 식각마스크로 상기 반도체기판을 식각하여 트렌치를 형성하되, 상기 식각공정을 진행하는 동안 상기 캐핑막패턴이 제거되도록 하는 공정과,Forming a trench by etching the semiconductor substrate using the capping layer pattern as an etch mask, wherein the capping layer pattern is removed during the etching process;
상기 캐핑막은 다결정실리콘층을 사용하여 2000 ∼ 3500Å 두께로 형성되는 것과,The capping film is formed to a thickness of 2000 ~ 3500Å using a polysilicon layer,
상기 트렌치는 상기 반도체기판을 염소가스와 HBr 가스를 혼합한 가스를 식각가스로 사용하여 형성되는 것과,The trench is formed by using the semiconductor substrate as a etching gas using a gas of chlorine gas and HBr gas,
상기 유기반사방지막, 캐핑막, 질화막, 패드산화막 및 반도체기판을 식각하는 공정은 30 ∼ 60℃의 온도에서 실시되는 것을 제1특징으로 한다.The organic anti-reflection film, the capping film, the nitride film, the pad oxide film, and the step of etching the semiconductor substrate are characterized by being carried out at a temperature of 30 to 60 캜.
또한, 이상의 목적을 달성하기 위한 본 발명에 따른 반도체소자의 제조방법은,In addition, the method of manufacturing a semiconductor device according to the present invention for achieving the above object,
반도체기판 상부에 게이트절연막, 게이트전극용 도전층, 마스크절연막, 캐핑막 및 유기반사방지막을 형성하는 공정과,Forming a gate insulating film, a gate electrode conductive layer, a mask insulating film, a capping film, and an organic antireflection film over the semiconductor substrate;
상기 유기반사방지막 상부에 게이트전극으로 예정되는 부분을 보호하는 감광막패턴을 형성하는 공정과,Forming a photoresist pattern on the organic anti-reflective coating to protect a portion of the organic anti-reflective coating;
상기 감광막패턴을 식각마스크로 상기 유기반사방지막, 캐핑막 및 마스크절연막을 식각하여 유기반사방지막패턴, 캐핑막패턴 및 마스크절연막패턴을 형성하는 공정과,Etching the organic antireflection film, the capping film, and the mask insulating film using the photoresist pattern as an etch mask to form an organic antireflection film pattern, a capping film pattern, and a mask insulating film pattern;
상기 감광막패턴 및 유기반사방지막패턴을 제거하는 공정과,Removing the photoresist pattern and the organic antireflection coating pattern;
상기 캐핑막패턴을 식각마스크로 상기 게이트전극용 도전층을 식각하여 게이트전극을 형성하되, 상기 식각공정을 진행하는 동안 상기 캐핑막패턴이 제거되도록 하는 공정과,Forming a gate electrode by etching the conductive layer for the gate electrode using the capping layer pattern as an etch mask, wherein the capping layer pattern is removed during the etching process;
상기 게이트전극용 도전층은 40 ∼ 70℃의 온도에서 식각되는 것과,The gate electrode conductive layer is etched at a temperature of 40 ~ 70 ℃,
상기 마스크절연막은 질화막, 산화막 또는 SiON막을 사용하여 1500 ∼ 2000Å 두께로 형성되는 것과,The mask insulating film is formed to a thickness of 1500 ~ 2000 막 by using a nitride film, oxide film or SiON film,
상기 캐핑막은 다결정실리콘층을 사용하여 100 ∼ 800Å 두께로 형성되는 것을 제2특징으로 한다.The capping film has a second feature that the polysilicon layer is formed to a thickness of 100 to 800 kPa.
이상의 목적을 달성하기 위한 본 발명에 따른 반도체소자의 제조방법은,Method for manufacturing a semiconductor device according to the present invention for achieving the above object,
반도체기판 상부에 비트라인 콘택플러그를 구비하는 층간절연막을 형성하는 공정과,Forming an interlayer insulating film having a bit line contact plug on the semiconductor substrate;
전체표면 상부에 비트라인용 도전층, 마스크절연막, 캐핑막 및 유기반사방지막을 형성하는 공정과,Forming a bit line conductive layer, a mask insulating film, a capping film, and an organic antireflection film over the entire surface;
상기 유기반사방지막 상부에 비트라인으로 예정되는 부분을 보호하는 감광막패턴을 형성하는 공정과,Forming a photoresist pattern on the organic anti-reflective coating to protect a portion intended as a bit line;
상기 감광막패턴을 식각마스크로 상기 유기반사방지막, 캐핑막 및 마스크절연막을 식각하여 유기반사방지막패턴, 캐핑막패턴 및 마스크절연막패턴을 형성하는 공정과,Etching the organic antireflection film, the capping film, and the mask insulating film using the photoresist pattern as an etch mask to form an organic antireflection film pattern, a capping film pattern, and a mask insulating film pattern;
상기 감광막패턴 및 유기반사방지막패턴을 제거하는 공정과,Removing the photoresist pattern and the organic antireflection coating pattern;
상기 캐핑막패턴을 식각마스크로 상기 비트라인용 도전층을 식각하여 비트라인을 형성하되, 상기 식각공정을 진행하는 동안 상기 캐핑막패턴이 제거되도록 하는 공정과,Forming a bit line by etching the conductive layer for the bit line using the capping layer pattern as an etch mask, and removing the capping layer pattern during the etching process;
상기 비트라인용 도전층은 30 ∼ 70℃의 온도에서 식각되는 것과,The bit line conductive layer is etched at a temperature of 30 ~ 70 ℃,
상기 마스크절연막은 질화막, 산화막 또는 SiON막을 사용하여 1500 ∼ 2000Å 두께로 형성되는 것과,The mask insulating film is formed to a thickness of 1500 ~ 2000 막 by using a nitride film, oxide film or SiON film,
상기 캐핑막은 다결정실리콘층을 사용하여 100 ∼ 800Å 두께로 형성되는 것과,The capping film is formed to a thickness of 100 ~ 800Å using a polysilicon layer,
상기 캐핑막은 금속층을 사용하여 200 ∼ 800Å 두께로 형성되는 것을 제3특징으로 한다.As a third feature, the capping film is formed to a thickness of 200 to 800 kW using a metal layer.
이하, 첨부된 도면을 참조하여 본 발명에 대하여 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail with respect to the present invention.
도 2a 내지 도 2d 는 본 발명의 제1실시예에 따른 반도체소자의 제조방법에 의한 공정 단면도로서, 트렌치를 이용한 소자분리절연막 형성방법을 도시한다.2A to 2D are cross-sectional views illustrating a method of fabricating a semiconductor device in accordance with a first embodiment of the present invention, and illustrate a method of forming an isolation film using trenches.
먼저, 반도체기판(21) 상부에 패드산화막(22), 질화막(24), 캐핑막(26) 및유기반사방지막(28)을 형성한다. 이때, 상기 질화막(24)은 500 ∼ 1600Å 두께로 형성되고, 상기 캐핑막(26)은 다결정실리콘층을 사용하여 2000 ∼ 3500Å 두께로 형성된다.First, a pad oxide layer 22, a nitride layer 24, a capping layer 26, and an oil-based anti-death layer 28 are formed on the semiconductor substrate 21. In this case, the nitride film 24 is formed to a thickness of 500 ~ 1600Å, the capping film 26 is formed to a thickness of 2000 ~ 3500Å using a polysilicon layer.
여기서, 상기 캐핑막(26)은 후속공정으로 형성되는 트렌치의 깊이를 고려하여 형성된 것이다.Here, the capping layer 26 is formed in consideration of the depth of the trench formed in a subsequent process.
다음, 상기 유기반사방지막(28) 상부에 소자분리영역으로 예정되는 부분을 노출시키는 감광막패턴(29)을 형성한다. (도 2a 및 도 2b 참조)Next, a photoresist pattern 29 is formed on the organic anti-reflection film 28 to expose a portion of the device isolation region. (See Figures 2A and 2B)
그 다음, 상기 감광막패턴(29)을 식각마스크로 상기 유기반사방지막(28), 캐핑막(26), 질화막(24) 및 패드산화막(22)을 식각하여 유기반사방지막패턴(도시안됨), 캐핑막패턴(27), 질화막패턴(25) 및 패드산화막패턴(23)을 형성한다. 이때, 상기 식각공정은 30 ∼ 60℃의 온도에서 실시된다.Subsequently, the organic anti-reflection film 28, the capping film 26, the nitride film 24, and the pad oxide film 22 are etched using the photoresist pattern 29 as an etch mask, and the organic anti-reflection film pattern (not shown) and the cathode are used. The ping pattern 27, the nitride layer pattern 25, and the pad oxide layer pattern 23 are formed. At this time, the etching process is carried out at a temperature of 30 ~ 60 ℃.
다음, 상기 감광막패턴(29)과 유기반사방지막패턴을 제거한 후 세정공정을 실시한다. (도 2c 참조)Next, the photoresist pattern 29 and the organic anti-reflective coating pattern are removed and then a cleaning process is performed. (See Figure 2c)
그 다음, 상기 캐핑막패턴(27)을 식각마스크로 상기 반도체기판(21)을 식각하여 트렌치(30)를 형성한다. 이때, 상기 식각공정은 30 ∼ 60℃의 온도에서 염소가스와 HBr 가스를 혼합한 가스를 식각가스로 사용하여 실시된다.Next, the trench 30 is formed by etching the semiconductor substrate 21 by using the capping layer pattern 27 as an etching mask. At this time, the etching process is carried out by using a gas of chlorine gas and HBr gas at the temperature of 30 ~ 60 ℃ as an etching gas.
상기 트렌치(30)를 형성하는 식각공정 동안 상기 캐핑막패턴(27)은 제거된다. (도 2d 참조)The capping layer pattern 27 is removed during the etching process of forming the trench 30. (See FIG. 2D)
도 3a 내지 도 3e 는 본 발명의 제2실시예에 따른 반도체소자의 제조방법에 의한 공정 단면도로서, 게이트전극 형성방법을 도시한다.3A to 3E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention, and illustrate a method of forming a gate electrode.
반도체기판(31) 상부에 게이트절연막(32)을 형성한다.A gate insulating film 32 is formed on the semiconductor substrate 31.
다음, 상기 게이트절연막(32) 상부에 게이트전극을 형성하기 위한 제1도전층(33), 제2도전층(35), 마스크절연막(37), 캐핑막(39) 및 유기반사방지막(41)을 형성한다. 이때, 상기 제1도전층(33)은 다결정실리콘층으로 형성되고, 상기 제2도전층(35)은 W층으로 형성되거나, 상기 제1도전층(33)과 제2도전층(35)이 폴리사이드구조로 형성될 수도 있다.Next, a first conductive layer 33, a second conductive layer 35, a mask insulating layer 37, a capping layer 39, and an organic antireflection layer 41 for forming a gate electrode on the gate insulating layer 32. To form. In this case, the first conductive layer 33 is formed of a polysilicon layer, the second conductive layer 35 is formed of a W layer, or the first conductive layer 33 and the second conductive layer 35 are It may be formed of a polyside structure.
그리고, 상기 마스크절연막(37)은 질화막, 산화막 또는 SiON막을 사용하여 1500 ∼ 2000Å 두께로 형성되고, 상기 캐핑막(39)은 다결정실리콘층을 사용하여 100 ∼ 800Å 두께로 형성된다.The mask insulating film 37 is formed to a thickness of 1500 to 2000 kV using a nitride film, an oxide film, or a SiON film, and the capping film 39 is formed to a thickness of 100 to 800 kW using a polysilicon layer.
다음, 상기 유기반사방지막(41) 상부에 게이트전극으로 예정되는 부분을 보호하는 감광막패턴(43)을 형성한다. (도 3a 및 도 3b 참조)Next, a photoresist pattern 43 is formed on the organic anti-reflective coating 41 to protect a portion of the organic anti-reflective coating 41. (See Figures 3A and 3B)
그 다음, 상기 감광막패턴(43)을 식각마스크로 상기 유기반사방지막(41), 캐핑막(39) 및 마스크절연막(37)을 식각하여 유기반사방지막패턴(도시안됨), 캐핑막패턴(40) 및 마스크절연막패턴(38)을 이때, 상기 식각공정은 40 ∼ 70℃의 온도에서 실시된다.Next, the organic anti-reflective film 41, the capping film 39, and the mask insulating film 37 are etched using the photoresist pattern 43 as an etch mask, and the organic anti-reflective film pattern (not shown) and the capping film pattern 40 are etched. And the mask insulating film pattern 38 at this time, the etching process is performed at a temperature of 40 ~ 70 ℃.
다음, 상기 감광막패턴(43)과 유기반사방지막패턴을 제거한 후 세정공정을 실시한다. (도 3c 참조)Next, the photoresist pattern 43 and the organic anti-reflective coating pattern are removed and then a cleaning process is performed. (See Figure 3c)
그 다음, 상기 캐핑막패턴(40)을 식각마스크로 상기 제2도전층(35)을 식각하여 제2도전층패턴(36)을 형성한다. 이때, 상기 제2도전층(35)이 W층인 경우 40 ∼70℃의 온도에서 NF3, CF4또는 SF6등의 불소가스를 식각가스로 이용하여 식각된다. (도 3d 참조)Next, the second conductive layer 35 is etched using the capping layer pattern 40 as an etch mask to form a second conductive layer pattern 36. In this case, when the second conductive layer 35 is a W layer, the second conductive layer 35 is etched using fluorine gas such as NF 3 , CF 4, or SF 6 as an etching gas at a temperature of 40 to 70 ° C. (See FIG. 3D)
이어서, 상기 캐핑막패턴(40)을 식각마스크로 상기 제1도전층(33)을 식각하여 제1도전층패턴(34)을 형성한다. 상기 제1도전층(33)이 다결정실리콘층인 경우 40 ∼ 70℃의 온도에서 염소가스를 식각가스로 이용하여 식각된다.Subsequently, the first conductive layer 33 is etched using the capping layer pattern 40 as an etch mask to form the first conductive layer pattern 34. When the first conductive layer 33 is a polysilicon layer, it is etched using chlorine gas as an etching gas at a temperature of 40 to 70 ℃.
여기서, 상기 제2도전층(35)과 제1도전층(33)을 식각하는 동안 상기 캐핑막패턴(40)이 제거된다. (도 3e 참조)Here, the capping layer pattern 40 is removed while the second conductive layer 35 and the first conductive layer 33 are etched. (See Figure 3E)
도 4a 내지 도 4c 는 본 발명의 제3실시예에 따른 반도체소자의 제조방법에 의한 공정 단면도로서, 비트라인 형성방법을 도시한다.4A through 4C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a third embodiment of the present invention, and illustrate a method of forming a bit line.
소정의 하부구조물이 구비되는 반도체기판(51) 상부에 비트라인 콘택플러그(53)가 구비되는 층간절연막(52)을 형성한다.An interlayer insulating layer 52 having a bit line contact plug 53 is formed on the semiconductor substrate 51 having a predetermined lower structure.
다음, 전체표면 상부에 비트라인을 형성하기 위한 제1도전층(54), 제2도전층(56), 마스크절연막(58), 캐핑막(60) 및 유기반사방지막(도시안됨)을 형성한다. 이때, 상기 제1도전층(54)은 Ti, TiN 또는 Ti/TiN 등의 확산방지막이나 다결정실리콘층으로 형성되고, 상기 제2도전층(56)은 W층으로 형성되거나, 상기 제1도전층(54)과 제2도전층(56)이 폴리사이드구조로 형성될 수도 있다.Next, a first conductive layer 54, a second conductive layer 56, a mask insulating film 58, a capping film 60, and an organic antireflection film (not shown) are formed on the entire surface to form a bit line. . In this case, the first conductive layer 54 is formed of a diffusion barrier or polycrystalline silicon layer such as Ti, TiN or Ti / TiN, and the second conductive layer 56 is formed of a W layer or the first conductive layer. 54 and the second conductive layer 56 may be formed of a polyside structure.
그리고, 상기 마스크절연막(58)은 질화막, 산화막 또는 SiON막을 사용하여 1500 ∼ 2000Å 두께로 되고, 상기 캐핑막(60)은 다결정실리콘층을 사용하여 100 ∼ 800Å 두께로 형성되거나, 금속층을 사용하여 200 ∼ 800Å 두께로 형성된다.The mask insulating film 58 is 1500-2000 kW thick using a nitride film, an oxide film or a SiON film, and the capping film 60 is 100-800 kW thick using a polysilicon layer, or 200 using a metal layer. It is formed to a thickness of -800 kPa.
다음, 상기 유기반사방지막 상부에 비트라인으로 예정되는 부분을 보호하는 감광막패턴(62)을 형성한다. (도 4a 참조)Next, a photoresist pattern 62 is formed on the organic anti-reflective coating to protect a portion intended as a bit line. (See Figure 4A)
그 다음, 상기 감광막패턴(62)을 식각마스크로 상기 유기반사방지막, 캐핑막(60) 및 마스크절연막(58)을 식각하여 유기반사방지막패턴(도시안됨), 캐핑막패턴(61) 및 마스크절연막패턴(59)을 형성한다.Next, the organic antireflection film, the capping film 60 and the mask insulating film 58 are etched using the photoresist pattern 62 as an etch mask to etch the organic antireflection film pattern (not shown), the capping film pattern 61 and the mask insulating film. The pattern 59 is formed.
다음, 상기 감광막패턴(62)과 유기반사방지막패턴을 제거한 후 세정공정을 실시한다. (도 4b 참조)Next, the photoresist film pattern 62 and the organic anti-reflective film pattern are removed and then a cleaning process is performed. (See Figure 4b)
그 다음, 상기 캐핑막패턴(61)을 식각마스크로 상기 제2도전층(56) 및 제1도전층(54)을 식각하여 제2도전층패턴(57)과 제1도전층패턴(55)을 형성한다. 이때, 상기 제2도전층(35)이 W층인 경우 30 ∼ 70℃의 온도에서 NF3, CF4또는 SF6등의 불소가스를 식각가스로 이용하여 식각된다. 그리고, 상기 제1도전층(33)이 다결정실리콘층이나 확산방지막인 경우 염소가스를 식각가스로 이용하여 식각된다.Next, the second conductive layer 56 and the first conductive layer 54 are etched using the capping layer pattern 61 as an etch mask to etch the second conductive layer pattern 57 and the first conductive layer pattern 55. To form. In this case, when the second conductive layer 35 is a W layer, the second conductive layer 35 is etched using an fluorine gas such as NF 3 , CF 4, or SF 6 as an etching gas at a temperature of 30 to 70 ° C. When the first conductive layer 33 is a polysilicon layer or a diffusion barrier layer, the first conductive layer 33 is etched using chlorine gas as an etching gas.
여기서, 상기 제2도전층(56)과 제1도전층(54)을 식각하는 동안 상기 캐핑막패턴(61)이 제거된다. (도 4c 참조)Here, the capping layer pattern 61 is removed while the second conductive layer 56 and the first conductive layer 54 are etched. (See Figure 4c)
이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 제조방법은, 소자분리절연막 또는 도전배선을 형성하는 경우 소자분리마스크로 사용되는 질화막 상부 또는 도전배선 상부에 형성되는 마스크절연막 상에 실리콘 또는 도전배선과 같은 종류의 물질로 캐핑막을 형성한 후 사진식각공정을 실시함으로써 캐핑막의 증착두께를 감소시킬 수 있고, 식각공정 시 상기 마스크절연막의 손실을 방지하여 후속 공정으로 형성되는 소자와의 절연 특성을 향상시켜 소자의 수율 및 신뢰성을 향상시키는 이점이 있다.As described above, the method of manufacturing a semiconductor device according to the present invention may include silicon or conductive wiring on a mask insulating film formed on an upper portion of a nitride film or on a conductive wiring, which is used as a device isolation mask when forming a device isolation insulating film or a conductive wiring. By forming a capping film of the same type of material and then performing a photolithography process, the deposition thickness of the capping film can be reduced. There is an advantage of improving the yield and reliability of the device.
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| KR101033985B1 (en) * | 2004-11-19 | 2011-05-11 | 주식회사 하이닉스반도체 | Method for forming bit lines of semiconductor devices |
| CN112582261A (en) * | 2019-09-27 | 2021-03-30 | 长鑫存储技术有限公司 | Method for manufacturing memory node contact window |
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| KR100278652B1 (en) * | 1998-01-13 | 2001-02-01 | 윤종용 | Manufacturing method of tungsten pattern for semiconductor device |
| KR100275731B1 (en) * | 1998-05-25 | 2001-01-15 | 윤종용 | Gate electrode and manufacturing method of the same and self-aligned contact using anti-reflective coating film |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR101033985B1 (en) * | 2004-11-19 | 2011-05-11 | 주식회사 하이닉스반도체 | Method for forming bit lines of semiconductor devices |
| CN112582261A (en) * | 2019-09-27 | 2021-03-30 | 长鑫存储技术有限公司 | Method for manufacturing memory node contact window |
| CN112582261B (en) * | 2019-09-27 | 2022-03-08 | 长鑫存储技术有限公司 | Method for manufacturing memory node contact window |
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