JP2000058511A - Dry etching method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a gate insulating film from being broken and, at the same time, to well maintain the uniform anisotropic shape of the insulating film without relying upon the roughness and denseness of a pattern. SOLUTION: In a dry etching method, a mask pattern 15 is formed on a semiconductor layer 14A and first etching treatment is performed for removing about 70% of the areas of the semiconductor layer 14A under the openings of the mask pattern 15 by using a first etching gas containing chlorine and bromine. Then second etching treatment is performed for removing the areas of the semiconductor layer 14A under the openings of the mask pattern 15 by using second etching gas containing more bromine than chlorine.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dry etching method in a process for manufacturing a semiconductor device made of a silicon-based semiconductor.

[0002]

2. Description of the Related Art In recent years, finer design rules have been more and more advanced along with higher integration and higher speed of semiconductor devices. Accordingly, in a processing field using dry etching, high anisotropy, high selectivity, high etching rate, and the like of a shape are required. Generally, for etching a silicon-based semiconductor layer such as single-crystal silicon, polycrystalline silicon, and polycide, chlorine, which is a halogen-based gas,
It is performed using a gas obtained by adding oxygen to hydrogen bromide.For example, when processing a gate electrode, a method of performing etching until a base gate oxide film appears and overetching the remainder is used. General.

[0003]

However, the conventional dry etching method has the following problems. FIG. 11 shows a sectional configuration of a gate electrode forming step in a Gbit class DRAM device. As shown in FIG. 11, a gate oxide film 102 is formed on an upper surface of a semiconductor substrate 101 made of silicon, and a plurality of gate electrodes 103 made of polycrystalline silicon are formed by dry etching. A mask pattern 104 is formed on the upper surface of each gate electrode 103. Since the thickness of the gate oxide film 102 is reduced to 4 nm or less, the conventional Cl ₂
In the etching of polycrystalline silicon using a Cl ₂ / O ₂ gas containing O ₂ and O ₂ , the selectivity of polycrystalline silicon to the gate oxide film 102 is small, and the oxide film tear 105 occurs in the gate oxide film 102. I will. That is,
In this etching step, the mean free path of the ion species is made sufficiently longer than the sheath length of the plasma or the energy of the ion species is increased by increasing the degree of vacuum to obtain a good anisotropic shape. However, in this case, the selectivity with respect to the gate oxide film 102 of polycrystalline silicon is further reduced, so that the gate oxide film 102 is broken.

On the other hand, a polycrystalline silicon gate oxide film 10
To increase the selectivity to 2, a method has been proposed in which oxygen or hydrogen bromide (HBr) is added to the etching gas. In this case, as shown in FIG. 12, the dimension b of the gate electrode 103 after etching becomes larger than a predetermined mask dimension a, and there is a problem that an anisotropic shape cannot be obtained.

As described above, there is a trade-off between the etching shape in the direction perpendicular to the substrate surface and the selectivity.

Further, in order to increase the speed of the device, when the device has a dual gate structure in which n-type and p-type doped gate electrodes coexist, the n-type polysilicon and the p-type polysilicon are Are etched at the same time,
The difference in the etching rate is caused by the difference in the dopant.
That is, since the etching rate of n-type polycrystalline silicon is higher than that of p-type polycrystalline silicon, the n-type region is etched first, and when all the p-type regions are etched, the gate is formed at the n-type region. Oxide film tearing occurs. Further, a difference occurs in a dimensional shift after etching due to a difference in etching rate.

Further, since the exposure wavelength in lithography is shortened, the depth of focus becomes shallower.
If the resist mask is not thinned, high resolution cannot be obtained, and a problem arises in the resistance of the resist mask when etching the silicon-based semiconductor layer.

SUMMARY OF THE INVENTION The present invention solves the above-mentioned conventional problems, prevents a gate insulating film from being broken, and enables a uniform and anisotropic shape to be favorably maintained without depending on a difference in pattern density. With the goal.

[0009]

In order to achieve the above-mentioned object, the present invention provides a semiconductor device, comprising: an insulating film formed on a substrate; When forming an element pattern including by etching, a first etching step having a high anisotropy and a second etching step having a high selectivity to an insulating film are provided.

[0010] Specifically, the first dry etching according to the present invention includes an insulating film forming step of forming an insulating film on a substrate and a semiconductor layer depositing step of depositing a semiconductor layer containing silicon on the insulating film. And the width of the opening is 0.
A mask pattern forming step of forming a mask pattern including an opening pattern of 5 μm or less, and etching of the semiconductor layer using the mask pattern as a mask and a first etching gas containing chlorine and bromine,
A first etching step of removing a part of a region below an opening of a mask pattern in a semiconductor layer in a depth direction, and using a mask pattern as a mask, a ratio of bromine to chlorine is larger than that of the first etching gas. The second etching gas is used to etch the semiconductor layer, thereby removing a portion of the semiconductor layer below the opening of the mask pattern and remaining in the first etching step. An etching step.

According to the first dry etching method, the first etching step comprises forming a silicon-based reaction product of SiCl _x or SiBr _{x on} a side surface of a semiconductor layer to be patterned while forming a silicon-based reaction product on a side surface perpendicular to the substrate surface. Etching is performed while maintaining the above. Since the first etching gas contains chlorine and bromine, good anisotropy can be maintained. Also,
In the second etching step of etching the portion remaining in the first etching step, the second etching gas has a larger ratio of bromine to chlorine than the first etching gas. Of the insulating film is improved.

In a second dry etching method according to the present invention, an insulating film forming step of forming an insulating film on a substrate, a p-type region doped with a p-type impurity and an n-type Forming a semiconductor layer including silicon having an n-type region doped with an impurity; and forming a semiconductor layer having a width of 0.5 μm or less on the p-type region and the n-type region of the semiconductor layer. A mask pattern forming step of forming a mask pattern including an opening pattern, and etching of the semiconductor layer with a first etching gas containing chlorine and bromine using the mask pattern as a mask, thereby forming a p-type semiconductor layer. A first etching step of removing portions of the mask pattern in the depth direction below the openings in the region and the n-type region, and a first etching process using the mask pattern as a mask. Using a second etching gas having a larger ratio of bromine to chlorine than the etching gas, in the first etching step in the region under the opening of the mask pattern in the p-type region and the n-type region of the semiconductor layer; And a second etching step for removing the remaining portion.

According to the second dry etching method, in the first etching step, the first etching gas contains chlorine and bromine, so that the anisotropy can be favorably maintained. Also,
In the second etching step of removing the portion remaining in the first etching step, the second etching gas is the first etching gas.
Since the ratio of bromine to chlorine is larger than that of the etching gas, the selectivity of the semiconductor layer to the insulating film is improved.

In the first or second dry etching method, the mask pattern is preferably made of an insulating film.

In the first or second dry etching method, it is preferable that the first etching gas contains oxygen.

In the second dry etching method, the first etching step is performed until just before the insulating film on the n-type region is exposed.
It is preferable to perform etching until a part of the insulating film on the mold region is exposed. In this case, the n-type region of the semiconductor layer containing silicon has a higher etching rate than the p-type region, but is etched until just before the insulating film on the n-type region is exposed in the first etching step.
The insulating film is not exposed in both the n-type region and the p-type region. Further, in the second etching step having a high selectivity with respect to the insulating film of the semiconductor layer, the etching is performed until a part of the insulating film on the n-type region is exposed, so that the insulating film is exposed in the n-type region. Also, the insulating film is not broken.

In the first or second dry etching method, the etching rate in the first etching step is preferably higher than the etching rate in the second etching step. In this case, since the reaction product is unlikely to deposit on the side surface of the semiconductor layer to be etched, high etching anisotropy can be maintained.

In the first or second dry etching method, it is preferable that the first etching gas and the second etching gas include Cl ₂ , HCl, SiCl ₄ or BCl ₃ .

In the first or second dry etching method, it is preferable that the first etching gas and the second etching gas include Br ₂ , HBr, SiBr ₄ or BBr ₃ .

A third dry etching method according to the present invention includes an insulating film forming step of forming an insulating film on a substrate, a semiconductor layer depositing step of depositing a semiconductor layer containing silicon on the insulating film, On the layer, the width of the opening is 0.5 μm
A mask pattern forming step of forming a mask pattern including an opening pattern described below, and etching of the semiconductor layer using the mask pattern so as to obtain an inverse microloading effect; A first etching step of removing a part of the lower region of the semiconductor layer in the depth direction, and etching the semiconductor layer using a mask pattern so as to obtain a microloading effect. And a second etching step of removing a portion under the opening of the mask pattern and remaining in the first etching step.

According to the third dry etching method, in the first etching step, etching is performed so as to obtain an inverse microloading effect. Therefore, the etching rate is high in a region where the opening pattern is dense, and small in a region where the opening pattern is sparse. Become. On the other hand, in the second etching step of etching the portion remaining in the first etching step, the etching is performed so as to obtain the microloading effect. Area is large.

[0022]

(First Embodiment) A first embodiment of the present invention.
The dry etching method according to the embodiment will be described with reference to the drawings.

FIGS. 1 and 2 show cross-sectional structures in a process order of a method of manufacturing a semiconductor device using a dry etching method according to a first embodiment of the present invention.

First, as shown in FIG. 1A, an element isolation region 12 made of LOCOS and a gate oxide film 13 as an insulating film having a thickness of about 4 nm are formed on the upper surface of a substrate 11 made of silicon. I do. Thereafter, a semiconductor layer 14A made of polycrystalline silicon having a thickness of about 250 nm is deposited over the entire surface of the substrate 11, and subsequently, the semiconductor layer 14A is doped with n-type impurity phosphorus (P) to form a semiconductor layer. 14A is an n-type. Thereafter, an antireflection film (ARC: Anti Reflective Coat) having a thickness of about 0.65 μm is added at a predetermined position on the semiconductor layer 14A.
ing) 15a and a resist film 15b are applied. Subsequently, a mask pattern 15 including an antireflection film 15a and a resist film 15b having a dense region 1A and a sparse region 1B is formed using photolithography. Here, the opening width of the mask pattern 15 in the dense area 1A is about 0.25 μm, and the opening width in the sparse area 1B is about 1 μm.

Next, as shown in a first etching step of FIG. 1B, the substrate 11 is subjected to inductively coupled plasma (ICP:
Inductively Coupled Plasm
a) The apparatus is put into an etching apparatus, and first, a so-called breakthrough etch for removing a natural oxide film on an exposed surface of the semiconductor layer 14A using Cl ₂ gas is performed. Thereafter, a first etching process is performed using the mask pattern 15 to remove about 70% of a region below the opening of the mask pattern 15 in the semiconductor layer 14A. The etching conditions are as shown below.

[First Etching Condition] Cl ₂ flow rate 30 sccm HBr flow rate 30 sccm Gas pressure 5 mTorr ICP power 200 W RF bias power 200 W Substrate temperature 50 ° C.

Next, as shown in the second etching step of FIG. 2A, the first etching process and the etching conditions are switched, and the portion of the semiconductor layer 14A remaining in the first etching process is removed. By performing a second etching process having a high selectivity of the semiconductor layer 14A with respect to the gate oxide film 13, the gate electrode 14 made of the semiconductor layer 14A is formed.
B are respectively formed. The etching conditions are as shown below.

[Second Etching Condition] Cl ₂ flow rate 20 sccm HBr flow rate 180 sccm He + O ₂ flow rate 3 sccm (He: O ₂ = 7: 3) Gas pressure 10 mTorr ICP power 200 W RF bias power 50 W Substrate temperature 50 ° C. Oxygen (O ₂ ) is used after being diluted with helium (He) so that its flow rate can be easily controlled.

In the second etching step, the ratio of bromine (Br) in the etching gas is increased and a small amount of oxygen (O ₂ ) is added to the etching gas, as compared with the first etching step. As a result, the etching selectivity of the semiconductor layer 14A to the gate oxide film 13 increases. As a result, it is possible to prevent the oxide film from being broken.

Here, as shown in FIG. 2A, a residual portion 14a that remains without removing the semiconductor layer 14A is formed near the step portion of the element isolation region 12. in this way,
In the second etching step, the end point of the dry etching is detected, but the time until a part of the gate oxide film 13 is exposed is measured in advance, and the etching is performed for the measured time. You may.

Next, as shown in FIG. 2B, the remaining portion 14a is removed by performing over-etching as a third etching step. The etching conditions for over-etching are as follows.

[Third Etching Conditions] HBr flow rate 100 sccm He + O ₂ flow rate 3 sccm (He: O ₂ = 7: 3) Gas pressure 60 mTorr ICP power 200 W RF bias power 200 W Substrate temperature 50 ° C.

In the third etching step, since only bromine (Br) is used as halogen in the etching gas, etching with extremely high selectivity to the gate oxide film 13 can be performed.

As described above, according to the present embodiment, as shown in FIG. 2B, a gate electrode 14B having a uniform and highly anisotropic shape can be formed.

In the present embodiment, the end point of the first etching step is set to around 70% of the thickness of the semiconductor layer 14A.
Similar effects can be obtained even when 90% etching is performed.

The same effect can be obtained by doping the semiconductor layer 14A with boron (B) to make the semiconductor layer 14A p-type.

(Second Embodiment) Hereinafter, a dry etching method according to a second embodiment of the present invention will be described with reference to the drawings.

FIGS. 3 and 4 show cross-sectional structures in the order of steps of a method for manufacturing a semiconductor device using the dry etching method according to the second embodiment of the present invention.

First, as shown in FIG. 3A, an element isolation region 22 made of LOCOS and a gate oxide film 23 having a thickness of about 4 nm are formed on the upper surface of a substrate 21 made of silicon. Thereafter, a semiconductor layer 24 made of polycrystalline silicon having a thickness of about 250 nm
A is deposited, and then the semiconductor layer 24A is doped with phosphorus (P) as an n-type impurity to make the semiconductor layer 24A n-type. Thereafter, an antireflection film 25a and a resist film 25b each having a thickness of about 0.65 μm are applied to predetermined positions on the semiconductor layer 24A. Subsequently, a mask pattern 25 including an antireflection film 25a and a resist film 25b having a dense region 1A and a sparse region 1B is formed by using photolithography. Here, the opening width of the mask pattern 25 in the dense area 1A is about 0.25 μm, and the opening width in the sparse area 1B is about 1 μm.

Next, as shown in the first etching step of FIG. 3B, the substrate 21 is put into an ICP etching apparatus, and the natural oxide film on the exposed surface of the semiconductor layer 24A is removed using Cl ₂ gas. After that, a first etching process is performed using the mask pattern 25 to remove about 70% of a region below the opening of the mask pattern 25 in the semiconductor layer 24A. The etching conditions are as shown below.

[First Etching Condition] Cl ₂ flow rate 30 sccm HBr flow rate 30 sccm He + O ₂ flow rate 7 sccm (He: O ₂ = 7: 3) Gas pressure 5 mTorr ICP power 200 W RF bias power 200 W Substrate temperature 50 ° C

As shown in FIG. 3B, an inverse microloading effect appears in which the etching rate is high in the area 1A where the pattern is dense, and the etching rate is low in the area 1B where the pattern is sparse. This is the semiconductor layer 2
When 4A is etched using ions or radicals dissociated or generated from Cl ₂ and HBr, a reaction product consisting of SiO _x is generated because O ₂ is added to the etching gas. Since the amount of this reaction product is reduced in the region 1A where the pattern is dense, it is caused by the relative increase in the etching rate in the region 1A where the pattern is dense.

Next, as shown in the second etching step of FIG. 4A, the first etching processing and the etching conditions are switched, and the remaining portion of the semiconductor layer 24A in the first etching step is removed. By performing a second etching process with high selectivity of the semiconductor layer 24A with respect to the gate oxide film 23, the gate electrode 24 made of the semiconductor layer 24A is formed.
B are respectively formed. The etching conditions are as shown below.

[Second Etching Condition] Cl ₂ flow rate 20 sccm HBr flow rate 180 sccm He + O ₂ flow rate 3 sccm (He: O ₂ = 7: 3) Gas pressure 10 mTorr ICP power 200 W RF bias power 50 W Substrate temperature 50 ° C

In the second etching step, the ratio of bromine (Br) in the etching gas is increased as compared with the first etching step, so that the etching selectivity of the semiconductor layer 24A to the gate oxide film 23 is increased. Become. Under the second etching condition, the incidence of ion species and radical species is reduced in the region 1A where the pattern is dense, so that a microloading effect in which the etching rate in the region 1A where the pattern is dense is relatively reduced appears. Accordingly, the etching selectivity of the semiconductor layer 24A to the gate oxide film 23 is increased, so that the oxide film can be reliably prevented from being broken. As described above, in the second etching step, the end point of the dry etching is detected.
A method may be used in which the time until a portion of 3 is exposed is measured in advance, and etching is performed for the measured time.

Also in this case, as shown in FIG. 4A, a residual portion 24a that remains without removing the semiconductor layer 24A is formed near the step portion of the element isolation region 22.

Next, as shown in FIG. 4B, as a third etching step, over-etching for removing the remaining portion 24a is performed. The etching conditions for over-etching are as follows.

[Third Etching Conditions] HBr flow rate 100 sccm He + O ₂ flow rate 3 sccm (He: O ₂ = 7: 3) Gas pressure 60 mTorr ICP power 200 W RF bias power 200 W Substrate temperature 50 ° C.

In the third etching step, since only Br is used as halogen in the etching gas, etching with extremely high selectivity to the gate oxide film 23 can be performed.

Hereinafter, the reverse microloading effect appearing in the first etching step and the microloading effect appearing in the second etching step will be described in detail.

First, in a first etching step in which O ₂ is added to a halogen-based gas containing Cl ₂ and HBr,
A phenomenon called an inverse microloading effect occurs in which the etching rate is high in the area 1A where the pattern is dense and is low in the area 1B where the pattern is dense. In this phenomenon, the reaction is promoted only by supplying a small amount of oxygen in the region where the pattern interval is small, while the amount of oxygen supplied is relatively large in the region where the pattern interval is large. Occurs when the etching is suppressed by oxidation of the side surface or deposition of a reaction product. This phenomenon is greatest under the third etching condition when the concentration of oxygen added to the etching gas is about 5%. Normally, oxide film breakage is mainly caused by the dense pattern 1A.
This reverse microloading effect is a major factor in oxide film breakage.

Next, in a second etching step using an etching gas containing Br as a main component and oxygen added,
A phenomenon called a microloading effect occurs in which the etching rate is high in the region 1B where the pattern is sparse, and low in the region 1A where the pattern is low. This phenomenon is caused by a difference in the incident amount of radicals due to the difference in density of the pattern due to the shadowing effect of the mask.

As described above, according to the present embodiment, as shown in FIG. 4 (b), the first etching step and the second etching step are continuously performed to achieve the reverse microloading effect and the micro-loading effect. By canceling the two effects of the loading effect, it is possible to form the gate electrode 24B having a uniform and highly anisotropic shape independent of the pattern density difference.

Further, as described above, the oxide film is easily torn in the region 1A where the pattern is dense, but the process utilizing the reverse microloading effect in which the etching rate is increased in the region 1A where the pattern is dense is performed first. Since the step utilizing the microloading effect of reducing the etching rate in the dense region 1A is performed later, it is possible to reliably prevent the oxide film from being broken.

In the present embodiment, the end point of the first etching step is set to around 70% of the thickness of the semiconductor layer 24A.
Similar effects can be obtained even when 90% etching is performed.

The same effect can be obtained by doping the semiconductor layer 24A with boron (B) to make the semiconductor layer 24A p-type.

(Modification of Second Embodiment) A dry etching method according to a modification of the second embodiment of the present invention will be described below with reference to the drawings.

FIGS. 5 and 6 show a sectional structure in the order of steps of a method for manufacturing a semiconductor device using a dry etching method according to a modification of the second embodiment of the present invention. In FIGS. 5 and 6, the same components as those shown in FIGS. 3 and 4 are denoted by the same reference numerals, and description thereof will be omitted.

In this modification, the thickness of the antireflection film 25a and the resist film 25b shown in FIGS.
Instead of the 5 μm mask pattern 25, a thickness of about 10
A mask pattern 26 made of 0 nm silicon oxide is used. Using this mask pattern 26, the first etching step, the second etching step, and the third etching step are successively performed under the same etching conditions as in the second embodiment.

In this manner, the thickness of the mask pattern can be reduced, so that the resolution at the time of exposure is improved, and a dimensional shift is less likely to occur because no reaction product of the resist film 25b is generated. Further, since the resistance to etching is significantly improved as compared with the resist, the accuracy of exposure is improved, and the yield is increased.

Although the silicon oxide film is used for the mask pattern 26, a silicon nitride film may be used.

(Third Embodiment) A dry etching method according to a third embodiment of the present invention will be described below with reference to the drawings.

FIG. 7 and FIG. 8 show cross-sectional structures in the order of steps of a method of manufacturing a semiconductor device using a dry etching method according to the third embodiment of the present invention.

First, as shown in FIG. 7A, an element isolation region 32 made of LOCOS and a gate oxide film 33 having a thickness of about 4 nm are formed on the upper surface of a substrate 31 made of silicon. After that, a semiconductor layer 34 made of polycrystalline silicon having a thickness of about 250 nm
A is deposited, and then the p-type region 2 is formed by selectively doping the semiconductor layer 34A with boron (B) as a p-type impurity, and selectively n-type with respect to the semiconductor layer 34A. The n-type region 3 is formed by doping the type impurity phosphorus (P). Thereafter, an antireflection film 35a and a resist film 35b each having a thickness of about 0.65 μm are applied to predetermined positions on the semiconductor layer 34A. Subsequently, a mask pattern 35 including an antireflection film 35a and a resist film 35b having a dense region 1A and a sparse region 1B is formed in each of the p-type region 2 and the n-type region 3 by using photolithography. . Here, the width of each opening of the mask pattern 35 in the dense region 1A is about 0.25 μm, and the width of each opening in the sparse region 1B is about 1 μm.

Next, as shown in the first etching step of FIG. 7B, the substrate 31 is put into an ICP etching apparatus, and the natural oxide film on the exposed surface of the semiconductor layer 34A is removed using Cl ₂ gas. Thereafter, a first etching process is performed using the mask pattern 35 to remove a part of a region below the opening of the mask pattern 35 in the semiconductor layer 34A. The etching conditions are as shown below.

[First Etching Condition] Cl ₂ flow rate 30 sccm HBr flow rate 30 sccm He + O ₂ flow rate 7 sccm (He: O ₂ = 7: 3) Gas pressure 5 mTorr ICP power 200 W RF bias power 200 W Substrate temperature 50 ° C

As shown in FIG. 7B, the p-type region 2 and the n-type region 2
Since the etching rate is different between the mold region 3 and the impurities contained therein, the etching end point is set to about 70% of the film thickness of the n-type region 3 in the semiconductor layer 34A having a high etching rate. Also in this case, similarly to the second embodiment, an inverse microloading effect in which the etching rate is relatively increased in the region 1A where the pattern is dense appears.

Next, as shown in the second etching step of FIG. 8A, the first etching processing and the etching conditions are switched, and the remaining portion of the semiconductor layer 34A in the first etching step is removed. By performing a second etching process having high selectivity to the gate oxide film 33 with respect to the semiconductor layer 34A, the gate electrode 3 made of the semiconductor layer 34A is formed.
4B are respectively formed. The etching conditions are as shown below.

[Second Etching Conditions] Cl ₂ flow rate 20 sccm HBr flow rate 180 sccm He + O ₂ flow rate 3 sccm (He: O ₂ = 7: 3) Gas pressure 10 mTorr ICP power 200 W RF bias power 50 W Substrate temperature 50 ° C

As shown in FIG. 8A, the end point of the etching is the time when a part of the gate oxide film 33 in the n-type region 3 is exposed. Also in this case, as in the second embodiment, a microloading effect in which the etching rate is relatively reduced in the region 1A where the pattern is dense appears.

Next, as shown in the third etching step of FIG. 8B, the remaining portion 34a of the p-type region 2 and the element isolation region 32 near the step portion without removing the semiconductor layer 34A is removed.
Is over-etched. The etching conditions for over-etching are as follows.

[Third Etching Conditions] HBr flow rate 100 sccm He + O ₂ flow rate 3 sccm (He: O ₂ = 7: 3) Gas pressure 60 mTorr ICP power 200 W RF bias power 200 W Substrate temperature 50 ° C.

In the third etching step, since only Br is used as the halogen in the etching gas, etching with extremely high selectivity to the gate oxide film 33 proceeds.

As described above, according to the present embodiment, there is almost no difference in the etching between the p-type region 2 and the n-type region 3 formed on one semiconductor substrate 31, and the region 1A has a dense pattern. Since the non-uniformity of the etching rate with the sparse region 1B can be canceled out, the gate electrode 34B having a uniform and highly anisotropic shape can be formed.

In the present embodiment, the end point of the first etching step is set to the n-type region 3 in the semiconductor layer 34A.
Is approximately 70% of the film thickness of the n-type region 3, but the same effect can be obtained even when etching is performed at 50% to 90% with respect to the film thickness of the n-type region 3.

(Modification of Third Embodiment) A dry etching method according to a modification of the third embodiment of the present invention will be described below with reference to the drawings.

FIGS. 9 and 10 show cross-sectional structures in the order of steps of a method of manufacturing a semiconductor device using a dry etching method according to a modification of the third embodiment of the present invention. FIG.
In FIG. 10 and FIG. 10, the same components as those shown in FIG. 7 and FIG.

In this modification, the thickness of the antireflection film 35a and the resist film 35b shown in FIGS.
Instead of the 5 μm mask pattern 35, a thickness of about 10
A mask pattern 36 made of 0 nm silicon oxide is used. Using this mask pattern 36, the first etching step, the second etching step, and the third etching step are continuously performed under the same etching conditions as in the third embodiment.

In this way, the thickness of the mask pattern can be reduced, so that the resolution at the time of exposure is improved, and the reaction product of the resist film 35b is not generated, so that a dimensional shift is less likely to occur. Further, since the resistance to etching is significantly improved as compared with the resist, the exposure accuracy is improved, and the yield is increased.

Although the silicon oxide film is used for the mask pattern 36, a silicon nitride film may be used.

In each of the embodiments, the gate electrode is formed by using polycrystalline silicon. However, the present invention is not limited to this. This is effective in performing patterning in which a dense / dense pattern is mixed in a silicon-based semiconductor layer. .

In each of the embodiments and the modifications, polycrystalline silicon is used for the semiconductor layer.
Refractory metal silicide or polycide may be used.

[0083]

According to the first or second dry etching method of the present invention, high anisotropy can be maintained in the first etching step because the etching gas contains chlorine and bromine in the first etching step. By increasing the ratio of bromine to chlorine in the second etching step of etching the remaining portion, the selectivity of the semiconductor layer to the insulating film can be increased. Therefore, the insulating film can be prevented from being broken, so that a highly reliable semiconductor element can be manufactured.

In the first or second dry etching method, when the mask pattern is made of an insulating film, the film thickness can be made smaller than that of the resist mask pattern, so that the resolution at the time of exposure is improved and the reaction of the resist is improved. Since no product is generated, a dimensional shift is less likely to occur. Also, since the resistance to etching is greatly improved compared to resist, the reliability of the mask is improved,
Higher yield.

In the first or second dry etching method, when the first etching gas contains oxygen, if the first etching gas contains a relatively large amount of oxygen with respect to the etching gas,
An inverse microloading effect in which the etching rate is lower in a sparse pattern area than in a dense pattern area appears. In addition, when a relatively small amount of oxygen is contained in the etching gas, a microloading effect in which the etching rate is lower in a dense pattern region than in a sparse pattern region appears. Accordingly, if the reverse microloading effect is used in the first etching step and the microloading effect is used in the second etching step, the difference in the etching rate in the dense / dense pattern is cancelled, and uniform processing can be performed. .

In the first or second dry etching method, when the etching rate in the first etching step is higher than the etching rate in the second etching step, a reaction product is deposited on a side surface of the semiconductor layer to be etched. It is difficult to maintain high anisotropy of etching.

In the first or second dry etching method, when the first etching gas and the second etching gas include Cl ₂ , HCl, SiCl ₄ or BCl ₃ , chlorine is surely contained in the etching gas. be able to.

In the first or second dry etching method, when the first etching gas and the second etching gas include Br ₂ , HBr, SiBr ₄ or BBr ₃ , bromine is surely contained in the etching gas. be able to.

In the second dry etching method, the first etching step is performed until just before the insulating film on the n-type region is exposed, and the second etching step is performed to expose a part of the insulating film on the n-type region. When the etching is performed up to, the n-type region of the semiconductor layer containing silicon has a higher etching rate than the p-type region. However, since the etching is performed until immediately before the insulating film on the n-type region is exposed in the first etching step,
The insulating film is not exposed in both the n-type region and the p-type region. Further, in the second etching step in which the selectivity of the semiconductor layer with respect to the insulating film is large, the etching is performed until part of the insulating film on the n-type region is exposed, so that the insulating film is not broken. Therefore, even when the p-type region and the n-type region are mixed on one semiconductor substrate, the semiconductor layer can be uniformly processed while reliably preventing the insulating film from being broken.

According to the third dry etching method of the present invention, etching is performed in the first etching step so as to obtain the reverse microloading effect,
In the second etching step of etching the portion remaining in the etching step, the etching is performed so as to obtain the microloading effect, so that the difference in the etching rate in the dense / dense pattern is canceled, and uniform processing becomes possible. In general, the insulating film is easily broken in the dense pattern region. However, in the second etching step, the insulating film in the dense pattern region is used because the microloading effect of reducing the etching rate in the dense pattern region is used. Breaking can be reliably prevented.

[Brief description of the drawings]

FIGS. 1A and 1B are cross-sectional views in the order of steps showing a method for manufacturing a semiconductor device using a dry etching method according to a first embodiment of the present invention.

FIGS. 2A and 2B are sectional views in the order of steps showing a method for manufacturing a semiconductor device using a dry etching method according to the first embodiment of the present invention.

FIGS. 3A and 3B are cross-sectional views in the order of steps showing a method for manufacturing a semiconductor device using a dry etching method according to a second embodiment of the present invention.

FIGS. 4A and 4B are cross-sectional views in the order of steps showing a method for manufacturing a semiconductor device using a dry etching method according to a second embodiment of the present invention.

FIGS. 5A and 5B are sectional views in the order of steps showing a method for manufacturing a semiconductor device using a dry etching method according to a modification of the second embodiment of the present invention.

FIGS. 6A and 6B are cross-sectional views in the order of steps showing a method for manufacturing a semiconductor device using a dry etching method according to a modification of the second embodiment of the present invention.

FIGS. 7A and 7B are cross-sectional views in the order of steps showing a method for manufacturing a semiconductor device using a dry etching method according to a third embodiment of the present invention.

FIGS. 8A and 8B are sectional views in the order of steps showing a method for manufacturing a semiconductor device using a dry etching method according to a third embodiment of the present invention.

FIGS. 9A and 9B are sectional views in the order of steps showing a method for manufacturing a semiconductor device using a dry etching method according to a modification of the third embodiment of the present invention.

FIGS. 10A and 10B are sectional views in the order of steps showing a method for manufacturing a semiconductor device using a dry etching method according to a modification of the third embodiment of the present invention.

FIG. 11 is a schematic cross-sectional view showing gate oxide film breakage that occurs when a selectivity to a gate oxide film is small when a conventional dry etching method for a silicon-based semiconductor layer is used.

FIG. 12 is a schematic cross-sectional view showing a taper shape and a dimensional shift of a gate electrode caused when a selectivity to a gate oxide film is increased when a conventional dry etching method for a silicon-based semiconductor layer is used.

[Explanation of symbols]

 Reference Signs List 1A dense region 1B sparse region 2 p-type region 3 n-type region 11 substrate 12 element isolation region 13 gate oxide film (insulating film) 14A semiconductor layer 14a remaining portion 14B gate electrode 15a antireflection film 15b resist film 15 mask pattern 21 Substrate 22 Element isolation region 23 Gate oxide film (insulating film) 24A Semiconductor layer 24a Remaining portion 24B Gate electrode 25a Antireflection film 25b Resist film 25 Mask pattern 26 Mask pattern (insulating film mask) 31 Substrate 32 Element isolation region 33 Gate oxide film (Insulating film) 34A Semiconductor layer 34a Remaining portion 34B Gate electrode 35a Antireflection film 35b Resist film 35 Mask pattern 36 Mask pattern (insulating film mask)

 ────────────────────────────────────────────────── ─── Continuing from the front page (72) Inventor Shunsuke Kugo 1-1, Komachi, Takatsuki-shi, Osaka Matsushita Electronics Co., Ltd. F-term (reference) 5F004 AA01 BA20 BC03 DA00 DA04 DA11 DA22 DA26 DA29 DB03 EA06 EA07

Claims (11)

[Claims] An insulating film forming step of forming an insulating film on a substrate; a semiconductor layer depositing step of depositing a semiconductor layer containing silicon on the insulating film; A mask pattern forming step of forming a mask pattern including an opening pattern having a width of 0.5 μm or less; and etching the semiconductor layer using a first etching gas containing chlorine and bromine using the mask pattern as a mask. Performing a first etching step of removing a part in a depth direction of a region below the opening of the mask pattern in the semiconductor layer; and using the mask pattern as a mask and comparing with the first etching gas. Etching the semiconductor layer using a second etching gas having a high ratio of bromine to chlorine, A second etching step of removing an area below the opening of the mask pattern in the first etching step and remaining in the first etching step. 2. The dry etching method according to claim 1, wherein the mask pattern comprises an insulating film. 3. The dry etching method according to claim 1, wherein the first etching gas contains oxygen. 4. An insulating film forming step of forming an insulating film on a substrate; and a p-type region doped with a p-type impurity and an n-type region doped with an n-type impurity on the insulating film. A semiconductor layer forming step of forming a semiconductor layer containing silicon having: and a mask pattern including an opening pattern having an opening width of 0.5 μm or less on the p-type region and the n-type region of the semiconductor layer. Forming a mask pattern using a first etching gas containing chlorine and bromine by using the mask pattern as a mask, thereby etching the p-type region and the n-type region of the semiconductor layer. A first etching step of removing a portion of the mask pattern in the depth direction below the opening of the mask pattern, and using the mask pattern as a mask, A second etching gas having a larger ratio of bromine to chlorine than a etching gas is used to form the first region in the p-type region and the n-type region of the semiconductor layer below the opening of the mask pattern and the first etching gas; A second etching step of removing a portion remaining in the etching step of (1). 5. The dry etching method according to claim 4, wherein the mask pattern is made of an insulating film. 6. The dry etching method according to claim 4, wherein the first etching gas contains oxygen. 7. The first etching step is performed until just before the insulating film on the n-type region is exposed, and the second etching step is performed on the insulating film on the n-type region. The dry etching method according to claim 4, wherein etching is performed until the portion is exposed. 8. The dry etching method according to claim 1, wherein an etching rate in the first etching step is higher than an etching rate in the second etching step. 9. The first etching gas and the second etching gas may be Cl ₂ , HCl, SiCl ₄ or BC
The dry etching method according to claim 1, wherein the dry etching method includes l ₃ . 10. The first etching gas and the second etching gas may be Br ₂ , HBr, SiBr ₄ or B
The dry etching method according to claim 1 or 4, characterized in that it comprises a br _3. 11. An insulating film forming step of forming an insulating film on a substrate; a semiconductor layer depositing step of depositing a semiconductor layer containing silicon on the insulating film; A mask pattern forming step of forming a mask pattern including an opening pattern having a width of 0.5 μm or less, and performing etching to obtain an inverse microloading effect on the semiconductor layer using the mask pattern. A first etching step of removing a part of the semiconductor layer in a depth direction of a region below the opening of the mask pattern; and using the mask pattern, a microloading effect can be obtained on the semiconductor layer. By performing the etching as described above, the first region in the semiconductor layer below the opening of the mask pattern and A second etching step of removing a portion remaining in the etching step of (1).