JPH1092929A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To surely form via holes through a layer insulation film and metal wiring on this film with reduced number of steps even if the manufacturing process is finely divided. SOLUTION: After planarizing a layer insulation film 24, a conductive film having a lower etching rate than that of a layer insulation film 24 is deposited on the surface of the film 24 in a process condition of via holes, via holes are bored through the conductive film by a photolithography step, using the conductive film with the via holes as a mask, vias are formed through the insulation film 24 and filled up with a conductive material and wiring layer electrically connected to the conductive material is formed on the insulation film 24.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a microfabrication process for realizing high integration, low wiring resistance, high reliability, and low cost. The present invention relates to a technique for etching a connection hole formed in an insulating film and a method for forming a metal wiring formed immediately above the connection hole.

[0002]

2. Description of the Related Art In a semiconductor device, as a manufacturing process is miniaturized and highly integrated, elements such as a transistor constituting an internal circuit are miniaturized, and wiring connecting these elements is also multi-layered. Is done. Accordingly, not only the gate width and the interval of the transistor, the width and the interval of the metal wiring connecting the elements, etc. are reduced, but also the contact holes formed in the first interlayer insulating film and the second and subsequent interlayer insulating films are formed. The diameter of connection holes such as via holes formed in the interlayer insulating film has also been reduced, and the aspect ratio has continued to increase.

However, in the etching step of the connection hole formed in the interlayer insulating film, considering the misalignment in the photolithography step and the processing variation in the photolithography step and the etching step, for example, the hole diameter of the contact hole is The holes must be opened in a size significantly smaller than the gate spacing.

For example, if the design rule is 0.3 μm, the diameter of the connection hole is about 0.15 μm.
Therefore, if the design rule is up to about 0.3 μm, the current manufacturing technologies such as the Poly-Si (polysilicon) sidewall process and the manufacturing method of the semiconductor device disclosed in Japanese Patent Application Laid-Open No. 6-61191 are used. Can be used to form a connection hole. For example, in a design rule of 0.2 μm, the diameter of the connection hole is approximately 0.05 mm in diameter.
Since it is limited to μm, it cannot be manufactured by the current manufacturing technology.

Here, in the Poly-Si sidewall process, a Poly-Si layer is deposited on an interlayer insulating film, and the Poly-Si layer is first formed by a photolithography step and an etching step.
-After opening the connection hole only in the Si layer and removing the resist,
Depositing a poly-Si layer for SW (sidewall) formation and etching back, forming a sidewall with the poly-Si layer for SW formation inside the connection hole formed in the poly-Si layer;
This sidewall reduces the diameter of the connection hole.
The connection holes in the interlayer insulating film are etched using the ly-Si layer as a mask.

Further, the method of manufacturing a semiconductor device disclosed in Japanese Patent Application Laid-Open No. 6-61191 uses a metal film instead of the Poly-Si layer, as in the case of the Poly-Si sidewall process. A metal film for SW formation is used instead of the Poly-Si layer for SW formation, and similarly, a metal sidewall is formed inside a connection hole formed in the metal film on the interlayer insulating film. The connection hole of the interlayer insulating film is etched using the metal film having the reduced hole diameter of the connection hole as a mask.

Further, as a technique for solving fundamental problems such as misalignment in the photolithography step and processing variations in the photolithography step and the etching step, there is, for example, a self-aligned contact (SAC) etching technique. The SAC technique is a technique for reducing the size of the diameter of a contact hole in a self-aligned manner with respect to a gate interval. Hereinafter, the SAC technique will be briefly described by taking a case where a contact hole is opened between gates as an example.

In the SAC technique, first, an oxide film on the gate, such as SiO _2, is formed on the surface of the gate, sidewalls are formed on the side walls of the gate, the source / drain is formed, and then Si ₃ N is formed on the surface. _Then, a stopper layer such as ₄ is deposited, and SiO _{2 serving} as an interlayer insulating film is further deposited and planarized. Thereafter, a resist pattern of a contact hole is formed by a photolithography process, and SiO _{2 serving as} an interlayer insulating film is formed according to etching conditions. To the stopper layer S
Etch with high selectivity to i ₃ N ₄ .

Then, the stopper layer Si ₃ N ₄ is replaced with S
S on the surface of i-substrate, oxide film on gate and sidewall
By etching while ensuring the selectivity to iO ₂ , a contact hole is opened in a self-aligned manner between the side edges of the gate. The advantage of this method is that it not only can absorb the misalignment during the formation of the contact mask in the photolithography process, the variation in the photo size (the processing size in the photolithography process), but also can open the photo size more than the gate interval. That you can do it.

However, the above-described conventional method for manufacturing a semiconductor device has various problems as described below.

In the current etching method, the photoresist
Of the interlayer insulating film using_TwoTo open a connection hole at
C as an etching gas for_FourF₈Large C / F ratio
Threshold gas is selected, and SiO_TwoOpened in
S of the side wall of the connection hole, the surface of the Si substrate and the stopper layer
i_ThreeN_FourC to be a protective film on the surface_xF_yPolymer deposited
Etching while etching, Si substrate or SAC
Stopper layer Si _ThreeN_FourThe selection ratio for
One, SiO of interlayer insulating film_TwoIs being etched.

However, first, in the etching by the SAC technique, the ion incident angle at the gate corner becomes large, and the sputtering effect at the gate corner becomes strong, so that the stopper layer Si ₃ N _{4 is formed.}
It is difficult to form a connection hole in SiO _{2 of the} interlayer insulating film while ensuring the selectivity to the insulating film. For this reason, it is necessary to select a gas having a higher C / F ratio as an etching gas and deposit a stronger and more sufficient C _x F _y polymer than ever before on the Si ₃ N ₄ surface of the stopper layer.

In the etching by the SAC technique,
Certainly, the contact hole and the Si substrate are connected in a self-aligned manner, and the alignment margin in the photolithography process of the contact hole can be expanded. However, for the purpose of high integration, the upper diameter of the contact hole is unnecessarily large. Cannot be expanded, ie
The design rule of the first metal wiring layer cannot be relaxed.

Therefore, in the SAC technique, although the rate of miniaturization of the contact hole size can be temporarily reduced, the photo size of the contact hole is eventually reduced to 0.2 μm.
m, the etch stop due to the deposition of deposits such as polymers on the bottom of the contact hole, the increase in contact resistance due to the injection of sidewall deposits and decomposed species of etching gas to the substrate surface, C / Use of a gas having a large F ratio causes various problems such as a decrease in yield due to generation of particles in the manufacturing apparatus.

Further, as a problem before that, when the gate interval becomes narrow, the Si ₃ N of the SAC stopper layer is reduced.
₄ is that a V-shaped slit is formed between the gates, so ironically, the gap is much smaller than the photoresist dimensions of the contact holes and the distance between the side walls of the parallel gates (that is, the diameter of the contact hole to be formed). In this case, the SiO ₂ of the interlayer insulating film formed must be removed, and the deposit which has served as a sidewall protective film at the time of etching is deposited on the V-shaped portion, and an etch stop occurs at this time. become.

On the other hand, the poly-Si sidewall process and the metal sidewall process in the method of manufacturing a semiconductor device disclosed in Japanese Patent Application Laid-Open No. 6-61191 also have the problem of increasing the number of steps, although they are advantageous. And variations in the formation of the contact hole mask (variations in the thickness of the poly-Si layer for the mask or metal film for the mask, variations in the processing dimensions in the photolithography and etching processes, etc.), variations in the thickness when depositing the sidewall film, and etching. There is a drawback that dimensional variations and the like of the sidewalls at the time overlap, and dimensional accuracy cannot be obtained.

In particular, the method of manufacturing a semiconductor device disclosed in Japanese Patent Application Laid-Open No. 6-61191 is apparently similar to the present invention, but differs greatly in the following points. That is, since it is a metal mask, sufficient selectivity can be ensured when etching the interlayer insulating film. However, as long as it is a side wall process, a mask metal is used so that the connection holes are not filled. A film thickness exceeding a certain value determined by the hole diameter of the connection hole formed in the film, the hole diameter of the final connection hole, the coverage at the time of depositing the SW forming metal film, and the like cannot be deposited, and almost the side wall Only thickness can be deposited.

In this case, since the SW forming metal film serving as the connection hole mask is thin, so-called under-etching occurs in which the lower side of the mask is etched by an obliquely incident etchant. In order to prevent this and increase the anisotropy, the material (mainly organic material) for forming the sidewall protective film, which has been conventionally supplied from the resist, must be supplied from the etching gas. As a result, C / F The use of a gas with a high deposition ratio and a high ratio causes various problems exactly the same as those in the SAC technology.

[0019]

SUMMARY OF THE INVENTION An object of the present invention is to solve the problems based on the above-mentioned prior art, and to reduce the number of steps even in a case where the manufacturing process is miniaturized. It is an object of the present invention to provide a method of manufacturing a semiconductor device in which a hole can be reliably formed and a metal wiring in an upper layer can be formed.

[0020]

In order to achieve the above object, the present invention provides a method of manufacturing a semiconductor device, comprising the steps of: planarizing an interlayer insulating film; Also, a conductive film having a low etching rate is deposited, the connection hole is formed in the conductive film by a photolithography process, and the conductive film having the connection hole formed therein is used as a connection hole mask to form the interlayer insulating film. Then, a conductive material is buried in the connection hole of the opened interlayer insulating film, and a wiring layer electrically connected to the conductive material is formed on the interlayer insulating film. And a method of manufacturing a semiconductor device.

Here, it is preferable that the wiring layer is formed by patterning a wiring pattern on the conductive film used as the connection hole mask. Further, the formation of the wiring layer is performed after the connection hole is opened in the interlayer insulating film, and after removing the conductive film used as the connection hole mask to expose the surface of the interlayer insulating film, A conductive material is buried in the connection hole of the interlayer insulating film, and then, on the interlayer insulating film, a new conductive film electrically connected to the conductive material in the connection hole is formed. It is also preferable that the wiring pattern is formed by patterning a wiring pattern on a conductive film. Further, the formation of the wiring layer includes:
After burying a conductive substance in the connection hole of the interlayer insulating film, the conductive film used as the connection hole mask is removed to expose the surface of the interlayer insulating film, and then, on the interlayer insulating film, It is also preferable that a new conductive film electrically connected to the conductive substance in the connection hole is formed, and a wiring pattern is patterned on the new conductive film.

Further, according to the present invention, after the interlayer insulating film is planarized, a conductive film is deposited on the surface of the interlayer insulating film, and the conductive film is formed by any of an electron beam, an ion beam, and a laser beam.
The conductive film and the interlayer insulating film are continuously directly opened under an etching atmosphere adapted for each film, and thereafter, a conductive material is embedded in a connection hole of the opened interlayer insulating film, It is another object of the present invention to provide a method of manufacturing a semiconductor device, wherein a wiring layer electrically connected to the conductive material is formed on an interlayer insulating film.

In the method of manufacturing a semiconductor device according to the present invention, after the interlayer insulating film is planarized, a conductive metal film is deposited on the entire surface of the interlayer insulating film, and the connection is performed by a photolithography step and an etching step. A resist mask for the holes is formed, and first, only the metal film is etched to open the connection holes. As will be described later, when this metal film is used as a wiring layer, a stacked structure of two or more layers may be used in advance when depositing the metal film at this stage.

In the subsequent step, alignment is performed with respect to the gate and the metal wiring in the lower layer from above the opaque metal film. Therefore, as a pre-process for depositing the metal film, after the interlayer insulating film is planarized, First, a concave portion serving as an alignment mark is formed in the interlayer insulating film by a photolithography process and an etching process, or directly by a laser beam, an electron beam, an ion beam, or the like. Since the surface of the metal film deposited on the surface of the interlayer insulating film reflects the concave portion of the mark, the resist mask of the connection hole is aligned with the mark.

After the metal film is etched to remove the resist used to form the connection holes, the metal film having the connection holes formed therein is used as a connection hole mask instead of this resist, and the etching process is performed. Then, a connection hole is opened by etching the interlayer insulating film. The etching gas at this time is
When the interlayer insulating film is made of silicon oxide, a non-depositing gas such as F ₂ , NF ₃ or SF ₆ is mainly used. When the interlayer insulating film is made of an organic compound such as polyimide, non-deposited gas such as O ₂ is mainly used. A deposition gas is used.

The side wall deposit of the connection hole can be peeled off in a subsequent peeling step, no etch stop occurs, the shape does not become bowing, the connection hole resistance does not increase due to carbon C injection, A C-containing gas may be added if the adverse effect is small, such as no abnormal generation of particles, and within an allowable range. Since the main etchant of the interlayer insulating film is F and an F-containing species (such as O ₂ when the interlayer insulating film is an organic substance), sufficient selectivity is secured for a metal film used as a connection hole mask. And there is no dimensional variation component due to erosion unlike a resist.

Since the connection hole formed in the metal film functions as an orifice, the etchant reaching the bottom of the connection hole when etching the interlayer insulating film to form the connection hole depends on its thickness. Can be restricted to those having a certain direction. That is, components other than the substantially vertical components of the etchant collide with the side surfaces of the connection holes formed in the metal film, are adsorbed or recombined, and then desorb. In order to adsorb or recombine components other than the substantially vertical components of the etchant, it is particularly effective to cool the wafer.

Here, the degree of integration is relatively low, that is,
If the diameter of the connection hole is relatively large and the level of carbon C due to the resist injected into the bottom of the connection hole is acceptable, or if a resist with high etching resistance is used, it is used for patterning the connection hole of the metal film. The resist which has been used can be used as it is for processing the interlayer insulating film, and when the integration degree is high, that is, when the hole diameter of the connection hole is relatively small and the use of the resist is inappropriate for patterning the connection hole, After passivating the surface of the metal film as necessary, use an electron beam, ion beam, laser beam, etc., continuously in the etching atmosphere, including the metal film and even the interlayer insulating film. The holes may be opened directly.

As described above, in the present invention, no resist is used for etching the interlayer insulating film and no deposition gas such as carbon C is used, or only a minimum amount is used as an auxiliary for maintaining the shape. Therefore, there is no bowing of the shape due to excessive deposits, etch stop at the slit portion of the stopper layer such as Si ₃ N ₄ due to deposition of deposits in the connection holes, side wall deposits of connection holes and etching gas. Increasing the contact hole resistance by injecting carbon C into the substrate surface of the decomposed species, decreasing the yield due to the generation of particles in the manufacturing apparatus by using a gas having a large C / F ratio, etc.
Various problems that have occurred in the conventional method of manufacturing a semiconductor device can be avoided even in the processing of a finer connection hole.

After the etching of the connection hole in the interlayer insulating film is completed, after washing and / or surface treatment for the next step are performed as necessary, the conductive material is embedded in the connection hole. Done. The embedding method may be a CVD method, a sputtering method or a reflow method. Further, a blanket method or a selective growth method may be used. As a result, the conductive substance is in electrical contact with the metal film used as the connection hole mask, so that the metal film used as the connection hole mask can be used as it is as the wiring film.

After the conductive material is buried in the connection hole, the conductive material used for burying the connection hole is deposited on the entire surface of the metal film used as the connection hole mask. In order to ensure the flatness of the metal wiring in the subsequent process for the photolithography process, or the compatibility at the time of wiring etching is poor, the characteristics of the metal film as a connection hole mask and the characteristics required as a wiring material are different. When a defect such as a difference occurs, an unnecessary portion of the surface may be removed by etch back or a CMP process.

At this time, a part or all of the conductive substance used for filling the connection hole deposited on the entire surface of the metal film used as the connection hole mask may be removed. Part or all of the metal film used as the mask may be removed. That is, after removing the entire metal film used as the connection hole mask until the interlayer insulating film is exposed, a new metal film serving as a wiring layer may be deposited on the entire surface of the interlayer insulating film. The metal film may have a laminated structure.

Conversely, an anti-reflection film such as TiN is formed on the outermost surface in order to improve the reliability of the wiring, for example, in order to avoid the reflection of the underlying film during the photolithography process in the subsequent process. At this point, a heterogeneous film may be further deposited. In particular, W (tungsten) or the like is selected as the filling material in the contact hole, and Ti is used as a base treatment prior thereto.
By depositing N by sputtering or CVD,
Since this TiN is located on the wiring surface in the flat portion, it can also serve as an antireflection film.

Thereafter, a photolithography process is performed on the upper metal wiring layer. The alignment is performed on the alignment mark and the connection hole of the metal film, and the metal wiring is etched at low cost. Can be formed.

The method of manufacturing a semiconductor device according to the present invention comprises:
The present invention is not limited to the contact hole connecting the first metal wiring layer and the substrate or the gate. The present invention can be applied to a via hole which is a connection hole between upper and lower metal wirings. SA
C) Applicable to technology. Further, since the method of manufacturing a semiconductor device according to the present invention is a process in which the deposition of deposits is suppressed to a minimum as described above, in the future, for example, if the manufacturing process is reduced to a size of 0.2 μm or less, miniaturization will proceed. Even, Si
Not etch stop occurs at the slit portions of the stopper layer, such as ₃ N _4, it may be opening a connection hole.

[0036]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of a method for manufacturing a semiconductor device according to the present invention will be described in detail based on a preferred embodiment shown in the accompanying drawings. 1 to 7 are conceptual diagrams illustrating a method for manufacturing a semiconductor device according to the present invention, and show an example in which a contact hole is formed between gates. First, in the semiconductor device 10 shown in FIG. 1, the semiconductor device 10 is separated by a field oxide film 11 and is formed on a semiconductor substrate 12 by an MO including a gate, a source and a drain.
A semiconductor element such as an S transistor is formed.

Here, the oxide film 14 on the gate is formed by depositing an oxide film continuously after depositing the gate film 16 and using the resist mask of the gate.
Are continuously etched under the respective conditions. Impurities are implanted into the substrate 12 before and after the formation of the sidewalls 18 to form source / drain regions 20,
After depositing Si ₃ N ₄ of the stopper layer 22 by CVD, SiO ₂ of the interlayer insulating film 24 is deposited by CVD, and the surface is subjected to CMP (chemical mechanical polishing).
Flatten using an apparatus.

Then, Al (aluminum), Cu (copper), W (tungsten), A
A metal film 26 such as u (gold) is deposited, and a resist mask 28 for a contact hole is formed on the metal film 26 by a photolithography process. At this time, the metal film 26 is deposited to a thickness required for characteristics in using it as a wiring in a later step, but a stacked structure may be formed by depositing two or more types of conductive materials. In this case, the alignment is performed using a concave portion formed by flattening the interlayer insulating film 24, forming an alignment mask by a photolithography process, and etching the underlying interlayer insulating film 24 to a small depth.

Then, as shown in FIG. 2, the metal film 26 is etched by a photolithography process using a resist mask 28 for the contact hole, and a contact hole 30 is opened in the metal film 26.
8 is removed by ashing and washing. Next, as shown in FIG. 3, instead of the resist 28, the metal film 26 in which the contact hole 30 is opened is used as a mask for the contact hole, and the SiO ₂ of the interlayer insulating film 24 is plasma-etched under high vacuum. To form a contact hole 30.

At this time, by optimizing the etching parameters, first, the Si ₃ N
₄ is not to be etched off. Further, the wafer is cooled, and an etchant component which does not enter the contact hole 30 formed in the metal film 26 almost perpendicularly into the contact hole 30 is formed on the metal film 2.
6 so as to be adsorbed on the side wall of the contact hole 30 opened in FIG. Thereafter, the stopper layer 22 is formed of Si ₃ N ₄
Is etched off under conditions having good selectivity with respect to the substrate 12, the gate oxide film 32, and the sidewalls 18.

Next, as shown in FIG. 4, as a pretreatment for the next step, after cleaning the inside of the contact hole 30 and the surface portion, performing a surface treatment or forming a conductive thin film as necessary, the CVD method is performed. , W, TiN, A
A contact hole filling material 34 such as 1 or Au is deposited on the surface and is filled in the contact hole 30. Then, FIG.
As shown in (2), the surface is etched back or planarized by CMP or the like as necessary.

At this time, the metal film 26 has excellent characteristics as a mask when the interlayer insulating film 24 is etched, but if the metal film 26 is insufficient as a wiring material, the metal film 26 is etched back or CMP to form the interlayer insulating film 24. The processing may be performed until the temperature reaches the temperature, and once completely removed, a new wiring material may be deposited. Further, when light reflection on the surface of the metal film 26 has an adverse effect during the photolithography process for the upper layer, or when the characteristics of the wiring cannot be ensured by a single layer, an antireflection film is formed on the surface. Alternatively, a laminated structure may be formed by depositing another conductive material.

Finally, as shown in FIG. 6, a resist mask 36 of a first metal wiring layer is formed on the thus obtained surface by a photolithography process.
By etching, a first metal wiring pattern 38 as shown in FIG. 7 is formed.

Although the method of manufacturing a semiconductor device according to the present invention has been described in detail above, the present invention is directed to the types of the metal films, the alignment method for forming the connection holes in the metal film, and the formation of the connection holes in the metal film in the above embodiments. It is not limited to the method, the filling material in the connection hole, various flattening methods, the structure of the self-aligned contact and the use thereof, the etching method of the interlayer insulating film, and the like, and can be variously changed without departing from the gist thereof. Needless to say, there is.

[0045]

As described above in detail, according to the method of manufacturing a semiconductor device of the present invention, a conductive film is deposited on an interlayer insulating film, and a connection hole is formed in the conductive film by a photolithography process. Then, after opening the connection hole in the interlayer insulating film using the conductive film as a connection hole mask, or continuously opening the connection hole in the conductive film and the interlayer insulating film by an electron beam, an ion beam, and a laser beam. After the hole is formed, a conductive substance is buried in the connection hole to make electrical contact with the conductive film, and a metal wiring is formed using the conductive film as a wiring layer.

According to the method of manufacturing a semiconductor device of the present invention,
A connection hole is formed in the conductive film using a photoresist, and the connection hole is formed in the interlayer insulating film using the conductive film as a connection hole mask, or by using an electron beam, an ion beam, or a laser beam. Since the connection holes are formed in the conductive film and the interlayer insulating film without using a photoresist, the C / F is not used when the connection holes are etched.
It is not necessary to use a deposition gas having a large ratio. For example, even when the manufacturing process is miniaturized to 0.2 μm or less, an etch stop, an increase in contact resistance, and an increase in C
By using a gas having a large / F ratio, various problems such as a decrease in yield due to generation of particles in the manufacturing apparatus can be avoided, and a connection hole can be reliably formed in the interlayer insulating film. In addition, since it can be manufactured without using a resist which is a main source of particles, a product yield is improved, a cleaning cycle of a manufacturing apparatus is extended, a processing ability is improved, and a metal film used as a connection hole mask is After being electrically connected to the conductive substance embedded in the connection hole, it can be used as a metal wiring, so that the effect of reducing the manufacturing cost by reducing the number of steps and the like can be obtained. In addition, according to the method for manufacturing a semiconductor device of the present invention,
At the time of processing the interlayer insulating film, the portions other than the connection holes are covered with an opaque metal film used as a connection hole mask, so that damage to the underlying element and the interlayer insulating film caused by energy light such as ultraviolet rays generated from plasma can be reduced. Further, by directly patterning the resist mask of the connection hole by electron beam drawing or the like, there is also an effect that a trouble due to charge-up can be prevented.

[Brief description of the drawings]

FIG. 1 is a conceptual diagram illustrating a method for manufacturing a semiconductor device of the present invention.

FIG. 2 is a conceptual diagram illustrating a method for manufacturing a semiconductor device of the present invention.

FIG. 3 is a conceptual diagram illustrating a method for manufacturing a semiconductor device according to the present invention.

FIG. 4 is a conceptual diagram illustrating a method for manufacturing a semiconductor device according to the present invention.

FIG. 5 is a conceptual diagram illustrating a method for manufacturing a semiconductor device of the present invention.

FIG. 6 is a conceptual diagram illustrating a method for manufacturing a semiconductor device according to the present invention.

FIG. 7 is a conceptual diagram illustrating a method for manufacturing a semiconductor device of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Semiconductor device 11 Field oxide film 12 Semiconductor substrate 14 Oxide film on gate 16 Gate 18 Side wall 20 Source / drain region 22 Stopper layer 24 Interlayer insulating film 26 Metal film 28, 36 Resist mask 30 Contact hole 32 Gate oxide film 34 Embedded material 38 Wiring pattern

Claims (5)

[Claims] After the interlayer insulating film is planarized, a conductive film having a lower etching rate than the interlayer insulating film is deposited on the surface of the interlayer insulating film under the processing conditions of the connection hole, and the photolithography step is performed. Opening the connection hole in the conductive film, using the conductive film in which the connection hole is opened as a connection hole mask, opening a connection hole in the interlayer insulation film, and then opening the interlayer insulation film. A method for manufacturing a semiconductor device, comprising: burying a conductive material in a connection hole of a film, and forming a wiring layer electrically connected to the conductive material on the interlayer insulating film. 2. The method according to claim 1, wherein the formation of the wiring layer is performed by patterning a wiring pattern on the conductive film used as the connection hole mask. 3. The formation of the wiring layer includes, after opening the connection hole in the interlayer insulating film, removing the conductive film used as the connection hole mask to expose the surface of the interlayer insulating film. Later, a conductive material is buried in the connection hole of the interlayer insulating film, and thereafter, a new conductive film electrically connected to the conductive material in the connection hole is formed on the interlayer insulating film. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the method is performed by patterning a wiring pattern on the new conductive film. 4. The method of forming a wiring layer according to claim 1, wherein the step of filling the connection hole of the interlayer insulating film with a conductive material and removing the conductive film used as the connection hole mask removes the surface of the interlayer insulating film. Exposing, and thereafter, forming a new conductive film electrically connected to the conductive material in the connection hole on the interlayer insulating film, and patterning a wiring pattern on the new conductive film. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the method is performed by: 5. After the interlayer insulating film is flattened, a conductive film is deposited on the surface of the interlayer insulating film, and the conductive film and the interlayer insulating film are formed by any one of an electron beam, an ion beam, and a laser beam. Are continuously and directly opened in an etching atmosphere suitable for each film, and thereafter, a conductive substance is buried in the connection holes of the opened interlayer insulating film, and the conductive material is formed on the interlayer insulating film. A method for manufacturing a semiconductor device, comprising forming a wiring layer electrically connected to a substance.