JPH0714052B2 - Method for forming electrode of charge coupled device - Google Patents

Method for forming electrode of charge coupled device

Info

Publication number
JPH0714052B2
JPH0714052B2 JP26197886A JP26197886A JPH0714052B2 JP H0714052 B2 JPH0714052 B2 JP H0714052B2 JP 26197886 A JP26197886 A JP 26197886A JP 26197886 A JP26197886 A JP 26197886A JP H0714052 B2 JPH0714052 B2 JP H0714052B2
Authority
JP
Japan
Prior art keywords
polysilicon
polysilicon layer
electrode
coupled device
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP26197886A
Other languages
Japanese (ja)
Other versions
JPS63116466A (en
Inventor
雅利 田部井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujifilm Holdings Corp
Original Assignee
Fuji Photo Film Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Photo Film Co Ltd filed Critical Fuji Photo Film Co Ltd
Priority to JP26197886A priority Critical patent/JPH0714052B2/en
Publication of JPS63116466A publication Critical patent/JPS63116466A/en
Publication of JPH0714052B2 publication Critical patent/JPH0714052B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は電荷結合デバイス(CCD)の電極形成方法に関
し、更に詳述すれば、デバイスの高密度化によりパター
ン寸法が微小化された際に隣接電極間を好適に分離でき
る転送電極の形成方法に関する。
The present invention relates to a method for forming electrodes of a charge-coupled device (CCD), and more specifically, when the pattern size is miniaturized by increasing the device density. The present invention relates to a method of forming a transfer electrode that can preferably separate adjacent electrodes.

〔従来技術〕[Prior art]

一般にCCD転送電極は、例えば第2図に図示するとお
り、酸化したポリシリコンが重ね合わされた多層構造か
ら成つている。
Generally, the CCD transfer electrode has a multi-layer structure in which oxidized polysilicon is superposed as shown in FIG. 2, for example.

このような多層構造の転送電極の製作において、例えば
リソグラフイ工程で使用するマスク・パターンの位置合
わせがずれると、1電極の1方の端部が隣接電極と離れ
て所謂目はずれ構造を生じる。従つて、従来デバイスは
マスクの重なり部分に合わせ余裕を設け、電極間に例え
ば1μm程度の重なりを有している。
In the production of such a transfer electrode having a multilayer structure, for example, if the alignment of the mask pattern used in the lithographic process is misaligned, one end of one electrode is separated from the adjacent electrode, resulting in a so-called misaligned structure. Therefore, in the conventional device, a margin is provided in the overlapping portion of the mask, and the electrodes have an overlap of, for example, about 1 μm.

しかし、このような重なりを有していたのでは、パター
ン寸法を微小化してデバイスの高密度化を達成すること
は困難であつた。
However, with such an overlap, it has been difficult to miniaturize the pattern size to achieve high density of devices.

高密度化に対応できるものとして、第3図に図示するよ
うな最終的に単層ポリシリコンから成る電極構造が考え
られた。このような電極構造では、従来の合わせ構造の
電極と同等の効果を有するために、隣接電極間が0.2μ
m〜0.5μm程度の微小間隔で分離されなければならな
い。
An electrode structure finally made of single-layer polysilicon as shown in FIG. 3 has been considered as one that can cope with high density. Such an electrode structure has the same effect as an electrode with a conventional mating structure, so that the distance between adjacent electrodes is 0.2μ.
They must be separated at minute intervals of about m to 0.5 μm.

また、電極製作の最終工程において、ポリシリコンのエ
ツチングにより上記微小間隔に分離された電極相互間は
酸化膜が設けられて絶縁される。
Further, in the final step of manufacturing the electrodes, an oxide film is provided between the electrodes separated by the etching of the polysilicon into the minute intervals to insulate the electrodes.

〔発明が解決しようとする問題点〕[Problems to be solved by the invention]

しかしながら、PSG(Phospho−Silicate Glass)酸化膜
を上記微小間隔に埋め込む事は難しく、空気の封入を生
じたり、またポリシリコンの微小間隔が機械強度や熱ひ
ずみ等に弱いと云う欠陥を有した。そのため、最終段で
形成するパツシベーシヨン膜に問題を生じ、クラツク等
の発生原因となつた。
However, it is difficult to embed a PSG (Phospho-Silicate Glass) oxide film in the above-mentioned minute interval, and air encapsulation occurs, and the minute interval of polysilicon has a defect that mechanical strength and thermal strain are weak. Therefore, a problem occurs in the passivation film formed in the final stage, which causes cracks and the like.

本発明の目的は、上記事情に基づいて行われたもので、
単層ポリシリコン構造の転送電極を微小間隔で形成し、
かつ前記間隔が好適に絶縁できる電荷結合デバイスの電
極形成方法を提供することにある。
The object of the present invention was made based on the above circumstances,
Transfer electrodes having a single-layer polysilicon structure are formed at minute intervals,
Another object of the present invention is to provide a method for forming an electrode of a charge-coupled device in which the distance can be suitably insulated.

〔問題点を解決するための手段〕[Means for solving problems]

すなわち、本発明の上記目的は、電荷転送方向と交差す
る方向に沿つて単層ポリシリコン層からなる電極が複数
本配置される電荷結合デバイスの電極形成方法におい
て、半導体基板上にゲート酸化膜及びポリシリコン層を
順次形成し、前記ポリシリコン層を所定間隔にパターニ
ンダして残つたポリシリコン層表面にポリ酸化膜を所定
厚に成長後、全域にフオトレジストを塗布して少なくと
もポリシリコン層表面が露出する迄平坦化エツチングを
行い、フオトレジスト及びポリシリコン層を除去した
後、全域にポリシリコンをデポジシヨンし、ドーピング
後、酸化を行い、ポリシリコン間の絶縁が完成すること
を特徴とする電荷結合デバイスの電極形成方法により達
成される。
That is, the above object of the present invention is to provide a gate oxide film and a gate oxide film on a semiconductor substrate in an electrode forming method of a charge-coupled device in which a plurality of electrodes made of a single-layer polysilicon layer are arranged along a direction intersecting a charge transfer direction. A polysilicon layer is sequentially formed, and a polysilicon oxide film is grown to a predetermined thickness on the surface of the remaining polysilicon layer after patterning the polysilicon layer at a predetermined interval, and then a photoresist is applied to the entire area to cover at least the polysilicon layer surface. Charge coupling is characterized by performing planarization etching until it is exposed, removing the photoresist and the polysilicon layer, depositing polysilicon on the entire area, and performing oxidation after doping to complete insulation between polysilicons. This is achieved by the method of forming electrodes of the device.

〔実施例〕〔Example〕

以下、図面により本発明による電極形成方法の実施例を
詳細に説明する。
Hereinafter, embodiments of the electrode forming method according to the present invention will be described in detail with reference to the drawings.

第1図に示す1実施例は、(a)において、P形シリコン
結晶基板10の表面に形成された図示しないN形チヤンネ
ル不純物層の上に、ゲート酸化膜(SiO2膜)1を挾んで
ポリシリコン2がデポジンヨンされている。前記ゲート
酸化膜1は熱酸化により250Å厚に形成される。また、
前記ポリシリコン2はリンが添加されて導電性を有し、
2000Å厚でCVDにより形成される。(b)において、前記ポ
リシリコン2は所定間隔、例えば1セルが3μm幅とな
るようにし、かつ電荷転送方向(図中、矢印で示す方
向)と交差する方向に沿つて複数本配列されるようにパ
ターニングされる。このパターニングは通常のリソグラ
フイによつて行われており、ここでの説明は省略する。
(c)において、前記ポリシリコン2の表面に、熱酸化法
によつてポリ酸化膜3を所定の膜厚に成長させる。この
膜厚は0.2μm〜0.5μmに形成されており、ポリ酸化膜
3の壁部は後述する分離された電極間の絶縁層になる。
(d)において、全域に低粘度レジスト4を塗布して段差
を埋めた後、反応性イオンエツチング(RIE)にて平坦
化エツチングを行う。この際、平坦化エツチングは、少
なくともポリシリコン2上のひさし部に相当するポリ酸
化膜3と共に、ポリシリコン2の1部が除去されるまで
行う。(e)において、前記低粘度レジスト4を剥離し、
更にポリシリコン2もエツチングして前記ポリ酸化膜3
だけの垂直壁を形成する。(f)において、全域にポリシ
リコン5を再度デポジシヨンし、ドーピング後(g)にお
いて、ポリシリコン5表面にポリ酸化膜3aを成長させ
る。この時、図(f)のポリSiの上部を点線で示した線ま
で、酸化し、隣接するポリSi電極の絶縁を完成しても良
いし、酸化工程の前に平坦化エツチングを行う。
In one embodiment shown in FIG. 1, in (a), a gate oxide film (SiO 2 film) 1 is sandwiched on an N-type channel impurity layer (not shown) formed on the surface of a P-type silicon crystal substrate 10. Polysilicon 2 is deposited. The gate oxide film 1 is formed to a thickness of 250 Å by thermal oxidation. Also,
The polysilicon 2 has conductivity by adding phosphorus,
Formed by CVD with a thickness of 2000Å. In (b), the polysilicon 2 is arranged at a predetermined interval, for example, one cell has a width of 3 μm, and a plurality of polysilicon 2 are arranged along a direction intersecting the charge transfer direction (direction indicated by an arrow in the figure). To be patterned. This patterning is performed by the usual lithography, and the description here is omitted.
In (c), a polyoxide film 3 is grown on the surface of the polysilicon 2 by a thermal oxidation method to a predetermined thickness. The film thickness is 0.2 μm to 0.5 μm, and the wall portion of the polyoxide film 3 serves as an insulating layer between separated electrodes, which will be described later.
In (d), a low-viscosity resist 4 is applied to the entire area to fill the steps, and then planarization etching is performed by reactive ion etching (RIE). At this time, the planarization etching is performed until at least a part of the polysilicon 2 is removed together with the polyoxide film 3 corresponding to the eaves part on the polysilicon 2. In (e), the low viscosity resist 4 is peeled off,
Further, the polysilicon 2 is also etched to remove the poly oxide film 3
Only form a vertical wall. In (f), the polysilicon 5 is again deposited over the entire area, and after doping (g), the polyoxide film 3a is grown on the surface of the polysilicon 5. At this time, the upper portion of the poly-Si in FIG. 6 (f) may be oxidized up to the line shown by the dotted line to complete the insulation of the adjacent poly-Si electrode, or planarization etching may be performed before the oxidation step.

この平坦化エツチングは少なくとも前記ポリ酸化膜3の
垂直壁頂部が露出されるまで行う。
This planarization etching is performed at least until the top of the vertical wall of the polyoxide film 3 is exposed.

〔発明の効果〕〔The invention's effect〕

以上記載したとおり、本発明の方法によれば、ポリシリ
コンが1層で、微小間隔のポリ酸化膜で分離された電荷
結合デバイスを製作できる。また、最終工程に於て、ポ
リシリコン及びポリ酸化膜表面が平坦に設けられている
ため、パツシベーシヨン膜を形成する場合、クラツク等
のトラブルを生じない。なお、本発明ではポリ酸化膜だ
けで電極間が分離される。
As described above, according to the method of the present invention, it is possible to fabricate a charge-coupled device in which polysilicon is a single layer and is separated by minutely spaced poly oxide films. Further, in the final step, since the surfaces of the polysilicon and the polyoxide film are provided flat, troubles such as cracks do not occur when the passivation film is formed. In the present invention, the electrodes are separated only by the polyoxide film.

【図面の簡単な説明】[Brief description of drawings]

第1図は、本発明の1実施例を説明するプロセス図、第
2図は、従来の積層ポリシリコン構造のCCD転送電極を
説明する断面図、第3図は、単層ポリシリコン構造を説
明する図である。 1……ゲート酸化膜、2,5……ポリシリコン、3,3a……
ポリ酸化膜、4……低粘度レジスト、10……P形シリコ
ン結晶基板
FIG. 1 is a process diagram for explaining one embodiment of the present invention, FIG. 2 is a sectional view for explaining a CCD transfer electrode having a conventional laminated polysilicon structure, and FIG. 3 is for explaining a single-layer polysilicon structure. FIG. 1 ... Gate oxide film, 2,5 ... Polysilicon, 3,3a ...
Poly oxide film, 4 ... Low viscosity resist, 10 ... P type silicon crystal substrate

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】電荷転送方向と交差する方向に沿って単層
ポリシリコン層からなる電極が複数本配置される電荷結
合デバイスの電極形成方法において、半導体基板上にゲ
ート酸化膜及びポリシリコン層を順次形成し、前記ポリ
シリコン層を所定間隔にパターニンダして残ったポリシ
リコン層表面及び側壁にポリ酸化膜を所定厚に成長後、
全域にフォトレジストを塗布して少なくともポリシリコ
ン層表面が露出する迄平坦化エッチングを行い、フォト
レジスト及びポリシリコン層を除去した後、全域にポリ
シリコンを再度デポジションし、ドーピング工程後酸化
工程によりポリシリコンの絶縁分離が完成するまで酸化
を行うことを特徴とする電荷結合デバイスの電極形成方
法。
1. A method for forming an electrode of a charge-coupled device, wherein a plurality of electrodes made of a single-layer polysilicon layer are arranged along a direction intersecting a charge transfer direction, wherein a gate oxide film and a polysilicon layer are formed on a semiconductor substrate. Sequentially formed, after patterning the polysilicon layer at a predetermined interval, a poly oxide film is grown to a predetermined thickness on the remaining polysilicon layer surface and sidewalls,
After applying photoresist to the entire area and performing planarization etching until at least the surface of the polysilicon layer is exposed, the photoresist and the polysilicon layer are removed, and then polysilicon is again deposited on the entire area. A method for forming an electrode of a charge-coupled device, which comprises performing oxidation until polysilicon insulation isolation is completed.
JP26197886A 1986-11-05 1986-11-05 Method for forming electrode of charge coupled device Expired - Lifetime JPH0714052B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26197886A JPH0714052B2 (en) 1986-11-05 1986-11-05 Method for forming electrode of charge coupled device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26197886A JPH0714052B2 (en) 1986-11-05 1986-11-05 Method for forming electrode of charge coupled device

Publications (2)

Publication Number Publication Date
JPS63116466A JPS63116466A (en) 1988-05-20
JPH0714052B2 true JPH0714052B2 (en) 1995-02-15

Family

ID=17369301

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26197886A Expired - Lifetime JPH0714052B2 (en) 1986-11-05 1986-11-05 Method for forming electrode of charge coupled device

Country Status (1)

Country Link
JP (1) JPH0714052B2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR940009601B1 (en) * 1991-09-14 1994-10-15 금성일렉트론 주식회사 Manufacturing method of charge coupled device
US5516716A (en) * 1994-12-02 1996-05-14 Eastman Kodak Company Method of making a charge coupled device with edge aligned implants and electrodes
JP2009196803A (en) 2008-02-25 2009-09-03 Konica Minolta Business Technologies Inc Paper conveying device

Also Published As

Publication number Publication date
JPS63116466A (en) 1988-05-20

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