JPS6153868B2 - - Google Patents
Info
- Publication number
- JPS6153868B2 JPS6153868B2 JP5413883A JP5413883A JPS6153868B2 JP S6153868 B2 JPS6153868 B2 JP S6153868B2 JP 5413883 A JP5413883 A JP 5413883A JP 5413883 A JP5413883 A JP 5413883A JP S6153868 B2 JPS6153868 B2 JP S6153868B2
- Authority
- JP
- Japan
- Prior art keywords
- conductivity type
- type region
- opposite conductivity
- region
- gate electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000000758 substrate Substances 0.000 claims description 9
- 239000004065 semiconductor Substances 0.000 claims description 8
- 239000012535 impurity Substances 0.000 claims description 5
- 230000005669 field effect Effects 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 24
- 235000012239 silicon dioxide Nutrition 0.000 description 12
- 239000000377 silicon dioxide Substances 0.000 description 12
- 238000005530 etching Methods 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229960000583 acetic acid Drugs 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- -1 boron ions Chemical class 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 239000012362 glacial acetic acid Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
Description
【発明の詳細な説明】
この発明は絶縁ゲート型電界効果半導体装置に
係り、とくに短チヤンネル化に好適な絶縁ゲート
型電界効果トランジスタに係るものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an insulated gate field effect semiconductor device, and particularly to an insulated gate field effect transistor suitable for shortening channels.
絶縁ゲート型電界効果トランジスタ（以下MIS
トランジスタという）を用いた半導体デバイスの
動作特性を向上するため、MISトランジスタのチ
ヤンネル長を短縮することが試みられている。し
かし乍らMISトランジスタのチヤンネル長の２μ
ｍ以下への短縮は、ゲート閾値がドレイン電圧に
依存するようになり、パンチスルーによるドレイ
ン耐圧の低下をも引き起すため動作が不安定とな
る。これを防ぐ試みはトランジスタのドレインお
よびソース領域の有効濃度を低下し、ソース領域
内部での帰還作用でドレイン電圧に依存するゲー
ト閾値の低下を防止することであるが、有効濃度
の低いソース領域をゲート電極直下のチヤンネル
領域から長く伸ばすことは、ソース抵抗を増大し
利得を過少にすることになる。 Insulated gate field effect transistor (MIS)
In order to improve the operating characteristics of semiconductor devices using MIS transistors, attempts have been made to shorten the channel length of MIS transistors. However, the channel length of the MIS transistor is 2μ.
If the voltage is reduced to less than m, the gate threshold value becomes dependent on the drain voltage, which also causes a decrease in drain breakdown voltage due to punch-through, resulting in unstable operation. An attempt to prevent this is to lower the effective concentration of the drain and source regions of the transistor, and prevent the gate threshold from decreasing depending on the drain voltage due to the feedback effect inside the source region. Extending the channel region long from the channel region immediately below the gate electrode increases the source resistance and reduces the gain.
この発明の目的は、短チヤンネル効果が少なく
且つ電気的特性の優れたMISトランジスタを提供
することにある。 An object of the present invention is to provide a MIS transistor with less short channel effect and excellent electrical characteristics.
本発明は、一導電型の半導体基板の一主表面に
設けられた第１の逆導電型領域と、該第１の逆導
電型領域から離れた前記一主表面に設けられた絶
縁ゲート構造と、該絶縁ゲート構造と前記第１の
逆導電型領域間の前記一主表面に導入された前記
第１の逆導電型領域より低不純物濃度の第２の逆
導電型領域と、該第２の逆導電型領域よりも深く
前記第１の逆導電型領域より浅く設けられ、かつ
前記第２の逆導電型領域よりもチヤンネル側に突
出するように設けられた前記半導体基板よりも不
純物濃度の高い一導電型領域とを有することを特
徴とするものである。 The present invention includes a first opposite conductivity type region provided on one main surface of a semiconductor substrate of one conductivity type, and an insulated gate structure provided on the first opposite conductivity type region away from the first opposite conductivity type region. , a second opposite conductivity type region having a lower impurity concentration than the first opposite conductivity type region introduced into the one main surface between the insulated gate structure and the first opposite conductivity type region; The semiconductor substrate has an impurity concentration higher than that of the semiconductor substrate, which is deeper than the opposite conductivity type region and shallower than the first opposite conductivity type region, and is provided so as to protrude toward the channel side than the second opposite conductivity type region. It is characterized by having a region of one conductivity type.
この発明によれば、一導電型領域と逆導電型領
域との間の接合容量が小さくなるので動作速度が
早くなり、短チヤンネルのMISトランジスタに適
用して電気的特性の再現性が著しく増大する。 According to this invention, since the junction capacitance between the one conductivity type region and the opposite conductivity type region is reduced, the operation speed is increased, and the reproducibility of electrical characteristics is significantly increased when applied to short channel MIS transistors. .
次にこの発明に特徴をより良く理解するため
に、この発明の実施例につき図を用いて説明す
る。 Next, in order to better understand the features of this invention, embodiments of this invention will be described using figures.
第１図Ａ〜第１図Ｅはこの発明の好ましい実施
例の主たる製造工程での断面図である。 FIGS. 1A to 1E are cross-sectional views of a preferred embodiment of the present invention at the main manufacturing steps.
第１図Ａ：比抵抗20Ω−cmのＰ型シリコン単結晶
基体１０１の一表面に特公昭50−1379号公報に
示されるようにシリコン窒化膜を用いて選択酸
化を施し、不活性領域に表面濃度1016〜1017cm
-3の高濃度Ｐ型領域１０２と1.0〜1.3μｍの厚
い二酸化硅素膜１０３を設ける。活性領域には
500Åの二酸化硅素のゲート絶縁膜１０４を熱
酸化成長し、この中央附近に巾2.5μｍの多結
晶シリコンのゲート電極１０５と多結晶シリコ
ンの選択蝕刻マスクとして用いた二酸化硅素膜
１０６を設ける。FIG. 1A: Selective oxidation is performed on one surface of a P-type silicon single crystal substrate 101 with a specific resistance of 20 Ω-cm using a silicon nitride film as shown in Japanese Patent Publication No. 1379/1983, and the surface is covered with an inactive region. Concentration 10 16 ~ 10 17 cm
-3 high concentration P type region 102 and 1.0 to 1.3 μm thick silicon dioxide film 103 are provided. In the active area
A gate insulating film 104 of silicon dioxide with a thickness of 500 Å is grown by thermal oxidation, and a gate electrode 105 of polycrystalline silicon with a width of 2.5 μm and a silicon dioxide film 106 used as a selective etching mask for the polycrystalline silicon are provided near the center thereof.
第１図Ｂ：ゲート電極１０５および二酸化硅素１
０６をマスクとして燐を活性領域に導入し、濃
度1020〜1021cm-3で接合深さ1.5μｍの高濃度の
Ｎ型領域１０７，１０８を形成する。Figure 1B: Gate electrode 105 and silicon dioxide 1
Using 06 as a mask, phosphorus is introduced into the active region to form highly concentrated N-type regions 107 and 108 with a concentration of 10 20 to 10 21 cm -3 and a junction depth of 1.5 μm.
第１図Ｃ：ゲート電極１０５は再び二酸化硅素膜
１０６をマスクとして化学蝕刻液で側面蝕刻す
る。多結晶シリコンの側面蝕刻には氷酢酸と硝
酸と弗酸とを40：４：１の体積比で混液とした
蝕刻液が好適で約２分間で0.5μｍの側面蝕刻
を得る。FIG. 1C: The sides of the gate electrode 105 are etched again using a chemical etching solution using the silicon dioxide film 106 as a mask. For side surface etching of polycrystalline silicon, an etching solution containing a mixture of glacial acetic acid, nitric acid, and hydrofluoric acid in a volume ratio of 40:4:1 is suitable, and a side surface of 0.5 μm can be etched in about 2 minutes.
第１図Ｄ：側面蝕刻によりゲート電極１０５′の
巾を1.5μｍににせばめたのち、ゲート電極１
０５′の上面の二酸化硅素膜１０６を除去しフ
オトレジスト膜２０１を被着する。フオトレジ
スト膜２０１はゲート電極１０５′とソース領
域として動作するＮ型領域１０７の上面に端が
到る開孔２０２を有し、この開孔を通してゲー
ト電極１０５′をマスクとしてボロンをイオン
注入して高濃度のＰ型領域２０３を形成する。
イオン注入条件は50KeVで注入量1011〜1012cm
-2が好適である。Figure 1D: After narrowing the width of the gate electrode 105' to 1.5 μm by side etching, the gate electrode 1
The silicon dioxide film 106 on the upper surface of 05' is removed and a photoresist film 201 is deposited. The photoresist film 201 has an opening 202 whose end reaches the upper surface of the gate electrode 105' and the N-type region 107 which acts as a source region, and boron ions are implanted through this opening using the gate electrode 105' as a mask. A heavily doped P-type region 203 is formed.
The ion implantation conditions were 50KeV and the implantation amount was 10 11 to 10 12 cm.
-2 is preferred.
第１図Ｅ：イオン注入後にフオトレジスト膜２０
１を除去し、1000℃の水素雰囲中で熱処理して
Ｐ型領域２０３の有効深さを１μｍ程度まで拡
大する。しかるのち、ゲート電極１０５′をマ
スクとしてＮ型領域１０７，１０８とゲート電
極１０５′との間の基体表面に燐を導入し濃度
約1015cm-3、接合深さ0.1μｍの低濃度Ｎ型領域
１０７′，１０８′を形成し、熱酸化によりＮ型
領域１０７，１０８，１０７′，１０８′および
ゲート電極１０５′の上面に二酸化硅素膜１０
９を成長する。ここでゲート電極１０５′は高
濃度のＮ型領域１０７，１０８および低濃度の
Ｎ型領域１０７′，１０８′にそれぞれ自己整合
し、ゲート電極１０５′の巾1.5μｍの直下に約
1.3μｍの実効チヤンネル長のMISトランジス
タのゲート電極として動作する。次に活性領域
の両端の高濃度のＮ型領域１０７，１０８およ
びゲート電極１０５′の上面を覆う二酸化硅素
膜１０９にそれぞれ開孔を選択蝕刻し、この開
孔を通して厚い二酸化硅素膜１０３の上面に伸
びるアルミニウムの配線電極１１０，１１１，
１１２を形成する。Figure 1 E: Photoresist film 20 after ion implantation
1 is removed and heat treated in a hydrogen atmosphere at 1000° C. to expand the effective depth of the P-type region 203 to about 1 μm. Thereafter, using the gate electrode 105' as a mask, phosphorus is introduced into the substrate surface between the N-type regions 107, 108 and the gate electrode 105' to form a low concentration N-type with a concentration of about 10 15 cm -3 and a junction depth of 0.1 μm. A silicon dioxide film 10 is formed on the upper surface of the N-type regions 107, 108, 107', 108' and the gate electrode 105' by thermal oxidation.
Grow 9. Here, the gate electrode 105' is self-aligned with the highly doped N-type regions 107, 108 and the lightly doped N-type regions 107', 108', respectively, and is approximately located directly under the 1.5 μm width of the gate electrode 105'.
It acts as the gate electrode of a MIS transistor with an effective channel length of 1.3 μm. Next, holes are selectively etched in the silicon dioxide film 109 covering the high concentration N-type regions 107 and 108 at both ends of the active region and the upper surface of the gate electrode 105', and the upper surface of the thick silicon dioxide film 103 is formed through these holes. Extending aluminum wiring electrodes 110, 111,
112 is formed.
上述の実施例は従来のシリコンゲート型MISト
ランジスタとほぼ同一の写真蝕刻工程で得られ、
工程を若干変更するのみで電気的特性を改善する
ことができる。即ち低濃度のＮ型領域１０７′，
１０８′はゲート電極１０５′の側面蝕刻で得られ
るため小間隔で得られソース抵抗の増大もなくパ
ンチスルー電圧の低下の防止とゲート閾値電圧の
安定性が得られる。 The above-mentioned embodiments are obtained using almost the same photolithography process as conventional silicon gate MIS transistors.
Electrical characteristics can be improved by only slightly changing the process. That is, the low concentration N-type region 107',
108' can be obtained by etching the side surfaces of the gate electrode 105', so that they can be obtained at small intervals, and there is no increase in source resistance, preventing a drop in punch-through voltage and stabilizing the gate threshold voltage.
さらに、本実施例の構造は低濃度のＮ型領域と
有効深さ、すなわち基板と実質的に同じ不純物濃
度となる深さが高濃度のＮ型領域の接合深さより
浅いＰ型領域とで得られるため、接合容量が小と
なり動作速度を早め、且つ電気的特性の再現性が
著じるしく増大する。これらの効果はドレイン側
をも同様な構造とした場合には更に顕著である。 Furthermore, the structure of this example has a low concentration N-type region and a P-type region whose effective depth, that is, the depth at which the impurity concentration is substantially the same as that of the substrate, is shallower than the junction depth of the high concentration N-type region. Therefore, the junction capacitance is reduced, the operating speed is increased, and the reproducibility of the electrical characteristics is significantly increased. These effects are even more remarkable when the drain side is also provided with a similar structure.
以上にこの発明について説明したが、ゲート電
極に用いる多結晶シリコンには高融点のモリブデ
ン、タングステン等の金属電極をも用い得る。
又、材料、導電型等は必要に応じて容易に変更で
きる。 Although the present invention has been described above, metal electrodes such as molybdenum, tungsten, etc. having a high melting point may also be used for the polycrystalline silicon used for the gate electrode.
Further, the material, conductivity type, etc. can be easily changed as necessary.
第１図Ａ乃至第１図Ｅは各々この発明の一実施
例を製造工程順に示す断面図である。
なお図において、１０１……Ｐ型シリコン単結
晶基体、１０２……不活性領域へのＰ型領域、１
０３……厚い二酸化硅素膜、１０４……ゲート絶
縁膜、１０５，１０５′……ゲート電極、１０６
……二酸化硅素膜、１０７，１０８……高濃度の
Ｎ型領域、１０７′，１０８′……低濃度のＮ型領
域、１０９……二酸化硅素膜、２０１……フオト
レジスト膜、２０２……開孔、２０３……高濃度
のＰ型領域、１１０，１１１，１１２……配線電
極、である。
FIGS. 1A to 1E are cross-sectional views showing one embodiment of the present invention in the order of manufacturing steps. In the figure, 101...P-type silicon single crystal substrate, 102...P-type region to inactive region, 1
03... Thick silicon dioxide film, 104... Gate insulating film, 105, 105'... Gate electrode, 106
...Silicon dioxide film, 107,108...High concentration N-type region, 107', 108'...Low concentration N-type region, 109...Silicon dioxide film, 201...Photoresist film, 202...Open Holes, 203...High concentration P-type regions, 110, 111, 112... Wiring electrodes.
Claims (1)
た第１の逆導電型領域と、該第１の逆導電型領域
から離れた前記一主表面に設けられた絶縁ゲート
構造と、該絶縁ゲート構造と前記第１の逆導電型
領域間の前記一主表面に導入された前記第１の逆
導電型領域より低不純物濃度の第２の逆導電型領
域と、該第２の逆導電型領域よりも深く前記第１
の逆導電型領域より浅く設けられ、かつ前記第２
の逆導電型領域よりもチヤンネル側に突出するよ
うに設けられた前記半導体基板よりも不純物濃度
の高い一導電型領域とを有することを特徴とする
絶縁ゲート型電界効果半導体装置。1. A first opposite conductivity type region provided on one main surface of a semiconductor substrate of one conductivity type, an insulated gate structure provided on the one main surface remote from the first opposite conductivity type region, and the insulating a second opposite conductivity type region having a lower impurity concentration than the first opposite conductivity type region introduced into the one main surface between the gate structure and the first opposite conductivity type region; and the second opposite conductivity type region. deeper than the first region
is provided shallower than the opposite conductivity type region, and the second
An insulated gate field effect semiconductor device comprising a one conductivity type region having a higher impurity concentration than the semiconductor substrate and which is provided so as to protrude toward the channel side than the opposite conductivity type region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5413883A JPS58194367A (en) | 1983-03-30 | 1983-03-30 | Insulated gate field effect semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5413883A JPS58194367A (en) | 1983-03-30 | 1983-03-30 | Insulated gate field effect semiconductor device |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3549976A Division JPS52117586A (en) | 1976-03-30 | 1976-03-30 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58194367A JPS58194367A (en) | 1983-11-12 |
| JPS6153868B2 true JPS6153868B2 (en) | 1986-11-19 |
Family
ID=12962209
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5413883A Granted JPS58194367A (en) | 1983-03-30 | 1983-03-30 | Insulated gate field effect semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58194367A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01164677U (en) * | 1988-05-09 | 1989-11-16 |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3221766B2 (en) * | 1993-04-23 | 2001-10-22 | 三菱電機株式会社 | Method for manufacturing field effect transistor |
| US5650340A (en) * | 1994-08-18 | 1997-07-22 | Sun Microsystems, Inc. | Method of making asymmetric low power MOS devices |
| KR960026960A (en) * | 1994-12-16 | 1996-07-22 | 리 패치 | Asymmetric Low Power Morse Device |
-
1983
- 1983-03-30 JP JP5413883A patent/JPS58194367A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01164677U (en) * | 1988-05-09 | 1989-11-16 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58194367A (en) | 1983-11-12 |
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