JPS58194367A - Insulated gate field effect semiconductor device - Google Patents

Abstract

PURPOSE:To obtain the MIS transistor having a small short channel effect, and moreover having the superiorly electric characteristic by a method wherein junction capacitance is reduced by constituting junctions with low concentration N type regions and P type regions having effectual depth shallower than the junction depth of high concentration N type regions. CONSTITUTION:The semiconductor device is constructed having the first reversely conductive type regions 107, 108 of high concentration provided on one main surface of a single conductive type semiconductor substrate 101, the insulated gate 104 provided on the main surface separated from the reversely conductive type regions thereof, the second reversely conductive type regions 107', 108' introduced on the main surface between the insulated gate 104 thereof and the first reversely conductive regions 107, 108, and having concentration lower than the first reversely conductive type regions, and the single conductive type region 203 provided under the second reversely conductive type regions 107', 108' shallower than depth of the first reversely conductive type regions from the main surface and having concentration higher than the substrate. According to this construction, junction capacitances between the single conductive region 203 and the reversely conductive type regions are reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an insulated gate field effect conductor device, and more particularly to an insulated gate field effect transistor suitable for short channel formation.

In order to improve the operating characteristics of dead conductor devices using insulated gate field effect transistors (hereinafter referred to as MIS transistors), attempts have been made to shorten the channel length of MID transistors.

However, the channel length of the MIS transistor is 2 μm.
Shortening to below becomes dependent on the gate threshold value 7 and the drain voltage, and also causes a decrease in the drain withstand voltage due to punch-through, resulting in unstable operation. Attempts to prevent this are to lower the effective concentration of the drain and source regions of the transistor, and to prevent the gate threshold from decreasing depending on the drain voltage due to the feedback effect inside the source region.
Extending the source region with a low effective concentration from the channel region directly under the gate electrode increases the source resistance and reduces the gain.

An object of the present invention is to provide an MI8) transistor with less short channel effect and excellent electrical characteristics.

The features of this invention are: - a highly concentrated first opposite conductivity type region provided on the surface of the conductivity type semiconductor substrate; an insulated gate structure provided on the surface remote from this opposite conductivity type region; A second opposite conductivity type region introduced into the main surface between the insulated gate structure and the first opposite conductivity type region and having a lower temperature than the first opposite conductivity type region, and a first opposite conductivity type region below the second opposite conductivity type region. A semiconductor device has a region of one conductivity type with a higher concentration than the substrate, which is shallower than the depth from the surface of the region of the opposite conductivity type.

According to this invention, the junction capacitance between the conductivity type region and the opposite conductivity type region is reduced, so the operation speed is increased, and the reproducibility of electrical characteristics is significantly increased when applied to short channel MIS transistors. .

Next, in order to better understand the characteristics of the present invention, embodiments of the present invention will be described using figures.

Figures 1 to 1 are cross-sectional views of the main manufacturing process of a preferred embodiment of the present invention.

Figure 1-1: Selective oxidation is performed on one surface of a P-type silicon single crystal substrate 101 with a specific resistance of 20 Ω-1 using a silicon nitride film as shown in Japanese Patent Publication No. 50-1379, and the surface is covered with an inactive region. Concentration 101・~IQ1) CI! A high-concentration P-type region 102 of "L-" and a thick silicon dioxide film 103 of 1.0 to 1.3 μm are provided. A gate insulating film 104 of silicon dioxide of 500 μm is grown by thermal oxidation in the active region, and A polycrystalline silicon gate electrode 105 with a width of 2.5 μm
A silicon dioxide film 106 used as a selective etching mask for polycrystalline silicon is provided.

FIG. 1(B): Gate electrode 105 and silicon dioxide film 1
fF4 was introduced into the active region using 06 as a mask, and the concentration was 1.
0m (1 to 1011crIL-1 bonding depth 1.5μ
m (D?% m [f) Form N-type regions 107 and 108.

FIG. 1 (q: The gate electrode 105 is again made of silicon dioxide film 10.
6 is used as a mask and the sides are etched with a chemical etching solution. For the side surface of polycrystalline silicon, mix 40:4 of glacial acetic acid, nitric acid, and hydrofluoric acid.
An etching solution mixed in a volume ratio of 1:1 is suitable, and the etching solution becomes 0 in about 2 minutes.
．． A side engraving of 5 μm is obtained.

Figure 1 Plow: The width of the gate electrode 105' is reduced by 1 by side etching.
．． After narrowing to 5 μm,
The silicon dioxide film 106 on the top surface of the "
1 acts as the gate electrode 105' and the source region.
It has an opening 2'o2 whose end reaches the upper surface of the mold region 107,
Boron ions are implanted through this opening using the gate electrode 105' as a mask to form a highly modified P-type region 203. The ion implantation conditions were 50KeV and 101L, 1
0”cIL-a is preferred.

FIG. 1 (Uniform: After ion implantation, the photoresist film 201 is removed and heat treated in a hydrogen atmosphere at 1000°0 to enlarge the effective depth of the P-type region 203 to about 1 μm.

Thereafter, using the gate electrode 105' as a mask, phosphorus is introduced into the substrate surface between the N-type regions 107, 108 and the gate electrode 105' to a depth of approximately IQ1 m-'' and a junction depth of 0.1.
Low concentration N-type regions 107', 108' with a thickness of μm are formed, and N-type regions 107, 108, 107', 10
A silicon dioxide film 109 is grown on the upper surfaces of 8' and gate electrode 105'. Here, the gate electrode 105' includes highly doped N-type regions 107, 108 and lightly doped N-type regions 10.
7'.

108', and operate as a gate electrode of a MIS transistor having an effective channel length of about 1.3 μm directly under the gate electrode ios' having a width of 1.5 μm. Next, a silicon dioxide film 1 is formed covering the highly doped N-type regions 107 and 108 at both ends of the active region and the -F plane of the gate electrode 105'.
09 are selectively etched, and aluminum electrodes 110, 111, and 112 are formed extending through the entire openings to the upper surface of the thick silicon dioxide film 103.

The above embodiment uses a conventional silicon gate MIS transistor and #1#'! Photograph of l'1 town - obtained by engraving process,
Electrical characteristics can be improved by only slightly changing the process. That is, since the low concentration N-type regions 107' and 108' are obtained by etching the side surfaces of the gate electrode 105', they can be obtained at small intervals, and there is no increase in source resistance, prevention of decrease in punch-through voltage, and stability of gate threshold voltage. can get.

Furthermore, the structure of this embodiment has a low-reflection N-type region and a P-type region whose effective depth, that is, the depth at which the impurity level is substantially the same as that of the substrate, is shallower than the junction depth of the high-concentration N-type region. As a result, the junction capacitance is reduced, the operating speed is increased, and the reproducibility of electrical characteristics is significantly increased. These effects are even more remarkable when the drain side is also provided with a similar structure.

Although this invention has been explained above, it can be used for gate electrodes.
Polycrystalline silicon contains high-grade gold such as molybdenum and tungsten! Four electrodes may also be used. Further, the material, conductivity type, etc. can be easily changed as necessary.

[Brief explanation of drawings]

Figures 11 to t41 (Each is a sectional view showing an embodiment of the present invention in the manufacturing process I1g. In the figures, 101...P-type silicon content crystal substrate, 102... ... P-type region to inactive region,
103... Thick silicon dioxide film, 104...
...Gate loquat membrane. 105.105'...Gate electrode, 106...
...Silicon dioxide film, 107,108...High concentration N-type region, 107'. 108'...Low concentration N-type region, 109...
...Silicon dioxide film, 201...Photoresist g, zoz...Opening, 203...High concentration P-type region, 110,111°112... ...
It is a wiring electrode. Fig. (A) (β) (C)

Claims (1)

[Claims] a ninth opposite conductivity type region provided on one main surface of a semiconductor substrate of one conductivity type;
an insulated gate structure provided on the main surface; a second region with a low impurity concentration; a region of opposite conductivity type; and a region of one conductivity type provided below the second region of opposite conductivity at a depth shallower than the depth from the main surface of the first reverse conductivity type region and having an impurity concentration higher than that of the semiconductor substrate. An insulated gate field effect semiconductor device comprising: