JPS6158986B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing an insulated gate field effect transistor.

In recent years, in integrated circuit devices using insulated gate field effect transistors (hereinafter abbreviated as MOS transistors), so-called short channel MOS transistors, which have a short effective channel length between the source and drain, have attracted attention in order to improve the electrical characteristics. There is. A short channel MOS transistor has the advantage of having a small device occupation area and a large current gain. However, the insulating gate film thickness must be reduced, and the insulating film is easily destroyed by surge voltage or injection of hot electrons during operation.

It has been observed that dielectric breakdown of short channel MOS transistors occurs frequently, especially between the drain and gate.

An object of the present invention is to have a high current gain equivalent to that of a conventional short channel MOS transistor, and to have a high current gain as compared to a conventional short channel MOS transistor.
An object of the present invention is to provide a method for manufacturing a short channel MOS transistor having a high dielectric strength between the drain and gate.

An insulated gate semiconductor device according to the present invention has a pair of opposite conductivity type regions on one surface of a one conductivity type semiconductor substrate, and an insulated gate film and a gate electrode are provided on the substrate surface between the regions. The surface of the opposite conductivity type region is lower than the substrate surface, and the thickness of the insulating film covering the vicinity of the end portion reaching the substrate surface of the PN junction formed by at least one of the opposite conductivity type regions and the substrate, An effective feature of the present invention is that it has a configuration in which it has a rise compared to the thickness of the insulating film covering the opposite conductivity type region, and that this rise is self-aligned with the end of the PN junction. be.

The present invention provides a method for forming a gate oxide film and a gate electrode on one surface of a semiconductor substrate of one conductivity type, and then forming a pair of opposite conductivity type regions. After forming the gate electrode, a recess is formed by etching, and then the substrate is heat-treated to form a thermal oxide film that partially rises at the contact area between the pre-recess and the gate oxide film. The concave portion is formed on the surface of the concave portion, and then ion implantation is performed on the entire surface of the substrate to introduce an impurity of the opposite conductivity type directly under the concave portion, and heat treatment is performed. It is characterized by terminating at the raised part of the membrane.

The short channel MOS transistor obtained by the present invention has a thin central insulating gate film, so
It has a high current gain and can suppress the punch-through phenomenon. Furthermore, since the insulating gate film is thicker in the channel portions at the source and drain ends, the dielectric breakdown voltage between the source and the gate and between the drain and the gate is high, making it possible to realize a highly reliable short channel MOS transistor.

The present invention is based on the discovery that when a window is opened after forming a gate oxide film and a gate electrode, and the substrate in the corresponding window is etched and then oxidized, the surrounding area of the window rises.

Next, the present invention will be explained by examples.

FIG. 1 is a cross-sectional view of one embodiment of the present invention, in which figure a is a cross-sectional view of a process in the middle of manufacturing, and figure b is a cross-sectional view of a finished product.

In this embodiment, a known selective oxidation method using a silicon nitride film is applied to the upper surface of a P-type silicon single crystal substrate 101 of 1 Ωcm, and a 1.5
A field insulating film 102 of silicon oxide of about micron size is provided. After removing the silicon nitride film on the surface of the substrate in the active region, a gate insulating film 103 of silicon oxide with a thickness of about 400 Å is grown by thermal oxidation, and a gate electrode 104 of polycrystalline silicon with a thickness of 0.5 μm crosses the active region on the upper surface. form a selection.
This gate electrode 104 contains approximately 10 ²⁰ cm ^-3 of phosphorus in polycrystalline silicon to increase conductivity. The upper surface of this gate electrode 104 is coated with a silicon oxide film 105 of about 0.5 microns in advance in a selective etching process, and after processing the gate electrode 104, a silicon oxide film 105 of about 0.5 microns is coated.
Utilizing the thickness difference of the gate insulating film 103 of 400 Å, etching is performed by immersing it in a buffer solution for about 1 minute, thereby forming the source and drain on both sides of the gate electrode 104 as shown in FIG. 1a. The surfaces 106 and 107 of the silicon substrate 101 to be exposed are exposed. The exposed surfaces 106 and 107 are etched by plasma etching or chemical etching to remove
Selective etching is performed in a range of 5000 Å (Fig. 1a).

Next, thermal oxidation is performed in a steam atmosphere, and a silicon oxide film 1 with a thickness of 500 to 3000 Å is applied to the etched surface of the substrate.
08 is grown by thermal oxidation, and this silicon oxide film 108
Phosphorus ions ( ³¹ P ⁺ ) are introduced by ion implantation through the substrate to form N-type regions 109 and 110 that serve as sources and drains, and annealed in N ₂ at 800 to 1000° C. In these steps, the N-type regions 109, 11
The junction depth of 0 is about 0.2 microns, and the effective channel length, which is the interval between the N-type regions 109 and 110, is about 1 micron. From then on, normal
By making full use of MOS technology, N-type regions 109 and 110
Openings are provided in the silicon oxide films 105 and 108 on the upper surface of the gate electrode 104, and the aluminum drain electrode wiring 11 is passed through each opening.
1. Source electrode wiring 112, gate electrode wiring 11
3 (Fig. 1b).

In this embodiment, the silicon oxide film 108 on the upper surface of the end of the PN junction between the N-type regions 109 and 110 and the substrate that ends on the substrate surface has a thick bulge directly under the gate electrode 104. The gate breakdown voltage here can be increased and deterioration of electrical characteristics due to hot electron injection can be prevented.

FIG. 2 is a cross-sectional view of another embodiment of the invention.

In this embodiment, a field oxide film 102 and a gate oxide film 103 are formed on the surface of a silicon substrate 101 as in the previous embodiment, and then polycrystalline silicon with a thickness of about 0.3 to 0.8 microns is formed by vapor phase growth.
A silicon nitride film of about 1000 to 2000 Å is sequentially grown, and the silicon nitride film and polycrystalline silicon film are selectively etched by photolithography. In this state, a silicon nitride film 202 with the same pattern is placed on the upper surface of a gate electrode 201 made of polycrystalline silicon, and by removing the gate oxide film 103 made of silicon oxide with a buffer solution, Surfaces 106 and 107 of substrate 101 are exposed. In the subsequent steps, as in the previous embodiment, the silicon substrate is etched, thermally oxidized, sources and drains are formed by ion implantation, the necessary windows are opened, aluminum wiring electrodes are formed, and gates are formed.・
It is possible to realize short channel MOS transistors with thicker silicon oxide films between the source and between the gate and drain. In this embodiment, the gate electrode 20 is removed during the process of removing the gate oxide film 103 that exposes the substrate surface.
1 is covered with the silicon nitride film 202, the workability of the processing process can be improved.

Although the embodiments of the present invention have been described above, the material, conductivity type, etc. of the present invention can be easily changed as necessary. For example, polycrystalline silicon can be easily replaced with molybdenum, tungsten, or high-melting point conductive materials, and selective oxidation is
It is also easy to change to MOS process technology.

[Brief explanation of the drawing]

Fig. 1 is a cross-sectional view of one embodiment of the present invention, Fig. a is a cross-sectional view of the manufacturing process, Fig. b is a cross-sectional view of the finished product, and Fig. 2 is a cross-sectional view of another embodiment of the present invention. It is a diagram. 101...Silicon substrate, 102...Field oxide film, 103...Gate oxide film, 104...
Polycrystalline silicon electrode, 105... silicon oxide film, 108... silicon oxide film, 109... source, 110... drain, 111, 112, 11
3... Source, drain, gate aluminum wiring electrode, 201... Polycrystalline silicon electrode, 202
...Silicon nitride film.

Claims (1)

[Claims] 1. In a method of forming a gate oxide film and a gate electrode on one surface of a semiconductor substrate of one conductivity type, and then forming a pair of opposite conductivity type regions, forming the gate electrode on the surface of the substrate where the opposite conductivity type regions are to be formed. A recess is formed by post-etching,
Thereafter, by heat-treating the substrate, a thermal oxide film is formed on the surface of the recess so that the contact area between the pre-recess and the gate oxide film partially rises, and then ions are implanted into the entire surface of the substrate. an insulated gate, wherein an impurity of opposite conductivity type is introduced directly under the recessed portion and heat treatment is performed, and the PN junction end portion formed thereby is terminated at the raised portion of the thermal oxide film. A method for manufacturing a type semiconductor device.