KR100505630B1 - Method for manufacturing MOSFET having elevated source/drain - Google Patents

Abstract

A method of manufacturing a MOS field effect transistor having an elevated source / drain of the present invention includes forming an isolation layer surrounding an active region of a semiconductor substrate, forming a gate insulating layer on the active region, and forming a gate insulating layer on the gate insulating layer. Forming a low concentration source and drain region by implanting impurity ions into the ion implantation mask film, forming a gate electrode on the surface, oxidizing the surface of the gate electrode, and forming a spacer on the sidewall of the gate electrode. Forming, removing a gate insulating film between the spacer and the device isolation film, selectively forming a silicon film on the surface and the gate of the semiconductor substrate from which the gate insulating film is removed, and oxidizing the surface of the silicon film to form an oxide film And implanting impurity ions into the oxide film into the ion implantation buffer film. Forming a high concentration source and drain region with a shallow junction.

Description

Method for manufacturing MOSFET having elevated source / drain

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a MOS field effect transistor having an elevated source / drain.

As the degree of integration of semiconductor devices increases, the area of MOSFETs, which are one of the important elements constituting the device, also decreases. As the area of MOS field-effect transistors is getting smaller, the short-channel effect caused by the punch-through between the source and the drain causes the device characteristics such as switching function and power consumption. Deteriorate

In general, it is known that the short-channel effect can be suppressed by adopting a lightly doped drain (LDD) structure or by forming the source region and the drain region shallowly. However, there is a limit in suppressing the short-channel effect when adopting the LDD structure, for example, there is a problem that the short-channel effect is not suppressed in an element of 0.35 탆 or less. In the method of forming a shallow junction, metal silicide is formed on the source / drain region in order to reduce the contact resistance between the source / drain region and the metal wiring for the source / drain electrode. There is a problem that a portion of the surface is consumed to narrow the gap between the depletion region and the metal silicide. As such, when the gap between the depletion region and the metal silicide becomes narrow, leakage current is easily generated. In order to solve this problem, the thickness of the metal silicide must be reduced, but in this case, the contact resistance between the source / drain region and the metal silicide becomes high, and in the subsequent process of forming a contact hole, the metal silicide is etched or thinned. There is a problem that the resistance is further increased.

Therefore, in order to solve the above problems, recently, methods for manufacturing a MOS field effect transistor having an elevated source / drain have been proposed. These methods are methods for producing MOS field effect transistors having elevated source / drain using polysilicon pads or using selective epitaxial growth.

However, in the case of using the polysilicon pad, there is a problem in that the manufacturing cost increases due to the increase in the number of processes, and in the case of using the selective epitaxial growth method, it is possible to select a silicon film at a position other than silicon due to the selectivity loss in the process of selectively forming the silicon film. There is a problem that island-type silicon films are formed to generate an electrical short between the gate electrode and the source / drain in a subsequent metal silicide formation process.

SUMMARY OF THE INVENTION The present invention provides a method of manufacturing a MOS field effect transistor having an elevated source / drain having a shallow junction using a simple process method while suppressing occurrence of an electrical short between gate and source / drain in a metal silicide process. To provide.

In order to achieve the above technical problem, a method of manufacturing a MOS field effect transistor having an elevated source / drain according to the present invention, forming a device isolation film surrounding the active region of the semiconductor substrate; Forming a gate insulating film on the active region; Forming a gate electrode on the gate insulating film; Oxidizing a surface of the gate electrode; Implanting impurity ions into the gate electrode through an ion implantation mask layer to form a low concentration source and drain region; Forming a spacer on sidewalls of the gate electrode, removing the gate insulating layer between the spacer and the device isolation layer; Selectively forming a silicon film on a surface of the semiconductor substrate from which the gate insulating film is removed and on the gate; Oxidizing the surface of the silicon film to form an oxide film, and implanting impurity ions into the ion implantation buffer film to form a high concentration source and drain region having a shallow junction.

In the present invention, the step of removing the oxide film; And removing the oxide layer to form metal silicide on the exposed silicon layer and the silicon layer.

The silicon film may be formed using a high vacuum chemical vapor deposition method, but may be formed using Si ₂ H ₂ Cl ₂ , H _2, and HCl gas as a source gas at a pressure of 10-80 torr and a temperature of 700-850 ° C. Or may be formed using high vacuum chemical vapor deposition, but using Si ₂ H ₆ gas and Cl gas as source gas at a pressure of 2-80 mtorr and a temperature of 550-700 ° C.

Selectively forming the silicon film and oxidizing the surface of the silicon film are preferably performed in-situ in the same chamber.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the present invention can be modified in many different forms, the scope of the invention should not be construed as limited to the embodiments described below. The embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art.

1 to 6 are cross-sectional views illustrating a method of manufacturing a MOS field effect transistor having an elevated source / drain according to the present invention.

Referring to FIG. 1, an isolation layer 11 defining an active region A is formed on a silicon substrate 10. The active region A is isolated by the device isolation layer 11. Generally, the device isolation layer 11 uses a local oxide of silicon (LOCOS) method, but other methods such as trench device isolation may be used. In the case of using the LOCOS method, first, for example, a silicon nitride film pattern is formed on the silicon substrate 10 of the active area A to prevent the active area A from being oxidized, and the silicon nitride film pattern is prevented from growing. As a mask, a field oxide film as the device isolation film 11 is grown on the silicon substrate 10. Subsequently, a gate insulating layer 12 is formed on the silicon substrate 10 in the active region A. The thickness of the gate insulating film 12 is 20-1000 kPa, and the kind of the insulating film of SiON, SiO ₂ or the like or a laminated structure of the insulating film may be possible.

Referring to FIG. 2, a gate electrode 13 is formed by stacking a conductive layer for a gate electrode on the entire structure of FIG. 1 and patterning the gate electrode. The gate electrode 13 is formed using polysilicon, but in some cases, the gate electrode 13 may be formed using silver, a low manganese or a polysilicon low manganese alloy. The surface of the gate electrode 13 is then oxidized to form a thin oxide film 14. After oxidizing the surface of the gate electrode 13, the low concentration source region 15 and the low concentration drain region 16 are formed by implanting low concentration impurity ions with the gate electrode 13 using an ion implantation mask. In order to form the low concentration source region 15 and the low concentration drain region 16, impurity ions are implanted at a implantation concentration of 1 × 10 ¹³ -1 × 10 ¹⁴ / cm 3 using low energy of 2-30 KeV.

Referring to FIG. 3, after the insulating film for spacer formation is deposited on the entire structure of FIG. 2, an etch back process is performed to form the gate spacers 17 on the sidewalls of the gate electrodes 13. The gate spacer 17 may be formed of a silicon nitride film or a silicon oxide film. The gate insulating layer 12 between the device isolation layer 11 and the gate spacer 17 is removed. Subsequently, a silicon film is formed by selectively growing silicon on the silicon substrate 10 and the gate electrode 13 between the device isolation film 11 and the gate spacer 17. In this case, a silicon film 18 is formed on the silicon substrate 10, and a polysilicon film 19 is formed on the gate electrode 13 formed using the polysilicon film. The silicon film 18 and the polysilicon film 19 may be formed using a low pressure chemical vapor deposition method, or may be formed using a high vacuum chemical vapor deposition method. In the case of using the low pressure chemical vapor deposition method, the silicon film 18 and the polysilicon film (Si ₂ H ₂ Cl ₂ , H _2, and HCl gas are used as source gases at a pressure of 10-80 torr and a temperature of 700-850 ° C. 19). In the case of using the high vacuum chemical vapor deposition method, the silicon film 18 and the polysilicon film 19 are formed by using Si ₂ H ₆ gas and Cl gas as source gas at a pressure of 2-80 mtorr and a temperature of 550-700 ° C. To form. The thickness of the formed silicon film 18 is approximately 500-1500 kPa, and the thickness of the polysilicon film 19 is thicker than the thickness of the silicon film 18. In this process step, island-type silicon films 20 may be formed at a place other than the surface of the silicon substrate 10 and the gate electrode 13 by selective loss due to various process conditions in chemical vapor deposition. have. That is, the island-type silicon films 20 may be formed in a place where the silicon film is not to be formed, such as the device isolation layer 11 and the gate spacer 17. As described above, the island-type silicon films 20 are an important cause of shorting between the gate electrode and the source / drain in a subsequent metal silicide formation process.

Therefore, referring to FIG. 4, the silicon film 18, the polysilicon film 19, and the island-type silicon film 20 are oxidized. Then, the first oxide film 21 is formed on the surface of the silicon film 18, the second oxide film 22 is formed on the surface of the polysilicon film 19, and the third oxide film is formed on the surface of the silicon film 20 having an island shape. 23 are formed respectively. At this time, since the oxidation rate of the polysilicon film 19 is faster than the oxidation rate of the single crystal silicon film 18, the thickness of the second oxide film 22 is thicker than the thickness of the first oxide film 21. Meanwhile, in a subsequent metal silicide forming process, an island-type silicon film 20 that shorts between the gate electrode and the source / drain is oxidized to the third oxide film 23 to prevent an electrical short circuit between the gate electrode and the source / drain. can do.

Next, referring to FIG. 5, a high concentration of impurity ions are implanted using the gate spacer 17 as an ion implantation mask and the first oxide film 21 as an ion implantation buffer film. Then, as shown, a high concentration of the source region 24 and a high concentration of the drain region 25 are formed, respectively. Since the first oxide film 21 is used as an ion implantation buffer film, a shallow source / drain region can be easily formed. Can be.

Next, referring to FIG. 6, the first oxide film 21, the second oxide film 22, and the third oxide film 23 are removed. And a metal silicide forming process. Namely, in detail, a metal layer is laminated on the entire surface. The metal layer is formed using a refractory metal, and may be formed using Ti, Co or Ni. Next, a heat treatment process is performed in an N ₂ , NH _3, or Ar atmosphere to form silicide on the bonding surface of the silicon film 18 and the metal layer and the bonding surface of the polysilicon film 19 and the metal layer. Subsequently, removing the unreacted metal layer and the metal nitride layer from the H ₂ O ₂ , H ₂ SO ₄ and H ₂ O solution leaves only the necessary metal electrode layer 26 as shown, thereby completing the metal silicide.

While many details are set forth in the foregoing description, they should be construed as illustrative of preferred embodiments rather than to limit the scope of the invention. Therefore, the scope of the present invention should not be defined by the described embodiments, but should be determined by the technical spirit described in the claims.

As described above, according to the MOS field effect transistor having an elevated source / drain region according to the present invention, an island-type silicon film generated in the process of forming a silicon layer selectively to form an elevated source / drain region is formed. Since the metal silicide process is performed after the oxidation and removal, the electrical short circuit between the gate electrode and the source / drain can be prevented during the metal silicide process, and the shallow source is implanted by implanting impurity ions using the oxide film on the silicon film as an ion implantation buffer film. The / drain region can be easily formed.

1 to 6 are cross-sectional views illustrating a method of manufacturing a MOS field effect transistor having an elevated source / drain according to the present invention.

<Explanation of symbols for the main parts of the drawings>

10 ... silicon substrate 11 ... element separator

12 gate insulating film 13 gate electrode

14 oxide 15, 24 source region

16, 25 ... drain area 17 ... gate spacer

18.Silicone film 19 ... Polysilicon film

20 Irish silicon film 21 First oxide film

22 ... second oxide film 23 ... third oxide film

26.Metal electrode layer

Claims (5)

Forming an isolation layer surrounding the active region of the semiconductor substrate; Forming a gate insulating film on the active region; Forming a gate electrode on the gate insulating film; Oxidizing a surface of the gate electrode; Implanting impurity ions into the gate electrode through an ion implantation mask layer to form a low concentration source and drain region; Forming a spacer on sidewalls of the gate electrode; Removing the gate insulating film between the spacer and the device isolation layer; Selectively forming a silicon film on a surface of the semiconductor substrate from which the gate insulating film is removed and on the gate; Oxidizing a surface of the silicon film to form an oxide film; and Implanting impurity ions into the ion implantation buffer film to form a high concentration source and drain region having a shallow junction. The method of claim 1, Removing the oxide film; And Forming a metal silicide on the exposed silicon film and the silicon layer by removing the oxide film; and further, forming a metal silicide on the exposed silicon film and the silicon layer. delete delete The method of claim 1, Selectively forming the silicon film and oxidizing the surface of the silicon film are performed in-situ in the same chamber, wherein the MOS field effect transistor having an elevated source / drain is formed.