KR20040001131A - Method for forming the semiconductor device - Google Patents
Method for forming the semiconductor device Download PDFInfo
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- KR20040001131A KR20040001131A KR1020020036231A KR20020036231A KR20040001131A KR 20040001131 A KR20040001131 A KR 20040001131A KR 1020020036231 A KR1020020036231 A KR 1020020036231A KR 20020036231 A KR20020036231 A KR 20020036231A KR 20040001131 A KR20040001131 A KR 20040001131A
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- gate electrode
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- oxide film
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- 238000000034 method Methods 0.000 title claims abstract description 33
- 239000004065 semiconductor Substances 0.000 title abstract description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 12
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 12
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 12
- 239000010703 silicon Substances 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000005530 etching Methods 0.000 claims description 15
- 239000012535 impurity Substances 0.000 claims description 11
- 239000007943 implant Substances 0.000 claims description 6
- 230000003213 activating effect Effects 0.000 claims description 5
- 150000004767 nitrides Chemical class 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 8
- 230000000694 effects Effects 0.000 abstract description 5
- 238000000137 annealing Methods 0.000 abstract description 3
- 125000006850 spacer group Chemical group 0.000 abstract description 3
- 239000002019 doping agent Substances 0.000 abstract 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 229920005591 polysilicon Polymers 0.000 description 6
- 238000010438 heat treatment Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 125000004430 oxygen atom Chemical group O* 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
본 발명은 반도체소자의 제조방법에 관한 것으로서, 보다 상세하게는 LDD 형성을 위해 주입된 불순물을 활성화하기 위한 열처리 공정에 의해 역 단채널(RSC : Rever Short Channel)효과의 발생이 방지하도록 하여 트랜지스터의 전기적인 특성을 향상시키도록 하는 반도체소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to prevent occurrence of a reverse short channel (RSC) effect by a heat treatment process for activating impurities implanted to form an LDD. It relates to a method for manufacturing a semiconductor device to improve the electrical characteristics.
일반적으로, 모스형전계효과 트랜지스터는 실리콘기판에 필드산화막을 형성한 후에 그 전면에 게이트 산화막 및 폴리실리콘층을 활성영역(Active Region)에 형성하고서 마스킹 식각으로 트랜지스터의 전극역할을 하는 게이트전극을 형성하여 이 게이트전극의 측면부분에 있는 실리콘기판에 이온을 주입하여 소오스/드레인영역을 형성하므로 트랜지스터로서 사용될 수 있게 된다.In general, a MOS type field effect transistor forms a field oxide film on a silicon substrate, and then forms a gate oxide film and a polysilicon layer in an active region on a front surface thereof, and forms a gate electrode that acts as an electrode of the transistor by masking etching. As a result, a source / drain region is formed by implanting ions into the silicon substrate on the side of the gate electrode, which can be used as a transistor.
이러한 트랜지스터에 게이트 산화막은 상부와 하부사이를 전기적으로 차단하는 절연역할을 하게 되는 것으로서, 반도체소자에서 전기적으로 전압이 높은 고전압영역과 전압이 낮은 저전압 영역이 동시에 사용되는 멀티플 게이트 산화막(Multiple Gate Oxide)을 갖는 트랜지스터에서는 고전압영역의 게이트 산화막의 두께는 두껍게 형성하고, 저전압영역에서는 게이트 산화막의 두께를 얇게 형성하여서 전기적으로 절연이 적절하게 이루어지도록 구성되어져 있다.In this transistor, the gate oxide film serves as an insulating role for electrically blocking the top and the bottom of the transistor. In the semiconductor device, a multiple gate oxide film in which a high voltage region with high voltage and a low voltage region with low voltage is used simultaneously is used. In the transistor having the structure, the gate oxide film in the high voltage region is formed to be thick, and in the low voltage region, the gate oxide film is formed in the thickness so that the insulation is properly performed.
도 1a 내지 도 1c는 종래의 일반적인 반도체소자의 게이트전극 형성방법을 순차적으로 보인 도면으로서, 종래의 공정을 살펴보도록 한다.1A to 1C are sequential views of a method of forming a gate electrode of a conventional semiconductor device, and a process of the related art will be described.
도 1a에 도시된 바와 같이, 필드산화막(2)이 형성된 실리콘기판(1) 상에 게이트산화막(3)과 폴리실리콘막(4)을 순차적으로 적층한 후, 노광공정 및 식각 공정에 의해 게이트전극이 패터닝되어 게이트전극 패턴(5)이 형성된다.As shown in FIG. 1A, the gate oxide film 3 and the polysilicon film 4 are sequentially stacked on the silicon substrate 1 on which the field oxide film 2 is formed, and then the gate electrode is formed by an exposure process and an etching process. The patterned pattern forms the gate electrode pattern 5.
그리고, 도 1b에 도시된 바와 같이, 상기 게이트전극 패턴(5)을 마스크로 엘디디(LDD : Lightly Doped Drain) 형성을 위한 불순물 임플란트(Implant) 공정이 진행되어 소오스/드레인(6)이 형성되었다.As shown in FIG. 1B, an impurity implant (Implant) process for forming a lightly doped drain (LDD) is performed using the gate electrode pattern 5 as a mask to form a source / drain 6. .
이어서, 도 1c에 도시된 바와 같이, 상기 주입된 불순물을 활성화하기 위한 폴리 열처리(annealing) 공정을 진행된 후, 상기 게이트전극 패턴(5) 측벽에 질화물 또는 산화물을 이용하여 스페이서(7)를 형성하여 워드라인을 형성하였다.Subsequently, as shown in FIG. 1C, after performing a poly annealing process for activating the implanted impurities, spacers 7 are formed on the sidewalls of the gate electrode pattern 5 using nitrides or oxides. A word line was formed.
그런데, 상기와 같은 종래의 반도체소자의 게이트전극 형성방법을 이용하게 되면, 상기 소오스/드레인이 형성을 위해 주입된 불순물을 활성화시키기 위한 열처리 공정 시, 옥시데이션 확산 상승에 의해 하부 게이트산화막의 상부 모서리 부분이 "A"와 같이 두께가 증가되어 폴리의 두께를 작게 함으로써, 역 단채널효과(Rever Short Channel)가 발생되어 트랜지스터의 전기적인 특성이 저하되는 문제점을 가지고 있다.However, when using the conventional method of forming the gate electrode of the semiconductor device as described above, during the heat treatment process for activating the impurity implanted for the source / drain formation, the upper edge of the lower gate oxide film by the oxidative diffusion As the portion is increased in thickness such as "A" to reduce the thickness of the poly, a short short channel is generated and the electrical characteristics of the transistor are deteriorated.
본 발명은 상기와 같은 문제점을 해결하기 위해 안출된 것으로, 본 발명이 목적은 필드산화막이 형성된 실리콘기판 상에 게이트산화막과 게이트전극을 순차적으로 적층한 후, 노광공정 및 식각 공정에 의해 게이트전극이 패터닝되어 게이트전극 패턴을 형성함에 있어서, 상기 폴리실리콘막 하부의 게이트산화막 에지부분을 식각하여 게이트산화막의 두께를 동일하게 형성한 후, LDD를 형성함으로써, 역 단채널(RSC : Rever Short Channel)효과의 발생을 방지하여 트랜지스터의 전기적인 특성을 향상시키도록 하는 반도체소자의 제조방법을 제공하는 것이 목적이다.The present invention has been made to solve the above problems, and an object of the present invention is to sequentially deposit a gate oxide film and a gate electrode on a silicon substrate on which a field oxide film is formed, and then the gate electrode is formed by an exposure process and an etching process. In forming the gate electrode pattern by patterning, the edge portion of the gate oxide layer under the polysilicon layer is etched to form the same thickness of the gate oxide layer, and then LDD is formed to form a reverse short channel (RSC) effect. It is an object of the present invention to provide a method for manufacturing a semiconductor device, which prevents the occurrence of the semiconductor element and improves the electrical characteristics of the transistor.
도 1a 내지 도 1c는 종래의 일반적인 반도체소자의 제조방법을 설명하기 위해 순차적으로 나타낸 단면도이다.1A to 1C are cross-sectional views sequentially illustrating a conventional method for manufacturing a conventional semiconductor device.
도 2a 내지 도 2e는 본 발명의 바람직한 실시예에 따른 반도체소자의 제조방법을 설명하기 위해 순차적으로 나타낸 단면도이다.2A through 2E are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor device in accordance with a preferred embodiment of the present invention.
-- 도면의 주요부분에 대한 부호의 설명 ---Explanation of symbols for the main parts of the drawing-
11 : 실리콘기판 12 : 필드산화막11 silicon substrate 12 field oxide film
13 : 게이트산화막 14 : 게이트전극13 gate oxide film 14 gate electrode
15 : 게이트전극 패턴 16 : 감광막 패턴15 gate electrode pattern 16 photosensitive film pattern
17 : LDD 18 : 측벽 스페이서17: LDD 18: side wall spacer
상기 목적을 달성하기 위하여, 본 발명은 필드산화막이 형성된 실리콘기판에 게이트산화막과 게이트전극 및 하드마스크를 순차적으로 적층한 후, 노광 및 식각 공정을 진행하여 게이트전극 패턴을 형성하는 단계와, 상기 게이트전극 패턴을 마스크로 불순물 임플란트(Implant) 공정을 진행하여 소오스/드레인을 형성하는 단계와, 상기 결과물 상에 폴리 열공정을 진행하여 주입된 불순물을 활성화한 후, 상기 게이트전극 패턴 상부에 감광막을 도포하는 단계와, 상기 열공정에 의해 두께가 두꺼워진 게이트산화막의 가장자리가 식각되도록 감광막에 노광 및 식각 공정을 진행하여 감광막 패턴을 형성하는 단계와, 상기 감광막 패턴을 식각마스크로 식각공정을 진행하여 두께가 다른 게이트산화막의 가장자리를 식각하여 게이트산화막의 두께를 동일하게 하는 단계와, 상기 게이트패턴 측벽에 질화물 또는 산화물을 이용하여 측벽스페이스를 형성한 후 , 엘디디(LDD : Lightly Doped Drain)를 형성하는 단계를 포함하여 이루어진 것을 특징으로 한다.In order to achieve the above object, the present invention is a step of sequentially forming a gate oxide film, a gate electrode and a hard mask on a silicon substrate on which a field oxide film is formed, and then forming a gate electrode pattern by performing an exposure and etching process, and the gate Impurity implant (Implant) process using an electrode pattern as a mask to form a source / drain, and a poly-thermal process on the resultant to activate the implanted impurities, and then applying a photosensitive film on the gate electrode pattern And forming a photoresist pattern by performing an exposure and etching process on the photoresist so that the edge of the gate oxide film thickened by the thermal process is etched, and etching the photoresist pattern with an etch mask. Etch the edges of other gate oxides to make the gate oxides the same thickness Characterized in that made in forming a: (Lightly Doped Drain LDD) step and, after formation of the sidewall spaces using a nitride or oxide on the gate pattern side wall, El Didier.
본 발명은 상기 게이트전극 하부의 게이트산화막 에지부분을 식각하여 게이트산화막의 두께를 동일하게 형성한 후, LDD를 형성함으로써, 역 단채널(RSC : Rever Short Channel)효과의 발생을 방지하여 트랜지스터의 전기적인 특성을 향상시킬 수 있다.According to the present invention, an edge portion of the gate oxide layer under the gate electrode is etched to form the same thickness of the gate oxide layer, and then an LDD is formed to prevent occurrence of a reverse short channel (RSC) effect, thereby preventing electric Can improve the characteristics.
이하, 첨부한 도면을 참조하여 본 발명의 바람직한 일실시예를 상세히 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2e는 본 발명의 바람직한 실시예에 따른 반도체소자의 제조방법을 설명하기 위해 순차적으로 나타낸 단면도이다.2A through 2E are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor device in accordance with a preferred embodiment of the present invention.
도 2a에 도시한 바와 같이, 실리콘기판(11) 상에 아이솔레이션 영역, 예컨대 STI(Shallow Trench Isolation) 영역에 의해 실리콘기판(11) 상부에 필드산화막(12)을 형성함으로써, 실리콘기판(11)을 액티브 영역과 필드 영역으로 구분한 후, 상기 액티브 영역의 상부에 산화막을 약 70 ~ 100Å의 두께로 얇게 성장시킴으로써 메모리 셀의 게이트산화막(13)을 형성한다.As shown in FIG. 2A, the silicon substrate 11 is formed by forming a field oxide film 12 over the silicon substrate 11 by an isolation region, for example, a shallow trench isolation (STI) region, on the silicon substrate 11. After dividing into an active region and a field region, a gate oxide layer 13 of the memory cell is formed by thinly growing an oxide layer on the active region to a thickness of about 70 to about 100 microns.
그리고, 상기 게이트산화막(13)이 형성된 결과물의 상부에 게이트전극(14)으로서, 예컨대 폴리실리콘층을 약 1000~1500Å이 두께로 화학기상증착 방법 또는 스퍼터링 방법을 이용하여 증착하고 노광공정 및 식각 공정을 진행하여 하드마스크(미도시함)를 형성한 후, 이를 식각마스크로 게이트전극(14)을 패터닝하여 게이트전극 패턴(15)을 형성한다.Then, as the gate electrode 14, the polysilicon layer is deposited to a thickness of about 1000 to 1500 Å by using a chemical vapor deposition method or a sputtering method as a gate electrode 14 on the resultant on which the gate oxide film 13 is formed, and an exposure process and an etching process. After forming a hard mask (not shown), the gate electrode 14 is patterned using an etching mask to form the gate electrode pattern 15.
이어, 도 2b에 도시된 바와 같이, 상기 게이트전극 패턴(15)을 마스크로 실리콘기판(11) 내에 소오스/드레인을 형성을 위한 불순물 임플란트(Implant) 공정을 진행한다.Subsequently, as illustrated in FIG. 2B, an impurity implant process is performed to form a source / drain in the silicon substrate 11 using the gate electrode pattern 15 as a mask.
그 후, 도 2c에 도시된 바와 같이, 상기 결과물 상에 주입된 불순물을 활성화시키기 위해 폴리 열공정(annealing)을 진행한 후, 상기 게이트전극 패턴(15) 상부에 감광막(미도시함)을 도포한다. 그리고, 상기 감광막을 열공정에 의해 두께가 두꺼워진 게이트산화막(13)의 가장자리가 식각되도록 노광 및 식각 공정을 진행하여 감광막 패턴(16)을 형성한다.Thereafter, as shown in FIG. 2C, a poly thermal process (annealing) is performed to activate impurities implanted on the resultant, and then a photosensitive film (not shown) is coated on the gate electrode pattern 15. do. In addition, the photoresist layer may be exposed and etched to etch the edges of the gate oxide layer 13 having a thick thickness by a thermal process to form the photoresist pattern 16.
이때, 상기 소오스/드레인이 형성을 위해 주입된 불순물을 활성화시키기 위한 열처리 공정 시, 옥시데이션 확산 상승에 의해 하부 게이트산화막(13)의 상부 가장자리 부분이 "A"와 같이 확산되어 게이트산화막(13)의 중앙 부분과 가장자리 부분의 두께가 다르게 형성된다. 즉, 상기 게이트산화막(13)의 가장자리 부분의 산소원자가 상부 폴리실리콘으로 이루어진 게이트전극(14) 하부 가장자리쪽으로 확산되어 게이트산화막(13)의 가장자리의 두께가 두껍게 형성된다.At this time, during the heat treatment process for activating the impurity implanted to form the source / drain, the upper edge portion of the lower gate oxide layer 13 is diffused as “A” by the oxidative diffusion, so that the gate oxide layer 13 The thickness of the center part and the edge part is formed differently. That is, oxygen atoms at the edges of the gate oxide film 13 diffuse toward the lower edge of the gate electrode 14 made of upper polysilicon, so that the thickness of the edge of the gate oxide film 13 is thick.
이어서, 도 2d에 도시된 바와 같이, 상기 감광막 패턴(미도시함)을 식각 마스크로 식각공정을 진행하여 상기 열처리 공정에 의해 두께가 두꺼워진 게이트산화막(13)의 가장자리를 식각하여 게이트산화막(13)의 두께를 중앙부분과 가장자리 부분이 동일하게 한 후, 상기 감광막 패턴(미도시함)을 제거한다.Subsequently, as shown in FIG. 2D, the etching process is performed using the photoresist pattern (not shown) as an etching mask to etch the edge of the gate oxide layer 13 thickened by the heat treatment process to form a gate oxide layer 13. ), The center portion and the edge portion have the same thickness, and then the photoresist pattern (not shown) is removed.
그리고, 도 2e에 도시된 바와 같이, 상기 게이트패턴(15) 측벽에 질화물 또는 산화물을 이용하여 측벽스페이스(18)를 형성하여 게이트전극 패턴(15)을 보호한 후, 엘디디(LDD : Lightly Doped Drain)(17)를 형성한다.As shown in FIG. 2E, after the sidewall space 18 is formed on the sidewall of the gate pattern 15 by using nitride or oxide, the gate electrode pattern 15 is protected, and then the LED is lightly doped. Drain) 17 is formed.
따라서, 본 발명에 따른 반도체소자의 제조방법을 이용하면 상기 폴리실리콘막 하부 게이트산화막의 두께를 동일하게 형성한 후, LDD를 형성하여 역 단채널(RSC : Rever Short Channel)효과의 발생이 방지함으로써, 트랜지스터의 전기적인 특성을 향상시켜 반도체소자의 특성과 신뢰성을 향상시킬 수 있는 효과가 있다.Therefore, by using the method of manufacturing a semiconductor device according to the present invention by forming the same thickness of the lower gate oxide film of the polysilicon film, LDD is formed to prevent the occurrence of a reverse short channel (RSC) effect In addition, the electrical characteristics of the transistor can be improved to improve the characteristics and reliability of the semiconductor device.
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