KR0172820B1 - Method of manufacturing semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same. The present invention relates to an MOSFET having an LDD structure that can be effectively applied to a semiconductor device of 256 M DRAM or higher.

The present invention is a semiconductor substrate; A low-concentration silicon single crystal layer of opposite conductivity type to the substrate formed on the semiconductor substrate at predetermined intervals above the predetermined region; A gate insulating film formed over an upper region of the substrate between the low concentration silicon single crystal layer and the entire surface of the low concentration silicon single crystal layer; A gate electrode formed over an upper region of the substrate between the low concentration silicon single crystal layers and a predetermined region over the low concentration silicon single crystal layer; Improving short channel effect and hot carrier characteristics by providing a semiconductor device including a high concentration source and a drain formed on the surface of the low concentration silicon single crystal layer across the gate electrode and spaced apart from the gate electrode at predetermined intervals, respectively, and controlling transistor characteristics. And the transistor channel length is extended to facilitate the high integration of the device.

Description

Semiconductor device and manufacturing method

1 is a process flowchart showing a method for manufacturing a MOSFET of a conventional LDD structure.

2 is a MOSFET cross-sectional structure diagram of the LDD structure according to the present invention.

3 is a process flowchart showing a method for manufacturing a MOSFET of an LDD structure according to an embodiment of the present invention.

4 is a process flowchart showing a method for manufacturing a MOSFET of an LDD structure according to another embodiment of the present invention.

5 is a process flowchart showing a method for manufacturing a MOSFET of an LDD structure according to still another embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

20: semiconductor substrate 21: n ^- silicon single crystal layer

22 photoresist pattern 23 gate oxide film

24: gate electrode 25: gate electrode upper insulating film

26: sidewall spacer 27: n ⁺ source and drain

28 Insulation layer 29 Source and drain electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a sub-micron-type MOSFET (Metal Oxide Semiconductor Field Effect Transist-or) structure requiring a high degree of integration and a method of manufacturing the same.

In general, integrated circuits of semiconductor devices require high quality of circuit performance and high density in their manufacture. Therefore, in the case of MOSFETs, as a result of efforts to reduce the device size, the manufacturing technology of semiconductor integrated circuits has been scaled down to the micron level.

The reduction of the semiconductor device must be balanced with the characteristics of the various devices only when the horizontal area is reduced and the vertical area is reduced in proportion to the horizontal area. In other words, when the size of the device decreases and the gap between the source and the drain approaches, there is a change in the characteristics of the unwanted device, and the representative short channel effect is a short channel effect. In order to solve this short channel effect, it is necessary to reduce the horizontal scale down, that is, reduce the gate length, and reduce the vertical scale down, that is, the thickness of the gate insulating layer and the junction depth, and accordingly, apply the applied voltage. Lower the doping concentration of the semiconductor substrate, and in particular, control the dop-ing profile of the implantation depth of the impurity ions in the channel region. However, since the operating power of the semiconductor device must satisfy the power value required by the electronic product using the device, the dimension of the semiconductor device is being scaled down, but the electrical dimension of the operating power required by the circuit has not been reduced yet.

In the case of MOS devices of semiconductor devices, in particular MOS transistors, the gap between the source and the drain decreases as the channel length becomes shorter. As a result, the electrons applied from the source are vulnerable to a hot carrier which is rapidly accelerated by a high electric field near the pinchoff in the channel direction of the drain junction (see Chenming Huet). al., hot-electron-induced MOSFET degradat-ion motal, monitor and improvement, IEEE transactions on electron devices, Vol.ED-32, No.2 (February 1985), pp. 375-385)

According to the paper cited above, the instability of the hot carrier is caused by a very high electric field near the drain junction due to the short channel length and the high applied voltage. The hot carriers (electrons) generated in this way are injected with a gate insulating film to flow the substrate current again. Therefore, in 1978, a L-ightly doped drain (LDD) structure was proposed, which improved the existing NMOS device structure, which has a reduced channel length and is vulnerable to hot carriers.

The characteristic of the LDD structure is that the lateral length is narrow, and the self-aligned lightly doped n-type region (n ⁻ region) is located between the channel and the heavily doped n-type source and drain region (n ⁺ region). This n ⁻ region spreads out a high electric field near the drain junction so that electrons, which are carriers applied from the source, are not accelerated rapidly even at high applied voltages, thereby solving the instability of the current caused by the hot carrier.

As a technology of manufacturing semiconductor devices having an integrated density of 1M DRAM or higher has been studied, various technologies for manufacturing a MOSEFT having an LDD structure have been proposed. Among them, the LDD manufacturing method using the method of forming the sidewall space with the insulator on the side of the gate is the most typical, and this technique has been used for most mass production technology.

FIG. 1 shows a method of manufacturing a MOSFET having an LDD structure according to the prior art in the order of a process.

First, as shown in FIG. 1A, the active region 10a and the isolation region 10b are formed on the silicon substrate 10 by a conventional method, and then the gate insulating film 12 is formed on the front surface. The silicon layer 13 'and the capgate oxide film 14' are sequentially formed.

Thus, as shown in FIG. 1 (b), the capgate oxide film and the polysilicon are patterned by a photolithography process to form the capgate oxide film 14 and the gate 13.

Next, as shown in Fig. 1 (c), phosphorus is implanted at a low dose with low implantation energy to form the n ⁻ region 101.

Subsequently, in order to form sidewall spaces as illustrated in FIG. 1D, the silicon oxide film 15 is deposited on the entire surface of the substrate by chemical vapor deposition (CVD).

Next, as shown in FIG. 1 (e), the entire surface of the silicon oxide film 15 is etched back by using a reactive ion etch technique, and the side surfaces of the gate 13 and the gate oxide film 14 are left. At this time, the gate insulating film 12 which is not protected by the gate is also etched to expose the surface of the silicon substrate. Therefore, a sidewall space 15 ′ formed of a part of the silicon oxide film 15 and a part of the gate insulating film 12 is formed on the side surface of the gate 13 and the cap gate oxide film 14.

Subsequently, the source and drain 102 are formed by ion implanting n-type impurities with a high dose to form a deeply doped junction and a heavily doped (n ⁺ ) source and drain as shown in FIG. At this time, the gate side wall space (15 '), so that the high-concentration ion injection when the barrier (barrier) serves to form the n ⁺ source and drain of these high-concentration doped in the gate channel (C) and the n ⁺ source and drain (102) It is possible to form an n ⁻ junction 101 ′ that is not affected by. However, there are some problems in the manufacturing method of the LDD device using the gate sidewall spacer as described above, which is not suitable as a practical technology for manufacturing next-generation semiconductor devices that require high integration and high quality.

That is, manufacturing processes such as an oxide film deposition and an etch back process by a CVD method for forming the gate sidewall spacers are added, and the surface of the silicon substrate of the active region may be exposed and contaminated during etching of the oxide film for forming the sidewall spacers. The exposed active impact damages the overetched, ie, the silicon substrate, and the overetched depth shows different unevenness depending on the position of the silicon substrate and the degree of integration of the pattern. You lose.

In addition, due to the etching of the substrate, the junction depth between the source and the drain is deepened, and thus the MOSFET cannot be satisfied with the hot carrier characteristics in the MOSFET device having a channel length of 0.5 μm or less.

On the other hand, in the conventional planar type source / drain junction transistor, since the source / drain junction is diffused toward the channel, the gate channel length of the mast is actually reduced in the MOSFET, so it is essentially 256M DRAM or more. The MOSFET structure is not suitable.

That is, since the diffusion to the lower side of the gate during the diffusion process for forming the source / drain junction, the channel length after the source / drain junction is actually formed smaller than the channel length defined on the mast.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and an object thereof is to provide a MOSFET and a method of manufacturing the same, which can be effectively applied to 256M DRAM or higher.

In order to achieve the above object, a Bonner invention semiconductor device includes a semiconductor substrate and a substrate formed between a low concentration silicon single crystal layer and a low concentration silicon single crystal layer of opposite conductivity to a substrate formed at a small interval apart from a predetermined region of the semiconductor substrate. A gate insulating film formed over an entire region of the region and the low-concentration silicon single crystal layer, a gate electrode formed over an upper region of the substrate between the low-concentration silicon single crystal layer and a predetermined region over the low-concentration silicon single crystal layer, and a surface of the low-concentration silicon single crystal layer across the gate electrode It includes a high concentration source and a drain formed in the portion spaced apart from the gate electrode at a predetermined interval.

The semiconductor device manufacturing method of the present invention for achieving the above object is epitaxially grown on the semiconductor substrate and a low concentration silicon single crystal layer of the opposite conductivity type to the substrate, and selectively etching the low concentration silicon single crystal layer of the transistor channel region Exposing a substrate portion, forming a gate insulating film over the low concentration silicon single crystal layer and the exposed substrate, forming a gate electrode on a predetermined region over the low concentration silicon single crystal layer including the transistor channel region, the gate Forming a sidewall spacer on the side of the electrode, implanting impurities of opposite conductivity to the substrate at a high concentration to form a high concentration source and drain junction on the surface of the low concentration silicon single crystal layer, and forming an insulating film on the entire surface of the substrate And performing an annealing process. Than it has done.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

2 shows a MOSFET cross-sectional structure according to the present invention.

In the MOSFET of the present invention, n ⁻ silicon single crystal layers 21 serving as LDD regions are formed in predetermined regions on the p-type semiconductor substrate 20, respectively, spaced a predetermined distance apart, and the upper portions of the substrates between the n ⁻ silicon single crystal layers 21 are formed. region and the n ^- is formed a gate insulating film on the low-concentration silicon single crystal layer over the ^n-gate in the silicon single crystal layer 21 insulating an upper portion of the gate over a predetermined area ^film-silicon single crystal layer 21, a substrate region and a n between An electrode 24 is formed, and n ⁺ source and indents 27 are formed on the surface of the n ⁻ silicon single crystal layer 21 on both ends of the gate electrode and are formed at predetermined intervals from the gate electrode.

Referring to Figure 3 describes a MOSFET manufacturing method according to an embodiment of the present invention as follows.

First, as shown in FIG. 3A, epitaxial growth of the n ⁻ silicon single crystal layer 21 doped with phosphorus is performed on the p-type semiconductor substrate 20 by forming n ⁻ LDD regions. . At this time, the concentration of phosphorus (P) is -10 ¹⁸ ions / cm ² , and the thickness of the n ^- silicon single crystal layer 21 is -1000 Pa. Subsequently, a photoresist pattern 22 defining a gate channel region is formed on the n ⁻ silicon single crystal layer 21. Subsequently, as shown in FIG. 3B, the n ^- silicon single crystal layer 21 is etched using the photoresist pattern 22 as a mask to expose the substrate of the channel region. As shown in FIG. 5, the photoresist pattern is removed using H ₂ SO ₄ / H ₂ O _2, and then subjected to an oxidation process in an H ₂ / O ₂ atmosphere at 850 ° C., so that a gate oxide film 23 having a thickness of about 100 μs is formed on the entire surface of the substrate. To form.

Next, as shown in FIG. 3 (d), n ⁺ polysilicon doped with phosphorus (P) is deposited on the entire surface of the substrate, and a CVD oxide film 25 is formed thereon as an insulating film.

Subsequently, as shown in FIG. 3E, the CVD oxide layer 25 and the n ⁺ polysilicon layer are patterned into a gate electrode pattern through a photolithography process to form the gate electrode 24 and the gate electrode upper insulating layer 25. Form. In this case, the gate electrode 24 overlaps the n ⁻ silicon single crystal layer 21 across the channel region by a predetermined length.

Next, as shown in FIG. 3 (f), a CVD oxide film is deposited as an insulating film, for example, to form sidewall spaces on the entire surface of the substrate, and then etched back by a method such as reactive ion etching to form a gate electrode 24 and a gate. The sidewall spacer 26 is formed on the side surface of the electrode upper oxide film 25. Subsequently, As is ion implanted under the conditions of 5.0 × ^{10 15} ions / cm ² and ³⁰ KeV to form n ⁺ source and drain junction 27.

Subsequently, as shown in FIG. 3G, for example, a CVD oxide film is formed as the insulating film 28 on the entire surface of the substrate, and an annealing process is performed at a temperature of about 870 占 폚. At this time, impurities of the n ⁻ silicon single crystal layer 21 are lightly auto-doped toward the substrate to form a junction of a source and a drain.

Next, as shown in FIG. 3 (h), a CVD oxide film is selectively removed as the insulating film 28 to form a contact hole exposing the formed n ⁺ source and drain 27, and then a conductive layer thereon. Is formed and patterned in a predetermined pattern to form the source and drain electrodes 29 respectively connected to n ⁺ source and drain 27 through the contact hole, thereby completing the manufacture of the MOSFET of the LDD structure according to the present invention.

Next, a MOSFET manufacturing method according to another embodiment of the present invention will be described with reference to FIG.

First, as shown in FIG. 4 (a), epitaxially grow a boron-doped p ^- silicon single crystal layer 30 on the p ^- type semiconductor substrate 20, and then n doped with phosphorus (P) thereon. ^-The silicon single crystal layer 21 is grown.

Subsequently, as shown in FIG. 4 (b), the same process as in the embodiment of FIG. 2 is performed to manufacture a MOSFET having an LDD structure.

The difference from the embodiment of FIG. 3 is that the p ^- silicon single crystal layer 30 is formed between the p-type semiconductor substrate 20 and the n ^- silicon single crystal layer 21 so that the transistor channel is extended by the p ^- silicon single crystal layer. It was made possible.

Next, referring to FIG. 5, a MOSFET manufacturing method according to still another embodiment of the present invention will be described.

As shown in Fig. 5 (a), after n ^- silicon single crystal layer 21 doped with phosphorus is epitaxially grown on the p-type semiconductor substrate 20, it is shown in Fig. 5 (b). As shown in the drawing, the n ⁻ silicon single crystal layer 21 in the channel region is selectively etched, and thus the exposed substrate portion is etched to a predetermined depth, and then the gate oxide film 23 is subjected to the same process as in the above embodiment. And a gate electrode 24 and the like are fabricated to form a MOSFET. As such, the substrate is partially etched so that the gate electrode is recessed below the substrate surface, thereby extending the channel length of the transistor.

As described above, in the present invention, since the gate pattern of the mast is used as the channel of the 100% transistor, the short channel effect and the hot carrier characteristics are remarkably improved.

In addition, since the n ^- LDD region is formed to overlap the gate electrode sufficiently, the sudden hot carrier degradation occurring at a certain voltage or more is improved, and the silicon single crystal layer having good uniformity and control characteristics of doping concentration is improved. And since it is used as a drain junction it is easy to control the characteristics of the transistor.

In addition, since the junction between the source and the drain and the substrate forms a planar junction, the breakdown voltage of the junction is significantly improved as compared with a junction having a bent portion.

In addition, by adding an n ^- silicon single crystal layer and a p ^- silicon single crystal layer on the substrate, the channel length of the transistor can be extended to facilitate the high integration of the device, and the gate electrode can be recessed by overetching the substrate. By extending the length, it is possible to obtain an element structure in which high integration is advantageous.

Claims (13)

A semiconductor substrate; A low-concentration silicon single crystal layer of opposite conductivity type to the substrate formed on the semiconductor substrate at predetermined intervals above the predetermined region; A gate insulating film formed over an upper region of the substrate between the low concentration silicon single crystal layer and the entire surface of the low concentration silicon single crystal layer; A gate electrode formed over an upper region of the substrate between the low concentration silicon single crystal layers and a predetermined region over the low concentration silicon single crystal layer; And a high concentration source and a drain formed on a surface of the low concentration silicon single crystal layer on both ends of the gate electrode and spaced apart from the gate electrode by a predetermined distance. The semiconductor device according to claim 1, wherein the low concentration silicon single crystal layer forms an LDD region. The semiconductor device according to claim 1, wherein the low concentration silicon single crystal layer and the gate electrode overlap each other by a predetermined distance. The semiconductor device according to claim 1, further comprising a low concentration silicon single crystal layer of the same conductivity type as the substrate between the semiconductor substrate and the low concentration silicon single crystal layer. The semiconductor device according to claim 1, wherein a substrate region between the low concentration silicon single crystal layers has a lower surface than other substrate regions. Epitaxially growing a low-concentration silicon single crystal layer opposite to the substrate on the semiconductor substrate, selectively etching the low-concentration silicon single crystal layer to expose a substrate portion of the transistor channel region, and exposing the low-concentration silicon single crystal layer and exposure Forming a gate insulating film on the substrate, forming a gate electrode on a predetermined region of the low-concentration silicon single crystal layer including the transistor channel region, forming a sidewall spacer on the side of the gate electrode, and the opposite of the substrate. Ion implantation at high concentration to form a high concentration source and drain junction on the surface of the low concentration silicon single crystal layer, forming an insulating film on the entire surface of the substrate, and performing an annealing process. A method of manufacturing a semiconductor device. The method of claim 6, wherein the low concentration silicon single crystal layer is a silicon single crystal layer doped with phosphorus (P). The method of claim 6, further comprising epitaxially growing a low-concentration silicon single crystal layer of the same conductivity type as that of the substrate before the step of epitaxially growing the low-concentration silicon single crystal layer on the semiconductor substrate. Method of manufacturing a semiconductor device. The method of claim 8, wherein the low-concentration silicon single crystal layer of the same conductivity type as the substrate is a boron-doped silicon single crystal layer. The semiconductor device of claim 6, further comprising selectively etching the low-concentration silicon single crystal layer to expose the substrate portion of the transistor channel region, and then etching the exposed substrate portion to a predetermined depth. Way. The method of claim 6, wherein the gate electrode is formed to overlap a predetermined length with the low concentration silicon single crystal layer across the channel region. 7. The method of claim 6, wherein an impurity of the low concentration silicon single crystal layer is automatically doped toward the substrate by the annealing process to form a source and a drain junction. The method of claim 6, after the annealing process, selectively removing the insulating layer to form a contact hole exposing the source and drain, and contacting the source and drain through the contact hole, respectively. Forming a source and drain electrode further comprising the step of manufacturing a semiconductor device.